Solid-state spark chamber for detection of radiation

Abstract

A combined semiconductor controlled circuit (CSCC) includes a semiconductor controlled switch (SCS). The SCS includes anode, cathode, anode gate and cathode gate terminals connected to P.sub.1 anode, N.sub.2 cathode, N.sub.1 anode gate and P.sub.2 cathode gate layers. The SCS also includes P-N junctions between P.sub.1 anode and N.sub.1 anode gate layers, N.sub.1 anode gate and P.sub.2 cathode gate layers and P.sub.2 cathode gate and N.sub.2 cathode layers. The CSCC also includes a Zener diode having a current path flowing from the cathode terminal to the anode gate terminal, a feedback resistor connecting cathode and cathode gate terminals and a substrate. A solid-state spark chamber includes a CSCC, a DC bias voltage source and an RC load having a parallel-connected load resistor and capacitor. The solid-state spark chamber also includes a plurality of measurement terminals and a ground. A method of making a solid-state spark chamber includes connecting the above components.

Claims

1. A combined semiconductor controlled circuit (CSCC) for detection of radiation, comprised of: a semiconductor controlled switch (SCS), wherein said SCS comprises an anode terminal connected to a P.sub.1 anode layer, a cathode terminal connected to an N.sub.2 cathode layer, an anode gate terminal connected to an N.sub.1 anode gate layer, and a cathode gate terminal connected to a P.sub.2 cathode gate layer wherein said SCS further comprises a first P-N junction between said P.sub.1 anode layer and said N.sub.1 anode gate layer, a second P-N junction between said N.sub.1 anode gate layer and said P.sub.2 cathode gate layer and a third P-N junction between said P.sub.2 cathode gate layer and said N.sub.2 cathode layer; a Zener diode having a path of current, wherein said Zener diode connects said cathode terminal and said anode gate terminal, wherein said path of current flows from said cathode terminal to said anode gate terminal; a feedback resistor, wherein said feedback resistor connects said cathode terminal and said cathode gate terminal; and a substrate.

2. The CSCC of claim 1, wherein said P.sub.1 anode layer is a P+ region surrounded by an N well, wherein said N.sub.2 cathode layer a N+ region surrounded by a P region surrounded by said N well, wherein said N.sub.1 anode gate layer is said N well, wherein said P.sub.2 cathode gate layer is said P region, wherein said substrate is a silicon substrate surrounding said N well, wherein said N.sub.1 layer further comprises an N+ contact region that contacts said anode gate terminal and said P.sub.2 layer further comprises a P+ contact region that contacts said cathode gate terminal.

3. The CSCC of claim 1, further comprising a control layer between said N.sub.1 anode gate layer and said P.sub.2 cathode gate layer, wherein said P.sub.1 anode layer is a P+ gallium arsenide (GaAs) layer, wherein said N.sub.2 cathode layer is said substrate, wherein said N.sub.1 anode gate layer is an N+ GaAs layer, wherein said P.sub.2 cathode gate layer is a P+ GaAs layer in direct contact with said substrate, wherein said control layer is an N GaAs layer, wherein said substrate is an N-doped GaAs substrate.

4. The CSCC of claim 1, wherein said P.sub.1 anode layer is a P+ GaAs layer in direct contact with said substrate, wherein said N.sub.2 cathode layer is an N+ GaAs layer, wherein said N.sub.1 anode gate layer is said substrate, wherein said P.sub.2 cathode gate layer is a P+ GaAs layer in direct contact with substrate, wherein said substrate is an N-doped GaAs substrate.

5. The CSCC of claim 1, wherein said N.sub.1 anode gate layer and said P.sub.2 cathode gate layer form a radiation interface directly exposed to a surrounding atmosphere.

6. The CSCC of claim 1, wherein said Zener diode is selected from the group consisting of: a diode with a quantum tunneling breakdown mechanism, a diode with an avalanche breakdown mechanism and diode with a combination of said quantum tunneling and avalanche breakdown mechanisms.

7. A solid-state spark chamber for detection of radiation, comprised of: a CSCC; a DC bias voltage source having a first bias terminal and a second bias terminal; an RC load having a first load terminal and a second load terminal, wherein said RC load comprises a load resistor and a load capacitor connected in parallel; a plurality of measurement terminals; and a ground, wherein said first bias terminal connects to an anode terminal of said CSCC, wherein said second bias terminal connects to said ground, wherein said first load terminal connects to a cathode terminal of said CSCC and to at least one of said plurality of measurement terminals, wherein said second load terminal connects to said ground and to another of said plurality of measurement terminals.

8. The solid-state spark chamber of claim 7, wherein said CSCC has a switching voltage V.sub.S based on a magnitude of an anode gate current I.sub.AG injected to an anode gate terminal of said CSCC.

9. The solid-state spark chamber of claim 8, wherein said DC bias voltage source has a bias voltage V.sub.B with a maximum voltage level V.sub.BM based on said switching voltage V.sub.S and a switching current I.sub.S.

10. The solid-state spark chamber of claim 7, wherein said load resistor has a resistance range R.sub.L based on a bias voltage V.sub.B, a switching voltage V.sub.S, a holding voltage V.sub.H, a holding current I.sub.H and a switching current I.sub.S.

11. The solid-state spark chamber of claim 7, wherein said load capacitor has a capacitance C.sub.L based on a switching time of said CSCC.

12. The solid-state spark chamber of claim 7, further comprising a photodetector connected between said ground and a cathode gate terminal of said CSCC.

13. The solid-state spark chamber of claim 12, wherein said photodetector is a silicon p-i-n diode.

14. The solid-state spark chamber of claim 12, wherein said photodetector is selected from the group consisting of: GaAs, germanium (Ge), cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe), gallium phosphide (GaP) or indium phosphide (InP) p-i-n diodes.

15. The solid-state spark chamber of claim 12, wherein said photodetector is removable and replaceable.

16. The solid-state spark chamber of claim 7, further comprising radiation shielding surrounding said DC bias voltage source, said RC load and said plurality of measurement terminals, wherein said radiation shielding is selected from the group consisting of: lead and cadmium.

17. A method of making a solid-state spark chamber for detection of radiation comprised of: connecting an anode terminal of a CSCC to a first bias terminal of a DC bias voltage source; connecting a second bias terminal of said DC bias voltage source to a ground; connecting a load resistor and a load capacitor in parallel to form an RC load; connecting a first load terminal of said RC load to a cathode terminal of a CSCC; connecting said first load terminal of said RC load to one of a plurality of measurement terminals; connecting a second load terminal of said RC load to said ground; connecting said second load terminal of said RC load to another of said plurality of measurement terminals.

18. The method of claim 17, further comprising connecting a photodetector between said ground and a cathode gate terminal of said CSCC.

19. The method of claim 18, further comprising: removing said photodetector, and replacing said photodetector with a different photodetector.

20. The method of claim 17, further comprising surrounding said DC bias voltage source, said RC load and said plurality of measurement terminals with radiation shielding.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a diagram of a CSCC in accordance with one embodiment of the invention.

(2) FIG. 2a illustrates a diagram of a SCS in accordance with one embodiment of the invention.

(3) FIG. 2b illustrates a diagram of a SCS in accordance with one embodiment of the invention.

(4) FIG. 2c illustrates a diagram of a SCS in accordance with one embodiment of the invention.

(5) FIG. 3 illustrates a circuit diagram of a solid-state spark chamber in accordance with one embodiment of the invention.

(6) FIG. 4 illustrates a circuit diagram of a solid-state spark chamber in accordance with one embodiment of the invention.

(7) FIG. 5 illustrates a process flow diagram of a method for making a solid-state spark chamber in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF INVENTION

(8) FIG. 1 illustrates a diagram of a CSCC 10 in accordance with one embodiment of the invention. CSCC 10 includes a SCS 20, a Zener diode 30 and a feedback resistor 40.

(9) SCS 20 includes a first P-N junction 21a, a second P-N junction 21b and a third P-N junction 21c. As used herein, the term P means a semiconductor having a larger hole concentration than electron concentration. As used herein, the term N means a semiconductor having a larger electron concentration than hole concentration. SCS 20 can switch from a high impedance state, also known as forward blocking mode, to a low impedance state, also known as a conduction mode.

(10) SCS 20 has a P.sub.1 anode layer 22a connected to an anode terminal 24a and an N.sub.2 cathode layer 22b connected to a cathode terminal 24b. SCS 20 also includes an N.sub.1 anode gate layer 22c connected to an anode gate terminal 24c and a P.sub.2 cathode gate layer 22d connected to a cathode gate terminal 24d. SCS 20 also includes a substrate 23. In one embodiment, N.sub.1 anode gate layer 22c and P.sub.2 cathode gate layer 22d form a radiation interface 25. During use, direct exposure of radiation interface 25 to the surrounding atmosphere permits detection of radiation.

(11) First P-N junction 21a is the interface between P.sub.1 anode layer 22a and N.sub.1 anode gate layer 22c. Second P-N junction 21b is the interface between N.sub.1 anode gate layer 22c and P.sub.2 cathode gate layer 22d. Third P-N junction 21c is the interface between P.sub.2 cathode gate layer 22d and N.sub.2 cathode layer 22b.

(12) Under low bias conditions, first P-N junction 21a and third P-N junction 21c are forward biased while second P-N junction 21b is reversed. SCS 20 is in forward blocking mode and second P-N junction 21b holds most of the voltage drop across SCS 20. When the bias increases, injected carriers from first P-N junction 21a and third P-N junction 21c collect in N.sub.1 anode gate layer 22c and P.sub.2 cathode gate layer 22d. The accumulation of charges reduces the potential drop within second P-N junction 21b, eventually forcing second P-N junction 21b to forward bias. The same effect occurs when injecting charges with correct polarity via anode gate terminal 24c and cathode gate terminal 24d. With first P-N junction 21a, second P-N junction 21b and third P-N junction 21c forward biased, SCS 20 switches to conduction mode.

(13) Switching time , the time required for SCS 20 to transition from forward blocking to conduction mode, is so low as to be essentially instantaneous. SCS 20 switches off when the current through SCS 20 falls below a holding current I.sub.H, the minimum current traveling from anode terminal 24a to cathode terminal 24b when SCS 20 is in conduction mode. Switching voltage V.sub.S is the voltage between anode terminal 24a and cathode terminal 24b when SCS 20 is about to switch from forward blocking to conduction mode. Switching voltage V.sub.S depends on the thicknesses and doping concentrations of P.sub.1 anode layer 22a, N.sub.2 cathode layer 22b, N.sub.1 anode gate layer 22c and P.sub.2 cathode gate layer 22d.

(14) Switching voltage V.sub.S can be controlled externally by anode gate current I.sub.AG, current injected to anode gate terminal 24c or cathode gate current I.sub.CG, current injected to cathode gate 24b. An increase in anode gate current I.sub.AG will increase switching voltage V.sub.S while an increase in cathode gate current I.sub.CG will decrease switching voltage V.sub.S.

(15) In one embodiment, using Zener diode 30 and feedback resistor 40 enables control of the transition characteristics of SCS 10. Zener diode 30 connects cathode terminal 24b and anode gate terminal 24c. Feedback resistor 40 connects cathode terminal 24b and cathode gate terminal 24d.

(16) Zener diode 30 connects cathode terminal 24b and anode gate terminal 24c to inject anode gate current I.sub.AG and set switching voltage V.sub.S. For Zener diode 30, the path of anode gate current I.sub.AG flows from cathode terminal 24b to anode gate terminal 24c. In various embodiments, Zener diode 30 may be a diode with a quantum tunneling breakdown mechanism, a diode with an avalanche breakdown mechanism or a diode with a combination of the quantum tunneling and avalanche breakdown mechanisms.

(17) Feedback resistor 40 connects cathode terminal 24b and cathode gate terminal 24d to set switching current I.sub.S and holding current I.sub.H. Switching current I.sub.S is the current traveling from anode terminal 24a to cathode terminal 24b when SCS 20 is about to switch from forward blocking to conduction mode. Lowering switching voltage V.sub.S or holding current I.sub.H makes SCS 10 switch its state with only a small amount of charge injected to anode gate terminal 24c. This increases sensitivity to radiation.

(18) Various embodiments of CSCC 10 incorporate various embodiments of SCS 20. These various embodiments of SCS 20 may be optimized to function in CSCC 10. FIGS. 2a-2c illustrate these various embodiments of SCS 20.

(19) FIG. 2a illustrates a diagram of SCS 20 in accordance with one embodiment of the invention. In the embodiment of FIG. 2a, P.sub.1 anode layer 22a is a P+ region inside of a N well, while N.sub.2 cathode layer 22b is a N+ region inside of a P region inside of the previously mentioned N well. As used herein, the term well indicates a semiconductor region fabricated to form a physical barrier between a substrate and one or more semiconductor regions. As used herein, the designation + indicates a semiconductor, either P or N, having a high doping concentration. As previously mentioned, P.sub.1 anode layer 22a connects to anode terminal 24a and N.sub.2 cathode layer 22b connects to cathode terminal 24b. N.sub.1 anode gate layer 22c is the previously mentioned N well and P.sub.2 cathode gate layer 22d is the previously mentioned P region. N.sub.1 anode gate layer 22c also includes an N+ contact region 26a that contacts anode gate terminal 24c. P.sub.2 cathode gate layer 22d also includes a P+ contact region 26b that contacts cathode gate terminal 24d. Substrate 23 is a silicon substrate. This configuration is based on standard CMOS processing technology. During use, radiation exposure typically occurs in second P-N junction 21b.

(20) FIG. 2b illustrates a diagram of SCS 20 in accordance with one embodiment of the invention. In the embodiment of FIG. 2b, P.sub.1 anode layer 22a is a P+ gallium arsenide (GaAs) layer, while N.sub.2 cathode layer 22b is substrate 23, an N-doped GaAs substrate. N.sub.1 anode gate layer 22c is an N+ GaAs layer and P.sub.2 cathode gate layer 22d is a P+ GaAs layer in direct contact with substrate 23. As previously mentioned, P.sub.1 anode layer 22a connects to anode terminal 24a, N.sub.2 cathode layer 22b connects to cathode terminal 24b, N.sub.1 anode gate layer 22c connects to anode gate terminal 24c and P.sub.2 cathode gate layer 22d connects to cathode gate terminal 24d. Substrate 23 is an N-doped GaAs substrate. During use, radiation exposure typically occurs in P.sub.2 cathode gate layer 22d. The embodiment of FIG. 2b also includes a control layer 27 located between N.sub.1 anode gate layer 22c and P.sub.2 cathode gate layer 22d. Control layer 27 is an N GaAs layer. As used herein, the designation indicates a semiconductor, either P or N, having a low doping concentration. Control layer 27 allows further control of the current and voltage characteristics of SCS 20.

(21) FIG. 2c illustrates a diagram of SCS 20 in accordance with one embodiment of the invention. In the embodiment of FIG. 2c, P.sub.1 anode layer 22a is a P+ GaAs layer in direct contact with substrate 23, while N.sub.2 cathode layer 22b is an N+ GaAs layer. N.sub.1 anode gate layer 22c is substrate 23, an N-doped GaAs substrate and P.sub.2 cathode gate layer 22d is a P+ GaAs layer in direct contact with substrate 23. As previously mentioned, P.sub.1 anode layer 22a connects to anode terminal 24a, N.sub.2 cathode layer 22b connects to cathode terminal 24b, N.sub.1 anode gate layer 22c connects to anode gate terminal 24c and P.sub.2 cathode gate layer 22d connects to cathode gate terminal 24d. Substrate 23 is an N-doped GaAs substrate. During use, radiation exposure typically occurs in substrate 23, allowing a larger area for radiation detection.

(22) FIG. 3 illustrates a circuit diagram of a solid-state spark chamber 100 in accordance with one embodiment of the invention. Solid-state spark chamber 100 includes CSCC 10, a DC bias voltage source 50, an RC load 60, a plurality of measurement terminals 70a and 70b and a ground 75.

(23) DC bias voltage source 50 connects to anode terminal 24a at a first bias terminal 51 and to ground 75 at a second bias terminal 52. DC bias voltage source 50 provides a bias voltage V.sub.B, a steady-state voltage, with a maximum voltage level V.sub.BM given by the equation
V.sub.BM=V.sub.S+(I.sub.S*R.sub.L)
where R.sub.L is a load resistance of RC load 60. The increase of bias voltage V.sub.B towards maximum voltage level V.sub.BM will increase the sensitivity of solid-state spark chamber 100 to radiation.

(24) RC load 60 connects to cathode terminal 24b at a first load terminal 61 and to ground 75 at a second load terminal 64. RC load 60 includes a load resistor 62 and a load capacitor 63 connected in parallel.

(25) Load resistor 62 has load resistance R.sub.L range determined by the expression

(26) $\frac{V_B-V_S}{I_S}>R_L>\frac{V_B-V_H}{I_H}$
where V.sub.H is a holding voltage, the minimum voltage between anode terminal 24a and cathode terminal 24b when SCS 20 is in conduction mode.

(27) Load capacitor 63 has a load capacitance C.sub.L resulting in an impedance of approximately 1 ohm. Load capacitance C.sub.L is determined by the equation

(28) $1~\frac{}{2C_L}$

(29) Measurement terminals 70a and 70b connect to first load terminal 61 and second load terminal 64, respectively. An output voltage V.sub.O measured across measurement terminals 70a and 70b provides voltage pulse V.sub.P corresponding to detection of radiation. Voltage pulse V.sub.P is a pulse with a base level given by the equation
V.sub.P=V.sub.BI.sub.S*R.sub.L
Altering bias voltage V.sub.B controls the rate of voltage pulses V.sub.P. In addition, sending a current via anode gate terminal 24c or cathode gate terminal 24d can also control the rate of voltage pulses V.sub.P.

(30) FIG. 4 illustrates a circuit diagram of a solid-state spark chamber 200 in accordance with one embodiment of the invention. The configurations, components and functions of CSCC 210, DC bias voltage source 250, RC load 260, measurement terminals 270a and 270b and ground 275 of FIG. 4 are substantially identical in form and function to their counterparts in the embodiment illustrated in FIG. 3.

(31) The embodiment of FIG. 4 also includes a photodetector 280 and optional radiation shielding 290. Connecting photodetector 280 between cathode gate terminal 224d and ground 275 increases the volume of solid-state spark chamber 200 exposed to radiation, thereby increasing the sensitivity of solid-state spark chamber 200. Injecting a charge generated by exposing photodetector 280 to radiation into second P-N junction 221b emulates an expansion of the volume of SCS 220.

(32) In the embodiment of FIG. 4, photodetector 280 is a silicon p-i-n diode. As used herein, the term p-i-n diode means a diode with an undoped semiconductor region between a P-type semiconductor region and an N-type semiconductor region. In other embodiments, photodetector 280 is a GaAs, germanium (Ge), cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe), gallium phosphide (GaP) or indium phosphide (InP) p-i-n diode. The heavier materials of these other photodetectors 280 provide greater sensitivity to beta and gamma radiation. In certain embodiments, photodetector 280 is removable, allowing a user to replace one photodetector 280 with another.

(33) Radiation shielding 290 may attenuate radiation, allowing interaction to occur within a specific, active volume of solid-state spark chamber 200, namely SCS 220 and/or photodetector 280. This prevents radiation from damaging or interfering with the operation of other elements of solid-state spark chamber 200.

(34) FIG. 5 illustrates a process flow diagram of a method 300 for making solid-state spark chamber 100 or 200 in accordance with one embodiment of the invention.

(35) In operation 302, method 300 connects anode terminal 24a/224a of CSCC 10/210 to first bias terminal 51/251 of DC bias voltage source 50/250.

(36) In operation 304, method 300 connects second bias terminal 52/252 of DC bias voltage source 50/250 to ground 75/275.

(37) In operation 306, method 300 connects load resistor 62/262 and load capacitor 63/263 in parallel to form RC load 60/260.

(38) In operation 308, method 300 connects first load terminal 61/261 of RC load 60/260 to cathode terminal 24b/224b of CSCC 10/210.

(39) In operation 310, method 300 connects first load terminal 61/261 of RC load 60/260 to one of measurement terminals 70a/270a and 70b/270b.

(40) In operation 312, method 300 connects second load terminal 64/264 of RC load 60/260 to ground 75/275.

(41) In operation 314, method 300 connects second load terminal 64/264 of RC load 60/260 to another of measurement terminals 70a/270a and 70b/270b.

(42) In optional operation 316, method 300 connects photodetector 280 between ground 275 and cathode gate terminal 224d of CSCC 210.

(43) In optional operation 318, method 300 removes photodetector 280.

(44) In optional operation 320, method 300 replaces photodetector 280 with a different photodetector 280. This operation allows the use of multiple photodetectors 280 having different properties within the same solid-state spark chamber 200.

(45) In optional operation 322, method 300 surrounds DC bias voltage source 250, RC load 260 and measurement terminals 270a and 270b with radiation shielding 290.

(46) It will be understood that many additional changes in the details, materials, procedures and arrangement of parts, which have been herein described and illustrated to explain the nature of the invention, may be made by those skilled in the art within the principle and scope of the invention as expressed in the appended claims.