SINGLE-ENDED TO DIFFERENTIAL CONVERSION CIRCUIT AND SIGNAL PROCESSING MODULE

Abstract

A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

Claims

1. A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals, comprising: an amplifier, comprising an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal; a first resistor coupled between the inverting input terminal and the output terminal of the amplifier; a second resistor coupled to the inverting input terminal of the amplifier, wherein the inverting input terminal of the amplifier receives the input signal via the second resistor; a third resistor coupled to the output terminal of the amplifier; and a resistor string coupled between the output terminal of the amplifier and the second resistor, comprising a fourth resistor and a fifth resistor connected in series, wherein a signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

2. The single-ended to differential conversion circuit as claimed in claim 1, further comprising: a sixth resistor coupled to the second resistor and the resistor string, receiving the input signal, wherein the second resistor is coupled between the sixth resistor and the inverting input terminal of the amplifier, and the fifth resistor is coupled between the sixth resistor and the fourth resistor.

3. The single-ended to differential conversion circuit as claimed in claim 1, wherein the sum of a first current flowing through the fifth resistor and a second current flowing through the fourth resistor is equal to a third current flowing through the third resistor.

4. The single-ended to differential conversion circuit as claimed in claim 1, wherein common mode output impedances of the single-ended to differential conversion circuit are equal.

5. The single-ended to differential conversion circuit as claimed in claim 1, wherein differential mode output impedances of the single-ended to differential conversion circuit are equal.

6. The single-ended to differential conversion circuit as claimed in claim 1, wherein the resistance of the fifth resistor is R, the resistance of the fourth resistor is nR , the resistance of the second resistor is xR, the resistance of the first resistor is yR, and the resistance of the third resistor is $\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}R.$

7. The single-ended to differential conversion circuit as claimed in claim 1, wherein the reference signal has a constant voltage value.

8. A signal processing module, comprising: a differential signal processing circuit, providing a pair of differential output signals according to a pair of differential intermediate signals, comprising: a fully-differential amplifier; and a single-ended to differential conversion circuit, converting an input signal into the pair of differential intermediate signals, and comprising: an amplifier, comprising an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal; a first resistor coupled between the inverting input terminal and the output terminal of the amplifier; a second resistor coupled to the inverting input terminal of the amplifier, wherein the inverting input terminal of the amplifier receives the input signal via the second resistor; a third resistor coupled between the output terminal of the amplifier and a non-inverting input terminal of the fully-differential amplifier; a fourth resistor coupled between the output terminal of the amplifier and an inverting input terminal of the fully-differential amplifier; and a fifth resistor coupled between the second resistor and the inverting input terminal of the fully-differential amplifier.

9. The signal processing module as claimed in claim 8, wherein an intermediate signal of the pair of differential intermediate signals is provided to the non-inverting input terminal of the fully-differential amplifier via the third resistor, and another intermediate signal of the pair of differential output signals is provided to the inverting input terminal of the fully-differential amplifier via the fourth and fifth resistors.

10. The signal processing module as claimed in claim 8, wherein the single-ended to differential conversion circuit further comprises: a sixth resistor coupled to the second resistor and the fifth resistor, receiving the input signal, wherein the second resistor is coupled between the sixth resistor and the inverting input terminal of the amplifier, and the fifth resistor is coupled between the sixth resistor and the fourth resistor.

11. The signal processing module as claimed in claim 8, wherein the sum of a first current flowing through the fifth resistor and a second current flowing through the fourth resistor is equal to a third current flowing through the third resistor.

12. The signal processing module as claimed in claim 8, wherein common mode output impedances of the single-ended to differential conversion circuit are equal.

13. The signal processing module as claimed in claim 8, wherein differential mode output impedances of the single-ended to differential conversion circuit are equal.

14. The signal processing module as claimed in claim 8, wherein the resistance of the fifth resistor is R, the resistance of the fourth resistor is nR, the resistance of the second resistor is xR, the resistance of the first resistor is yR, and the resistance of the third resistor is $\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}R.$

15. The signal processing module as claimed in claim 8, wherein the reference signal has a constant voltage value.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0010] The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

[0011] FIG. 1 shows a signal processing module according to an embodiment of the invention; and

[0012] FIG. 2 shows a signal processing module according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0013] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0014] FIG. 1 shows a signal processing module 100 according to an embodiment of the invention. The signal processing module 100 comprises a single-ended to differential conversion circuit 110 and a differential signal processing circuit 120. The single-ended to differential conversion circuit 110 is capable of converting a single-ended input signal into a pair of intermediate signals (labeled as the differential current signals I.sub.CM+I.sub.SIG and I.sub.CMI.sub.SIG, wherein I.sub.CM represents the DC component and I.sub.SIG represents the AC component). In some embodiments, the pair of intermediate signals may be the voltage signals, and the single-ended to differential conversion circuit 110 is capable of converting the single-ended input signal into the voltages (e.g. the differential voltage signals V.sub.CM+V.sub.SIG and V.sub.CMV.sub.SIG) corresponding to the pair of intermediate signals. The differential signal processing circuit 120 is capable of processing the pair of intermediate signals and providing a pair of differential output signals OUT.sub.P/OUT.sub.N according to the pair of intermediate signals (e.g. I.sub.CM+I.sub.SIG and I.sub.CMI.sub.SIG). For example, in some embodiments, the differential signal processing circuit 120 amplifies the pair of intermediate signals (e.g. I.sub.CM+I.sub.SIG and I.sub.CMI.sub.SIG) to obtain the pair of differential output signals OUT.sub.P/OUTN. As another example, in some embodiments, the differential signal processing circuit 120 modifies the pair of intermediate signals (e.g. I.sub.CM+I.sub.SIG, I.sub.CMI.sub.SIG) according to a modification signal (not shown) to obtain the pair of differential output signals OUT.sub.P/OUT.sub.N. It should be noted that the operation of the differential signal processing circuit 120 is used as an example, and not to limit the invention.

[0015] FIG. 2 shows a signal processing module 200 according to another embodiment of the invention. The signal processing module 200 comprises a single-ended to differential conversion circuit 210 and a differential signal processing circuit 220. The single-ended to differential conversion circuit 210 is capable of converting a single-ended input signal V.sub.CM+V.sub.IN into a pair of differential intermediate signals. In the embodiment, the pair of differential intermediate signals are a pair of differential current signals (e.g. the current (I.sub.P1+I.sub.P2) at the node n2 and the currentI.sub.N at the node n3 in FIG. 2). It should be noted that, V.sub.CM may represent a DC voltage, and V.sub.IN may represent an AC component containing the AC voltage. For example, when V.sub.CM=0V, V.sub.IN can be used to represent a pure AC signal without a DC component. Of course, V.sub.IN can also be used to represent an AC signal with a DC component. In particular, the embodiments are used as the examples, and not to limit the invention. In the embodiment, the single-ended to differential conversion circuit 210 comprises an amplifier 230 (as shown in FIG. 2, the amplifier 230 is a single-ended amplifier), and six resistors R1-R6. In some embodiments, the resistor R6 could be omitted. In other words, the resistor R6 is optional. The differential signal processing circuit 220 comprises a fully-differential amplifier 240, and two feedback units 250 and 260. The feedback unit 250 is coupled between an inverting input terminal and a non-inverting output terminal of the fully-differential amplifier 240, and the feedback unit 260 is coupled between a non-inverting input terminal and an inverting output terminal of the fully-differential amplifier 240. In some embodiments, the differential signal processing circuit 220 further comprises two input units (not shown), wherein one input unit is coupled between the inverting input terminal of the fully-differential amplifier 240 and a node n2 of the single-ended to differential conversion circuit 210 (for example, between one differential output terminal of the single-ended to differential conversion circuit 210 and the inverting input terminal of the fully-differential amplifier 240), and another input unit is coupled between the non-inverting input terminal of the fully-differential amplifier 240 and the resistor R3 of the single-ended to differential conversion circuit 210 (for example, between the other differential output terminal of the single-ended to differential conversion circuit 210 and the non-inverting input terminal of the fully-differential amplifier 240). Thus, a gain is determined according to the input units and the feedback units 250 and 260 for the fully-differential amplifier 240. In practice, if the fully-differential amplifier 240 is an ideal amplifier, the input voltages of its inverting input terminal and its non-inverting input terminal are equal. If the fully-differential amplifier 240 is a non-ideal amplifier, the input voltages of its inverting input terminal and its non-inverting input terminal are the differential voltages. In the embodiment, no matter whether the fully-differential amplifier 240 is an ideal amplifier, the two input currents of the fully-differential amplifier 240 are the differential currents. Therefore, in the embodiment, for the convenience of explanation, the differential intermediate signals are the differential current signals, and the fully-differential amplifier 240 is an ideal amplifier 240. It should be noted that the specific type of the fully-differential amplifier 240 is used as an example, and not to limit the invention. The reason is that, for a particular type of fully-differential amplifier 240, the fully-differential amplifier 240 will automatically adjust the voltages of its input terminals, such that the voltages of the input terminals can meet the objective requests of the particular type of fully-differential amplifier. In the embodiment, for the convenience of description, the voltages of two input terminals of the fully-differential amplifier 240 are maintained at the voltage V.sub.CM (i.e. the voltage V.sub.n2 of the node n2 and the voltage V.sub.n3 of the node n3 are equal to the voltage V.sub.CM, e.g. V.sub.n2=V.sub.n3=V.sub.CM), and it should be noted that the invention is not limited thereto.

[0016] In the single-ended to differential conversion circuit 210 of FIG. 2, the amplifier 230 has an inverting input terminal coupled to a terminal of the resistor R1 and a terminal of the resistor R2, a non-inverting input terminal for receiving a reference signal V.sub.ref, and an output terminal coupled to another terminal of the resistor R1, a terminal of the resistor R3, and a terminal of the resistor R4. In some embodiments, the reference signal V.sub.ref has a constant voltage value. For example, the voltage level of the reference signal V.sub.ref is equal to that of the DC voltage V.sub.CM. For convenience of description, the reference signal V.sub.ref is equal to that the DC voltage V.sub.CM in the embodiment, and it should be noted that the invention is not limited to this. Because, if the voltage level of the DC voltage V.sub.CM is not equal to that of the reference signal V.sub.ref, V can be replaced by (V.sub.CMV.sub.ref+V.sub.IN). Thus, based on the following embodiments, the resistance value of the resistor R3, and the equivalent impedance of the single-ended to differential conversion circuit 210 can be obtained accordingly. The resistor R6 is coupled to a node n1, and the resistor R6 is an input resistor for receiving the input signal V.sub.IN. The resistor R2 is coupled between the node n1 and the inverting input terminal of the amplifier 230, and the inverting input terminal of the amplifier 230 can receive the input signal V.sub.IN via the resistor R2. The resistor R1 is coupled between the inverting input terminal and the output terminal of the amplifier 230. The resistor R3 is coupled between the output terminal of the amplifier 230 and the non-inverting input terminal of the fully-differential amplifier 240. The resistor R4 is coupled between the output terminal of the amplifier 230 and the node n2. The resistor R5 is coupled between the node n2 and the node n1. Furthermore, the resistors R4 and R5 form a resistor string coupled between the node n1 and the output terminal of the amplifier 230. In some embodiments, the resistance value of the resistor R3 is determined according to the resistors R1, R2, R4 and R5.

[0017] In one embodiment, the resistance (or impedance) of the resistor R5 is R, which is a unit resistance for the single-ended to differential conversion circuit 210. The resistance of the resistor R6 is mR. The resistance of the resistor R2 is xR. The resistance of the resistor R1 is yR. The resistance of the resistor R4 is nR. According to the resistances of the resistors R1, R2, R4 and R5, the resistance of the resistor R3 is obtained according to the following formula (1):

[00001]$\begin{array}{cc}R.Math..Math.3=\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}R.& \left(1\right)\end{array}$

[0018] Furthermore, according to a virtual ground concept of circuit analysis in operational amplifier, the nodes at the non-inverting input terminal and inverting input terminal of the amplifier 230, and the nodes at the non-inverting input terminal and inverting input terminal of the fully-differential amplifier 240 are maintained at a steady reference potential (i.e. a virtual ground). Thus, a voltage V.sub.n1 at the node n1 is obtained according to the following formula (2):

[00002]$\begin{array}{cc}{V}_{n.Math..Math.1}=V_{\mathrm{CM}}+V.Math..Math.1=V_{\mathrm{CM}}+\frac{\frac{x}{1+x}}{m+\frac{x}{1+x}}{V}_{\mathrm{IN}},& \left(2\right)\end{array}$

wherein

[00003]$V.Math..Math.1+\frac{\frac{x}{1+x}}{m+\frac{x}{1+x}}{V}_{\mathrm{IN}}.$

[0019] Furthermore, according to the voltage V.sub.n1 at the node n1, and the resistors R1 and R2, a voltage V2 at the output terminal of the amplifier 230 is obtained according to the following formula (3):

[00004]$\begin{array}{cc}V.Math..Math.1=V_{\mathrm{CM}}-\frac{y}{x}V.Math..Math.1.& \left(3\right)\end{array}$

[0020] According to the voltages V.sub.n1, V.sub.n2 and V2, the current I.sub.p1 flowing through the resistor R5, the current I.sub.p2 flowing through the resistor R4, and current I.sub.N flowing through the resistor R3 are respectively obtained according to the following formulas (4)-(6):

[00005]$\begin{array}{cc}{I}_{P.Math..Math.1}=-\frac{V_1}{R};& \left(4\right)\\ I_{P.Math..Math.2}=\frac{\frac{y}{x}V.Math..Math.1}{n.Math.R};\mathrm{and}& \left(5\right)\\ I_N=\frac{\frac{y}{x}V.Math..Math.1}{\frac{\frac{y}{x}R}{1-\frac{y}{x}.Math.\frac{1}{n}}}=\left(1-\frac{y}{n}.Math.\frac{1}{n}\right)\frac{V_1}{R}=-\left(I_{P.Math..Math.1}+I_{P.Math..Math.2}\right).& \left(6\right)\end{array}$

[0021] From the formulas (4) - (6), by appropriately setting the resistance value of the resistor R3, the output currents of the single-ended to differential conversion circuit 210 are always a pair of differential signals based on the architecture shown in FIG. 2, i.e. I.sub.N=(I.sub.P1+I.sub.P2). Furthermore, by determining the relationship between the voltage/current of the inverting input terminal and the voltage/current of the non-inverting input terminal of the fully-differential amplifier 240, a common mode or a differential mode is determined for the signal processing module 200, so as to estimate the common mode or differential mode perturbations for the pair of intermediate signals, and then the equivalent impedance R.sub.EQ.sub._.sub.P observed at the inverting input terminal of the fully-differential amplifier 240 (in other words, observing the single-ended to differential conversion circuit 210 from the inverting input terminal of the fully-differential amplifier 240) and the equivalent impedance R.sub.EQ.sub._.sub.N observed at the non-inverting input terminal of the fully-differential amplifier 240 are obtained (in other words, observing the single-ended to differential conversion circuit 210 from the non-inverting input terminal of the fully-differential amplifier 240). In some embodiments, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ_N may be set to the same. In some embodiments, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are the output impedances for the single-ended to differential conversion circuit 210.

[0022] In order to calculate the output impedances, the voltages V.sub.CM+V.sub.P and V.sub.CM+V.sub.N are applied to the output terminals of the single-ended to differential conversion circuit 210, without receiving the single-ended input signal at its input terminal. For example, in order to calculate the common mode output impedances of the single-ended to differential conversion circuit 210), the voltage V.sub.CM+V.sub.P applied to the inverting input terminal and the voltage V.sub.CM+V.sub.N applied to the non-inverting input terminal of the fully-differential amplifier 240 are assumed to be the same, i.e. Vp=V.sub.P=V.sub.N. Furthermore, in a common mode, if the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are equal, a current from the inverting input terminal of the fully-differential amplifier 240 to the single-ended to differential conversion circuit 210 is equal to a current from the non-inverting input terminal of the fully-differential amplifier 240 to the single-ended to differential conversion circuit 210, i.e. I.sub.P1+I.sub.P2=I.sub.N. Thus, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are obtained according to the following formulas (7)-(8):

[00006]$\begin{array}{cc}{R}_{\mathrm{EQ\_P}}=\frac{1}{1+\frac{m.Math.x}{m+x}}+\frac{1}{n}.Math.\left(1+\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}\right);\mathrm{and}& \left(7\right)\\ R_{\mathrm{EQ\_N}}=\frac{1+\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}}{\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}}.& \left(8\right)\end{array}$

When

[0023] [00007]$\frac{1}{1+\frac{m.Math.x}{m+x}}+\frac{1}{n}.Math.\left(1+\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}\right)=\frac{1+\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}}{\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}}$

is satisfied, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are the same in the common mode.

[0024] Correspondingly, in order to calculate the differential mode output impedances of the single-ended to differential conversion circuit 210, the voltage V.sub.CM+V.sub.P applied to the inverting input terminal and the voltage V.sub.CM+V.sub.N applied to the non-inverting input terminal of the fully-differential amplifier 240 are the differential signals, e.g. V.sub.P=V.sub.N. Furthermore, in a differential mode, if the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are equal, a current from the single-ended to differential conversion circuit 210 to the inverting input terminal of the fully-differential amplifier 240 is equal to a current from the non-inverting input terminal of the fully-differential amplifier 240 to the single-ended to differential conversion circuit 210, i.e. I.sub.P1+I.sub.P2=I.sub.N. Thus, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are obtained according to the following formulas (9)-(10):

[00008]$\begin{array}{cc}{R}_{\mathrm{EQ\_P}}=\frac{1}{1+m.Math..Math.x}+\frac{1}{n}.Math.\left(1+\frac{y}{x}.Math.\frac{m.Math..Math.x}{1+m.Math..Math.x}\right);\mathrm{and}& \left(9\right)\\ R_{\mathrm{EQ\_N}}=\frac{1-\frac{y}{x}.Math.\frac{m.Math..Math.x}{1+m.Math..Math.x}}{\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}}.& \left(10\right)\end{array}$

When

[0025] [00009]$\frac{1}{1+\frac{m.Math.x}{m+x}}+\frac{1}{n}.Math.\left(1+\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}\right)=\frac{1-\frac{y}{x}.Math.\frac{\frac{m.Math.x}{m+x}}{1+\frac{m.Math.x}{m+x}}}{\frac{\frac{y}{x}}{1-\frac{y}{x}.Math.\frac{1}{n}}}$

When is satisfied, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are the same in the differential mode.

[0026] It should be noted that if the common-mode output impedances or the differential mode output impedances are respectively equal, the absolute value of the sum of the currents I1 and I2 is equal to the absolute value of the current I3, i.e. |I.sub.P1+I.sub.P2|=|I.sub.N|. Furthermore, according to actual application, the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N can be obtained for a common mode or a differential mode perturbation. Typically, it can not meet that the common-mode equivalent impedances and the differential-mode equivalent impedances are respectively equal. Specifically, according to actual requirements, it is possible to set that the common-mode equivalent impedances are equal or the differential-mode equivalent impedances are equal, and the invention does not make this any limitation. For example, since the circuit (e.g. the single-ended to differential conversion circuit 110) disposed in front of the differential signal processing circuit 120 usually has a common-mode noise, the common-mode noise can be cancelled between the two differential input terminals of the fully-differential amplifier 240 by setting the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are the same in the common mode, thereby decreasing noise. For another example, by setting the equivalent impedances R.sub.EQ.sub._.sub.P and R.sub.EQ.sub._.sub.N are the same in the differential mode, distortion is decreased in the applications with a differential mode feedback.

[0027] By adding the resistor R4 between the node n2 and the output terminal of the amplifier 230, only a single single-ended amplifier (i.e. the amplifier 230) is used in the single-ended to differential conversion circuit 210. Thus, compared with the conventional single-ended to differential conversion circuits (e.g. using two single-ended amplifiers solution, or a fully-differential amplifier solution, and so on), the layout area and the power consumption are decreased in the single-ended to differential conversion circuit 210. Furthermore, trade-off between the input magnitude of the single-ended input signal and the performance of the amplifier 230 can be optimized. With the introduction of the resistor R4 (e.g. a resistance of nR), the equivalent input is scaled by 1-1/n (n>1), and the non-idealities of the amplifier 230 can be cancelled to be |1/n(1(y/x)(1/n))/(y/x)|. For example, assuming that the resistors R1 and R2 are equal to the resistor R5 (i.e. x=y=1) and the resistor R4 is twice as big as the resistor R5 (i.e. n=2), the noise and distortion caused by the amplifier 230 can be cancelled completely. Specifically, the noise and distortion caused by the amplifier 230 can be decreased by appropriately controlling the ratio of the resistors R1, R2, R4 and R5. It should be noted that, x, y, m and n of the embodiments are not limited to an integer.

[0028] While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.