Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit

Abstract

An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.

Claims

1. A process for producing a contact on an active zone of an integrated circuit, the active zone lying above a semiconductor substrate, comprising: forming an insulating multilayer above said active zone and in and above a cavity bordering the active zone and extending, in an insulating zone, into a vicinity of a semiconductor region, wherein forming comprises: forming a first insulating layer covering the active zone and lining the walls of the cavity; and forming an insulating region on top of the first insulating layer; etching a portion of the insulating multilayer so as to define an orifice opening onto the active zone and into the cavity; and filling the orifice with an electrically conductive filling material; wherein forming said insulating region comprises, after the first insulating layer has been formed: forming an additional insulating layer configured to prevent, during said etching operation, a segment of the first insulating layer lining the walls of the cavity and located in proximity to said semiconductor region from being pierced.

2. The process according to claim 1, wherein forming the insulating region comprises: filling the cavity with a first insulating material covering the portion of the first insulating layer lining the walls of the cavity, forming the additional insulating layer covering the first insulating layer and the first insulating material; and forming a second insulating layer on the additional insulating layer.

3. The process according to claim 2, wherein etching comprises: performing a first etch of the second insulating layer stopped on the additional insulating layer, and then performing a second etch configured to etch: the additional insulating layer and the subjacent first insulating layer so as to expose the active zone, and the additional insulating layer and a subjacent portion of the first insulating material located in said cavity, without piercing said segment of the first insulating layer.

4. The process according to claim 2, wherein a material of the additional insulating layer is identical to a material of the first insulating layer.

5. The process according to claim 1, wherein a thickness of the additional insulating layer is between 5 and 20 nanometers.

6. The process according to claim 1, wherein forming the insulating region comprises: forming the additional insulating layer to cover the portion of the first insulating layer lining the walls of the cavity, the additional insulating layer being configured to be selectively etchable relative to the first insulating layer, filling the cavity with a first insulating material covering the additional insulating layer; and forming a second insulating layer on the first insulating material.

7. The process according to claim 6, wherein etching comprises: performing a first etch of the second insulating layer stopped on the portion of the first insulating layer located above the active zone and on the additional insulating layer, and then performing a second selective etch configured to etch said portion of the first insulating layer located above the active zone, so as to expose the active zone without etching the additional insulating layer.

8. The process according to claim 6, wherein the first insulating layer comprises a silicon nitride and the additional insulating layer comprises a high dielectric constant oxide.

9. The process according to claim 1, wherein said semiconductor substrate is a semiconductor film borne by a buried insulating layer itself borne by a carrier substrate, said buried insulating layer comprising at least one portion of said insulating zone, said semiconductor region being a portion of said carrier substrate.

10. A process, comprising: producing an insulating multilayer above an active zone of an integrated circuit, the active zone lying above a semiconductor substrate; forming a cavity bordering the active zone; depositing an insulating multilayer above said active zone and in and above said cavity, wherein depositing comprises: depositing a first insulating layer covering the active zone and lining the walls of the cavity; and depositing a second insulating layer on top of the first insulating layer; etching a portion of the insulating multilayer so as to define an orifice opening onto the active zone and into the cavity; and filling the orifice with an electrically conductive filling material; wherein said second insulating layer protects a segment of the first insulating layer lining the walls of the cavity and located in proximity to said semiconductor region from being pierced by said etching.

11. The process according to claim 10, wherein depositing the second insulating layer comprises: filling the cavity with a first insulating material covering the portion of the first insulating layer lining the walls of the cavity, forming an additional insulating layer covering the first insulating layer and the first insulating material; and forming a further insulating layer on the additional insulating layer.

12. The process according to claim 11, wherein etching comprises: performing a first etch of the further insulating layer stopping on the additional insulating layer, and then performing a second etch to remove the additional insulating layer and the subjacent first insulating layer in said cavity so as to expose the active zone without piercing said segment of the first insulating layer.

13. The process according to claim 11, wherein a material of the additional insulating layer is identical to a material of the first insulating layer.

14. The process according to claim 10, wherein a thickness of the additional insulating layer is between 5 and 20 nanometers.

15. The process according to claim 10, wherein the second insulating layer covers the portion of the first insulating layer lining the walls of the cavity, the second insulating layer being selectively etchable relative to the first insulating layer, further comprising: filling the cavity with a first insulating material covering the second insulating layer; and forming a further insulating layer on the first insulating material.

16. The process according to claim 15, wherein etching comprises: performing a first etch of the further insulating layer stopping on the portion of the first insulating layer located above the active zone and on the second insulating layer, and then performing a second selective etch configured to etch said portion of the first insulating layer located above the active zone, so as to expose the active zone without etching the second insulating layer.

17. The process according to claim 15, wherein the first insulating layer comprises a silicon nitride and the second insulating layer comprises a high dielectric constant oxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely nonlimiting methods of implementation and embodiments thereof and the appended drawings, in which:

(2) FIGS. 1 to 35 schematically illustrate methods of implementation and embodiments.

DETAILED DESCRIPTION

(3) FIG. 1 schematically illustrates a top view of one portion of an integrated circuit IC comprising an active zone ZA here flanked by two polysilicon lines LP.

(4) The active zone ZA may be a source or drain zone of a transistor the polysilicon line LP of which, located on the left in FIG. 1, then forms a gate region. In this case, another active zone will be present located on the other side of the polysilicon line LP and forming the drain or source region of the transistor.

(5) This being so, generally, the active zone ZA may be any active zone, for example a zone allowing a contact to be made with a view to biasing the subjacent substrate.

(6) In the example described here, the integrated circuit IC comprises a plurality of parallel polysilicon lines, the two lines on the right in FIG. 1 resting on an insulating zone DS and serving as patterns aiding with the photolithography of the gate regions.

(7) Moreover, the contact CTC extends parallel to the polysilicon lines LP. It makes contact with the active zone ZA and projects from this active zone in the direction parallel to the polysilicon lines LP in order to overlap an insulating cavity CV0.

(8) In the examples that will now be described, the integrated circuit is produced on an SOI substrate although the invention is not limited to this type of substrate.

(9) Moreover, of the following figures, those of even number are schematic cross sections along the line AA in FIG. 1 whereas those of uneven number are schematic cross-sectional views along the line BB in FIG. 1.

(10) A first variant of a process for producing the contact CTC will now be described in more detail with reference more particularly to FIGS. 2 to 19.

(11) In FIGS. 2 and 3, the structure STR obtained after the conventional first phases of the integration process of the contact comprises, as indicated above, an SOI substrate comprising a semiconductor film 3 on a buried insulating layer 2 (BOX) itself borne by a subjacent semiconductor carrier substrate 1.

(12) In the example described here, the zone 4 is a trench isolation zone, for example a shallow trench isolation (STI) zone.

(13) The active zone ZA results from epitaxy of silicon 50 between the two polysilicon lines LP.

(14) The preparation for this epitaxy requires cleaning treatments, generally wet treatments based on hydrofluoric acid (HF), which consume a certain amount of silicon oxide on all the exposed surfaces of the wafer, and especially in the insulating zones 4, between two polysilicon lines LP, thus causing cavities CV0, CV1, CV2 to form.

(15) Moreover, the epitaxial region 50 and the polysilicon lines LP have undergone a siliciding treatment, the active zone thus comprising a zone 51 comprising a metal silicide, for example nickel silicide (NiSi).

(16) It may be seen in FIG. 3 that the bottom of the cavity CV0, which borders the active zone ZA, neighbors a portion of the carrier substrate 1.

(17) As illustrated in FIGS. 4 and 5, a first insulating layer 6, typically an etch stop layer made of silicon nitride (this layer commonly being designated the contact etch stop layer (CESL) by those skilled in the art) is deposited on the structure STR in FIGS. 2 and 3.

(18) Next, as illustrated in FIGS. 6 and 7, a first insulating material 7, for example silicon dioxide, is deposited on this layer 6.

(19) Next, a chemical-mechanical polish is carried out (FIGS. 8 and 9).

(20) In the following step, illustrated in FIGS. 10 and 11, an additional insulating layer 8 is deposited on the first insulating layer 6 and on the first insulating material 7, the latter having especially filled the cavity CV0.

(21) This additional insulating layer 8 may also be a layer of silicon nitride. As will be seen in more detail below, it will also serve as an etch stop layer.

(22) Next, as illustrated in FIGS. 12 and 13, a second insulating material 9, for example a TEOS oxide, is deposited.

(23) Next, in a conventional way known per se, an aperture 100 defining the geometry of the future contact CTC is produced in a mask 10.

(24) Next, as illustrated in FIGS. 14 and 15, a first etch GV1 of the second insulating material 9 is carried out through the orifice 100 so as to define a first orifice 101 opening onto the additional insulating layer 8.

(25) This first etch GV1 is stopped on the layer 8. By way of example, it is possible to use a reactive ion etch (RIE) with a fluorocarbon chemistry.

(26) At this stage, on account of the presence of the additional insulating layer 8 above the cavity CV0, the etch GV1 has not etched the first insulating material 7 present in the cavity CV0, which would have been the case if this layer 8 were absent.

(27) Next, as illustrated in FIGS. 16 and 17, a second etch GV2 is carried out allowing a portion of the layer 8 and of the layer 6 to be etched so as to expose the silicided zone 51 of the active zone ZA. Moreover, this etch GV2 also etches the layer 8 located above the cavity CV0 and consumes a portion of the first insulating material 7. This being so, after this etch GV2, there remains a height h, for example 40 nm, of a first insulating material 7 on top of the first insulating layer 6 lining the bottom of the cavity CV0.

(28) This etch GV2 is also a conventional etch known per se, for example a reactive ion etch with a chemistry containing a gas such as CH.sub.xF.sub.y.

(29) The additional insulating layer 8 is advantageously thick enough to be able to act as an etch stop layer for the etch GV1 and thin enough not to disrupt the etch GV2 and to allow the silicided zone 51 to be effectively exposed. A thickness comprised between 5 and 20 nm is an acceptable thickness. In practice, the additional insulating layer 8 has a thickness of about 10 nm.

(30) Next, as illustrated in FIGS. 18 and 19, the orifice 102 obtained after the etch GV2 is filled with an electrically conductive filling material, for example copper, tungsten or aluminum. This filling is carried out in a conventional way by deposition followed by a chemical-mechanical polishing.

(31) As may be seen in FIGS. 18 and 19, the integrated circuit here comprises an active zone ZA lying above the semiconductor substrate 3. A cavity CV0 borders the active zone ZA and extends, in an insulating zone 2, and possibly 4, as far as into the vicinity of a semiconductor region here formed by a portion of the carrier substrate 1. The electrically conductive contact CTC is located within an insulating multilayer and emerges onto the active zone ZA and into the cavity.

(32) This insulating multilayer here comprises the first insulating layer 6 covering the active zone outside the contact CTC, lining at least partially the walls of the cavity CV0 and possessing a segment 60 located between the contact CTC and the semiconductor region 1.

(33) The insulating multilayer also comprises an insulating region on top of the first insulating layer 6. This insulating region comprises the first insulating material 7 and the second insulating material 9, around the contact CTC, and the additional insulating layer 8. This additional insulating layer 8 possesses a first portion 80 covering the first insulating layer 6 outside the contact CTC and a second portion 81 here located between the insulating materials 7 and 9 and at a distance from the portion of the first insulating layer 6 that lines the walls of the cavity CV0.

(34) To illustrate one variant of the invention, reference is now more particularly made to FIGS. 20 to 35.

(35) The process according to this variant also starts with the steps illustrated in FIGS. 2 to 5.

(36) Then, as illustrated in FIGS. 20 and 21, an additional insulating layer 12 that covers the first insulating layer 6 is deposited on the structure illustrated in FIGS. 4 and 5.

(37) This additional insulating layer 12 forms a barrier layer and it is selectively etchable relative to the first insulating layer 6. In other words, the additional insulating layer 12 is configured to not or almost not be etched during etching of the first insulating layer 6.

(38) By way of indication, the first insulating layer 6 may comprise silicon nitride whereas the additional insulating layer 12 may comprise a dielectric material of high dielectric constant k, typically higher than 15. Such a dielectric may for example be AlO.sub.2, HfO.sub.2, MN, TiN or TiO.sub.2 these examples not being limiting.

(39) Next, as illustrated in FIGS. 22 and 23, the first insulating material 7 is deposited on this additional insulating layer 12. This deposition is followed by a chemical-mechanical polish allowing the structure illustrated in FIGS. 24 and 25 to be obtained. More precisely, the additional insulating layer 12 remains in the cavities but has been removed above other portions of the first insulating layer 6, in particular above the active zone ZA.

(40) In this respect, the additional insulating layer 12 is advantageously thick enough to act as an etch stop layer and thin enough not to disrupt the chemical-mechanical polish.

(41) A thickness comprised between 2 and 15 nm is an acceptable thickness. Typically, the thickness of the additional insulating layer 12 is about 6 nm.

(42) Next, as illustrated in FIGS. 26 and 27, the second insulating material 9, typically TEOS oxide, is deposited. Next, in an analogous way to the way described above, the aperture 100 allowing the geometry of the contact CTC to be defined is formed in the mask 10 (FIGS. 28 and 29).

(43) Next, an etch GV4 that is for example identical to the etch GV1 is carried out. This etch GV4 is stopped, on the one hand, on the first insulating layer 6 above the active zone ZA, and on the other hand, on the additional insulating layer 12 in the bottom of the cavity CV0.

(44) An orifice 103 is thus formed (FIGS. 30 and 31).

(45) Next, an etch GV5 is carried out that allows the additional insulating layer 6 to be selectively etched without etching or almost without etching the additional insulating layer 12.

(46) Such an etch GV5 is for example a reactive ion etch with a chemistry containing a gas such as CH.sub.xF.sub.y.

(47) An orifice 104 opening onto the silicided zone 51 of the active zone ZA and opening onto the additional insulating layer 12 in the bottom of the cavity CV0 is then obtained (FIGS. 32 and 33).

(48) Next, in an analogous way to the way described above, the orifice 104 is filled so as to form the electrically conductive contact CTC (FIGS. 34 and 35).

(49) The presence of the additional insulating layer 12 in the bottom of the cavity CV0 thus makes it possible to avoid piercing the first insulating layer 6 and therefore a short circuit between the end of the contact CTC and the neighboring portion of the carrier substrate 1.

(50) As may be seen in FIGS. 34 and 35, the insulating multilayer this time comprises the first insulating layer 6 covering the active zone ZA outside the contact CTC and lining the walls of the cavity CV0 and the additional insulating layer 12 covering the portion of the first insulating layer 6 that lines the walls of the cavity. The contact CTC has reached this additional insulating layer 12 in the cavity CV0.

(51) Furthermore, in an analogous way to the way described above, the insulating multilayer moreover comprises an insulating region located on top of the first insulating layer 6 and of the additional insulating layer 12 and comprising the first insulating material 7 and the second insulating material 9 around the contact CTC.

(52) The invention is not limited to the methods of implementation and embodiments just described but encompasses any variant.

(53) The substrate may also be a bulk substrate bearing raised active regions.

(54) The invention may apply to any type of transistor, especially planar MOS transistors, but also FinFET MOS transistors.