METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS AND SEMICONDUCTOR COMPONENT

Abstract

A method for producing a plurality of semiconductor components (1) is provided, comprising the following steps: a) providing a semiconductor layer sequence (2) having a first semiconductor layer (21), a second semiconductor layer (22) and an active region (25), said active region being arranged between the first semiconductor layer and the second semiconductor layer for generating and/or receiving radiation; b) forming a first connection layer (31) on the side of the second connection layer facing away from the first semiconductor layer; c) forming a plurality of cut-outs (29) through the semiconductor layer sequence; d) forming a conducting layer (4) in the cut-outs for establishing an electrically conductive connection between the first semiconductor layer and the first connection layer; and e) separating into the plurality of semiconductor components, wherein a semiconductor body (20) having at least one of the plurality of cut-outs arises from the semiconductor layer sequence for each semiconductor component and the at least one cut-out is completely surrounded by the semiconductor body in a top view of the semiconductor body. Furthermore, a semiconductor component is provided.

Claims

1. A method for producing a plurality of semiconductor components, comprising the steps of: a) providing a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and an active region, arranged between the first semiconductor layer and the second semiconductor layer provided for generating and/or receiving radiation; b) forming a first connection layer on the side of the second connection layer facing away from the first semiconductor layer; c) forming a plurality of cut-outs through the semiconductor layer sequence; d) forming a conducting layer in the cut-outs for establishing an electrically conductive connection between the first semiconductor layer and the first connection layer; and e) singulating into the plurality of semiconductor components, wherein a semiconductor body having at least one of the plurality of cut-outs arises from the semiconductor layer sequence for each semiconductor component and the at least one cut-out is completely surrounded by the semiconductor body in a top view of the semiconductor body.

2. Method according to claim 1, in which a separating layer is applied between the active region and the conducting layer for electrical insulation, said separating layer covering the lateral surfaces of the cut-outs at least on the level of the second semiconductor layer and of the active region.

3. Method according to claim 1, in which material for the separating layer is applied over the entire semiconductor layer sequence with the cut-outs for forming said separating layer, and the material is removed in such a way, by means of a directionally selective etching method, that only surfaces running obliquely or perpendicularly to a main extension plane of the semiconductor layers of the semiconductor layer sequence remain covered by the separating layer.

4. Method according to claim 3, in which further material of the separating layer is removed in a subsequent further directionally selective etching method and the first semiconductor layer in the cut-outs is sectionally exposed.

5. Method according to claim 4, in which the first connection layer is exposed by the further directionally selective etching method.

6. Method according to claim 1, in which a first insulation layer with openings is formed before forming the cut-outs between the semiconductor layer sequence and the first connection layer, wherein the cut-outs are formed in such a way that they overlap with the openings in a top view of the semiconductor layer sequence.

7. Method according to claim 1, in which a growth substrate for the semiconductor layer sequence is removed before step c).

8. Method according to claim 1, in which a masking layer with a plurality of openings is applied to the semiconductor layer sequence before applying the conducting layer and each cut-out is completely arranged within one of the plurality of openings in a top view and the first semiconductor layer laterally to the cut-outs is partially free from the masking layer.

9. Method according to claim 8, in which the openings taper with increasing distance from the semiconductor layer sequence and material for the conducting layer, with a main deposition direction running obliquely to a vertical direction running perpendicular to a main extension plane of the semiconductor layer sequence, is deposited such that the material of the conducting layer deposited in the openings overlaps with material of the conducting layer deposited on the masking layer in a top view.

10. Method according to claim 1, in which a covering layer is applied to the conducting layer and said covering layer serves as mask for removing material from the first semiconductor layer.

11. Method according to claim 1, wherein the semiconductor layer sequence is secured to a carrier between step b) and step c).

12. Semiconductor component having a semiconductor body, comprising a first semiconductor layer, a second semiconductor layer and an active region arranged between the first semiconductor layer and the second semiconductor layer for generating and/or receiving radiation, wherein a first connection layer is arranged on the side of the second semiconductor layer facing away from the first semiconductor layer; the semiconductor body has at least one cut-out extending through the semiconductor body and said cut-out is completely surrounded by the semiconductor body in a top view of said semiconductor body; and a conducting layer is arranged in the at least one cut-out and forms an electrically conductive connection between the first semiconductor layer and the first connection layer.

13. Semiconductor component according to claim 12, wherein the conducting layer is immediately adjacent to the first semiconductor layer in the at least one cut-out.

14. Semiconductor component according to claim 12, wherein the conducing layer is partially arranged on one radiation passage surfaces situated opposite to the active region of the first semiconductor layer.

15. Semiconductor component according to claim 12, wherein the first semiconductor layer has a contact layer, which is formed solely below the conducting layer in a top view of the semiconductor component.

16. Semiconductor component according to claim 12, wherein a second connection layer is arranged between the first connection layer and the second semiconductor layer for electrically contacting the second semiconductor layer.

17. Semiconductor component according to claim 12, wherein the semiconductor component further comprises a separating layer, the separating layer covers a lateral surface of the cut-out at least on the level of the second semiconductor layer and of the active region, and wherein the lateral surface comprises a partial area in which the first semiconductor layer is free from the separating layer.

18. A method for producing a plurality of semiconductor components, comprising the steps of: a) providing a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and an active region, arranged between the first semiconductor layer and the second semiconductor layer provided for generating and/or receiving radiation; b) forming a first connection layer on the side of the second connection layer facing away from the first semiconductor layer; c) forming a plurality of cut-outs through the semiconductor layer sequence; d) forming a conducting layer in the cut-outs for establishing an electrically conductive connection between the first semiconductor layer and the first connection layer; and e) singulating into the plurality of semiconductor components, wherein a semiconductor body having at least one of the plurality of cut-outs arises from the semiconductor layer sequence for each semiconductor component and the at least one cut-out is completely surrounded by the semiconductor body in a top view of the semiconductor body; wherein a separating layer is applied between the active region and the conducting layer for electrical insulation, said separating layer covering the lateral surfaces of the cut-outs at least on the level of the second semiconductor layer and of the active region; and a material of the separating layer covering the lateral surfaces is removed such that the lateral surfaces comprise a partial area in which the first semiconductor layer is free from the separating layer.

Description

[0048] Further features, embodiments and expediencies result from the following description of the exemplary embodiments in conjunction with the figures.

[0049] The figures show in:

[0050] FIGS. 1A to 1N an exemplary embodiment of a method for producing a semiconductor component on the basis of interim steps schematically shown in sectional view;

[0051] FIGS. 2A and 2B each a further exemplary embodiment of a method for producing a semiconductor component on the basis of interim steps schematically shown in sectional view; and

[0052] FIGS. 3 to 5 each show an exemplary embodiment of a semiconductor component.

[0053] Identical, similar and similarly acting elements are indicated with the same reference numerals in the figures.

[0054] The figures and size ratios of the elements shown in the figures amongst each other should not be considered as true-to-scale. Instead, individual elements and in particular layer thicknesses can be shown exaggeratedly large for the sake of better representation or the sake of better comprehension.

[0055] An exemplary embodiment for a method for producing in particular optoelectronic semiconductor components is provided on the basis of FIGS. 1A to 1N. To simplify the representation, only an excerpt is shown from which precisely one semiconductor component arises in a singulation step. The produced semiconductor components can, for example, be radiation emitters, such as luminescent diodes, or radiation receivers, such as photodiodes or solar cells.

[0056] A semiconductor layer sequence 2 comprising an active region 25 for generating and/or receiving electromagnetic radiation is provided. In the exemplary embodiment shown, the active region 25 is configured for generating radiation and has a quantum structure. Said quantum structure comprises a plurality of quantum layers 251, wherein a barrier layer 252 is arranged between adjacent quantum layers. Only two quantum layers are shown in FIG. 1A for the sake of simplified representation, although the active region can have more than two quantum layers. For the sake of simplified representation, the structure of the active region 25 is not explicitly illustrated in the subsequent illustrations. The active region 25 is arranged between a first semiconductor layer 21 and a second semiconductor layer 22. In the exemplary embodiment shown, the first semiconductor layer 21 has a contact layer 210 on the side of the contact layer 210 facing away from the active region 25. The contact layer 210 serves for simplified electrical contact of the first semiconductor layer in a subsequent method step. The contact layer 201 expediently has a higher doping than the material of the first semiconductor layer adjacent to the contact layer, for example a doping of at least 110.sup.18 cm.sup.3. However, such a contact layer is not essential.

[0057] The first semiconductor layer 21 and the second semiconductor layer 22 are different from each other with regard to the type of conductivity. For example, the first semiconductor layer 21 is n-type and the second semiconductor layer is p-type or vice versa. The deposition of the semiconductor layer sequence 2 ensues on a growth substrate 200, for example by means of epitaxial deposition, such as MOVPE.

[0058] The semiconductor layer sequence, in particular the active region 25, preferably contains a III-V compound semiconductor material.

[0059] III-V compound semiconductor materials are particularly suitable for radiation generation in the ultraviolet (Al.sub.xIn.sub.yGa.sub.1-x-yN) via the visible (Al.sub.xIn.sub.yGa.sub.1-x-yN, in particular for blue to green radiation, or Al.sub.xIn.sub.yGa.sub.1-x-yP, in particular for yellow to red radiation) up to the infrared (Al.sub.xIn.sub.yGa.sub.1-x-yAs) spectral range. In this context, 0x1, 0y1 and y1, in particular with x1, y1, x0 and/or y0 apply. Further, high internal quantum efficiencies are achievable with III-V compound semiconductor materials, in particular from the stated material systems.

[0060] A structuring 26 with a plurality of depressions 260 is formed on the side facing away from the growth substrate 200 (FIG. 1B). The structuring is in particular provided for reducing wave guiding effects and for improving the outcoupling efficiency in the case of a radiation-emitting component. For example, the structuring 26 can be configured in the form of microprisms. However, other configurations are also conceivable, for example an irregular structuring, such as a roughening.

[0061] A first insulation layer 71 is formed on the semiconductor layer sequence 2. Said first insulation layer 71 comprises cut-outs 711. The electrical contacting of the second semiconductor layer now ensues via the cut-outs of the first insulation layer. A second connection layer 32 is formed on the insulation layer. Said second connection layer 32 exemplarily comprises a first partial layer 321 and mirror layer 322. The first partial layer is formed in the cut-outs 711 and servers for the electrical contacting of the second semiconductor layer 22. However, the first insulation layer is not essential. It is also conceivable that the second connection layer is adjacent to of the second semiconductor layer in a large area. For the sake of simplified representation, the first partial layer 321 is not explicitly shown in the further interim steps.

[0062] The designation of individual layers in the type of a numeration such as first insulation layer and second insulation layer in the present application serves only the simplified reference to individual layers and does not implicit an order in the production of layers. In addition, the term second insulation layer does not necessarily require the presence of a first insulation layer.

[0063] The second connection layer 32 further comprises cut-outs 325. The second semiconductor layer 22 is free from metallic material in such cut-outs.

[0064] As shown in FIG. 1C, a first connection layer 31 is subsequently applied to the second connection 32. Said second connection layer 32 partially runs between the first connection layer 31 and the second semiconductor layer 22. For electrical insulation between the first connection layer and the second connection layer a second insulation layer is formed between the two connection layers. The second insulation layer covers the entire semiconductor layer sequence. Furthermore, the second insulation layer in the cut-outs 325 of the second connection layer is adjacent to the first insulation layer 71.

[0065] No metallic material is located in the area of the cut-outs 325 of the second connection layer 32 between the first connection layer 31 and the second semiconductor layer 22.

[0066] The first connection layer 31 covers the entire semiconductor layer sequence 2. No lithographic structuring method is thus required for the formation of the first connection layer 31.

[0067] Subsequently, the semiconductor layer sequence is secured to a carrier 5 by means of a connection layer 55, for instance a soldering layer or an electrically conductive adhesive layer. The second semiconductor layer 22 is arranged on the side of the semiconductor layer sequence facing the carrier 5 (FIG. 1D).

[0068] The carrier serves the mechanical stabilization of the semiconductor layer sequence 2, and therefore the growth substrate 200 is no longer required to this end and can be removed (FIG. 1E). The removal of the growth substrate can, for example, ensue mechanically, for instance by means of grinding, lapping or polishing and/or chemically, for example by means of wet-chemical or dry-chemical etching.

[0069] In particular, the growth substrate can be mechanically thinned in a first partial step. In a second partial step, the remaining residue can be removed by means of a chemical removal method. In deviation thereto, it is also conceivable that the growth substrate 200 is already removed during the securing process on the carrier. In such case, the semiconductor layer sequence can for example be stabilized by a temporary auxiliary carrier during the securing process on the carrier.

[0070] As shown in FIG. 1F, cut-outs 29 are formed from the side facing away from the carrier 5, which extend completely through the semiconductor layer sequence 2. At the same time, isolation trenches 28 are formed for subdividing the semiconductor layer sequence 2 into semiconductor bodies 20 laterally spaced from each other. The formation of the cut-outs 29 and of the isolation trenches 28 in one production step reduces the production outlay. However, the cut-outs and the isolation trenches can also be formed successively in completely separate steps. The cut-outs and the isolation trenches are spaced apart from each other in lateral direction, and therefore the cut-outs of the individual semiconductor bodies are each surrounded by material of the semiconductor body along the entire circumference. The cut-outs 29 and/or isolation trenches 28 can have perpendicular flanks, i.e. flanks running parallel to the vertical direction. Alternatively, the flanks can be formed obliquely to the vertical direction, wherein the cross-section of the cut-outs 29 and/or isolation trenches 28 tapers in the direction of the carrier 5.

[0071] In a top view, the cut-outs 29 in the semiconductor layer sequence overlap with the cut-outs 325 of the second connection layer 325. In particular, the cut-outs 29 run completely within the cut-outs 325 of the second connection layer 325.

[0072] Subsequently, material for a separating layer 73 is deposited by means of a conformally acting method, for example by means of a CVD (chemical vapour deposition) method or ALD (atomic layer deposition) method. A conformally deposited layer follows to the form of the material located below. The material of the separating layer covers the entire semiconductor layer sequence, in particular including the lateral surfaces of the cut-outs 29 and the isolation trenches 28.

[0073] As shown in FIG. 1G, the separating layer 73 is completely subjected to a directionally selective etching method, such that surfaces running parallel to the main extension plane of the semiconductor layers of the semiconductor layer sequence 2 are freed from the material of the separating layer. The separating layer 73 is thus located only on the lateral surfaces running obliquely or perpendicularly to the main extension plane, in particular on the lateral surfaces 290 of the cut-outs 29 and on the lateral surfaces of the isolating trenches 28.

[0074] Thus, the directionally selective etching method allows a separating layer to be realized that effects an electrical insulation of the lateral surfaces of the cut-outs 29 in the area of the cut-outs, without a lithography method being required to this end. Instead, the formation of the separating layer 73 is self-aligned. The waive of two lithographic steps aligned with each other for the formation of the coated cut-outs allows the lateral extension of the cut-outs 29 to be reduced, thus decreasing the proportion of the active region 25, which is lost by the formation of the cut-outs 29. For example, a dry-chemical etching method is suitable as a directionally selective etching method, such as reactive ion etching.

[0075] As shown in FIG. 1H, a masking layer 8, for example a photo resist layer is subsequently applied to the semiconductor layer sequence 2. The masking layer is designed in such a way that openings 81 are formed in the masking layer, wherein the cut-outs 29 are completely arranged within the openings 81 in a top view of the semiconductor layer sequence 2. With increasing distance from the semiconductor layer sequence 2, the cross-section of the openings 81 decreases, such that an undercut area is created.

[0076] Subsequently, as illustrated in FIG. 1I, material of the separating layer 73 is removed by means of another directionally selective method. The further directionally-selective method as well has a higher etching rate in the vertical direction than in the lateral direction. The material covering the lateral surfaces 29 is thus removed in the vertical direction. Therefore, the lateral surfaces 290 of cut-outs 29 in each case comprise a partial area 291, in which the first semiconductor layer 21 is exposed. In particular, the partial area is adjacent to the contact layer 210.

[0077] Further, the material located between the first connection layer 31 and the cut-outs 29 is removed on the bottom of the cut-outs 29 such that the first connection layer 31 is exposed by means of the further directionally selective etching method. In particular, material of the second insulation layer 72 is removed in the area of cut-outs 29. Exposure of the first connection layer 31 ensues in the cut-outs 325 of the second connection layer. Thus, no metallic material has to be removed when exposing said layer.

[0078] Subsequently, as illustrated in FIG. 1J, a conducting layer 4 is applied to the semiconductor layer sequence 2 covering its entire surface. Material of the conducting layer 4 covers the lateral surfaces 290 of cut-outs 290 and the mask layer 8. Preferably, deposition of the conductive layer ensues in a main deposition direction (indicated by an arrow 95), which runs obliquely to the vertical direction such that partial areas of the first semiconductor layer are covered by the conductive layer, which areas are covered by the mask layer 8 in a top view. Thus, the material deposited on the first semiconductor layer 4 and the material deposited on the mask layer overlap in areas in a top view. Preferably, the semiconductor layer sequence is rotated during deposition of the conducting layer such that the conducting layer 4 completely circumvents the cut-outs 29 on the first semiconductor layer.

[0079] Subsequently, a covering layer 74 is deposited over its entire surface (FIG. 1K), preferably as well with a main deposition direction running obliquely to the vertical direction.

[0080] After removal of the mask layer 8 (FIG. 1L), the areas of the semiconductor layer previously covered by the masking layer are free from the covering layer 74. In particular, the covering layer 74 completely covers the conducting layer 4.

[0081] The masking layer 74 can now serve as a mask for a material removal of the semiconductor layer sequence 2 (FIG. 1M). During material removal, the contact layer 210 can be removed in sections such that the latter is only present below the covering layer 74 and the conducting layer 4. A good ohmic contact to the conducting layer 4 can be achieved by means of the contact layer 210. Lateral from the conducting layer 4, the material of the contact layer 210 is removed such that the risk of a radiation absorption by the contact layer 210 is reduced. This achieves a good electrical conductivity and at the same time reduced absorption losses in a simple and reliable manner. In particular, no additional photolithographic step is required to that end.

[0082] In the material removal of material of the semiconductor layer sequence, furthermore an outcoupling structuring 27 can be formed, e.g. in the form of a roughening.

[0083] Subsequently, as illustrated in FIG. 1N, optionally a passivation layer 75 is applied to the semiconductor layer sequence. It is as well conceivable to additionally form a radiation conversion layer (not explicitly shown) on the passivation layer or to provide a radiation conversion material in the passivation layer.

[0084] The carrier 5 is thinned from the side facing away from the semiconductor layer sequence 2. Thereby the height of the component can be reduced. Prior to the thinning, the carrier may comprise a higher mechanical robustness due to the higher thickness. As an alternative, the semiconductor layer sequence 2 can be applied onto a carrier, which carrier already has the final thickness desired in the completed semiconductor component.

[0085] A first contact 61 is formed on the side of the carrier 5 facing away from the semiconductor layer sequence 5. In this present exemplary embodiment, the first contact 5 is connected to the first semiconductor layer 21 via the carrier 5, the first connection layer 31 and the conducting layer 4. A second contact 62 for electrically contacting the second semiconductor layer 22 via the second connection layer 32 is formed laterally from the semiconductor body 20 on the side of the carrier 5 facing the semiconductor layer sequence 2.

[0086] By application of an external electric voltage between the first contact 61 and the second contact 62, charge carriers can be injected into the active region 25 from opposing sides and will recombine there while emitting radiation.

[0087] For the formation of the individual semiconductor components, the compound thus produced will be singulated along the singulation lines so that the produced semiconductor components in each case comprise a part of the carrier 5 and a semiconductor body 20 with at least one cut-out 29.

[0088] The method described allows producing semiconductor components in a simple and reliable manner, wherein the semiconductor body 2, particularly the radiation passage surface 11, is free of structures for current distribution and an external contact, for example for a wire bond connection. The electric contacting of the first semiconductor layer 21 arranged on the side of the active region 25 facing away from the carrier 5 may be effected by the cut-outs 29, wherein the cut-outs 29 can be produced in a self-adjusting process in a reliable and simple manner such that the conducting layer 4 is electrically insulated in the cut-outs from the second semiconductor layer 22 and the active region 25.

[0089] FIG. 1N shows an exemplary embodiment of a semiconductor component 1 produced this way. The semiconductor component 1, merely by way of example, comprises a rear-sided first contact 61 and a front-sided contact 62, arranged particularly laterally from the semiconductor body 2.

[0090] The first insulation layer 71, the second insulation layer 72, the separation layer 73, the cover layer 74 and the passivation layer 75 preferably each contain an electrically insulting material, for example an oxide such as silicon oxide, or a nitride such as silicon nitride.

[0091] The first connection layer 31, the second connection layer 32, the first contact 61 and the second contact 62 preferably each comprise a metal or consist of a metal or a metal alloy. The layers may in each case have a single-layered or multi-layered design.

[0092] A further exemplary embodiment for a method is shown with reference to the intermediate steps illustrated in FIG. 2A. This exemplary embodiment essentially corresponds to the exemplary embodiment described in conjunction with FIGS. 1A to 1N.

[0093] Here, FIG. 2A essentially corresponds to FIG. 1B. In contrast, the cut-out 325 of the second connection layer 32 is located in one of the depressions 260a of the structure 26. Preferably, the lateral extent of the depressions 260a has a size that the cut-out 325 of the second connection layer 32 is completely located within the depression. The remaining depressions 260 may have a smaller lateral extent. Thus, removing the entire thickness of the semiconductor layer sequence is no longer required when subsequently forming the cut-outs through the semiconductor layer sequence (see FIG. 1F).

[0094] The further production steps can be performed as described in connection with the first exemplary embodiment.

[0095] A further exemplary embodiment for a method is shown with reference to the intermediate step illustrated in FIG. 2B. This exemplary embodiment essentially corresponds to the exemplary embodiment illustrated in FIG. 2A. In contrast, in the step shown in FIG. 2B, the first insulation layer 71 is formed such that semiconductor layer sequence has openings 712 in the region of the cut-outs 712 to be produced. The electric contacting of the first connection layer 31 via the conductor layer 4 can be effected by these openings see FIG. 1J). In contrast to the intermediate step illustrated in FIG. 1I, partial removal of the first insulation layer in the cut-outs 29 after removal of the semiconductor layer sequence is not required. This way, exposure of the first connection layer 31 is facilitated.

[0096] The first partial layer 321 of the second connection layer provided for the electrical contacting of the second semiconductor layer 22 can be applied in the openings 712 just like in the cut-outs 711. Subsequently, said layer can be removed in the openings, particularly in the step in which the second connection layer 32 is being structured.

[0097] This allows for the forming of the openings 712 to be effected without additional lithography mask in a simple manner. The openings 712 for electrical contacting of the first semiconductor layer 21 and the cut-outs 711 for electrical contacting of the second semiconductor layer 22 can thus be formed in a joint method.

[0098] The further production steps can be performed as described in conjunction with the first exemplary embodiment. The exemplary embodiment illustrated in FIG. 2B is also suitable for the first exemplary embodiment.

[0099] In contrast to the exemplary embodiment illustrated in FIG. 1N, the exemplary embodiment of a semiconductor component 1 illustrated in FIG. 3 comprises two front-sided contacts. The first contact 61 is thus not arranged on the rear side of the carrier 5 but also laterally from the semiconductor body 20. In this case, the carrier 5 may just as well be configured to be electrically insulating.

[0100] The exemplary embodiment illustrated in FIG. 4 comprises, just like the exemplary embodiment shown in FIG. 1N, a front-sided contact and a rear-sided contact. In contrast, the first contact 61 which is connected to the first semiconductor layer 21 in an electrically conducting manner is the front-sided contact. The second contact 62 connected to the second semiconductor layer 22 forms a rear-sided contact. Thus, in this case, the semiconductor layer arranged on the side of the active region 25 facing the carrier, namely the second semiconductor layer 22, can be contacted to a rear-sided contact externally through the carrier.

[0101] In the exemplary embodiment illustrated in FIG. 4, in contrast to the exemplary embodiment described in conjunction with FIG. 1N, a semiconductor component 1 is shown, in which the first contact 61 and the second contact 62 are formed on the rear side of the carrier 5. In this case, the carrier 5 has through-connections 51. Both contacts of the semiconductor component 1 are accessible from the rear side. The carrier 5 includes a carrier body 50 with cut-outs, the through-connections extending through said cut-outs in the vertical direction. The carrier body is sectionally covered by a carrier insulation layer 57, in particular in the region of the through-connections 51, on a main face facing the semiconductor body 20 and a main face facing away from the semiconductor body. The first connection layer 31 and the second connection layer 32 are insulated from one another electrically via an intermediate space 56. For example, the intermediate space can be filled with a gas such as air or an inert gas or be evacuated. As an alternative, the intermediate space may be filled with an electrically insulating solid material.

[0102] This patent application claims the priority of the German patent application 10 2014 102 029.4, the disclosure of which is incorporated herein by reference.

[0103] The invention is not limited by the description in conjunction with the exemplary embodiments. The invention rather comprises all new features as well as any combination of features, which particularly includes any combination of features in the patent claims, even if said feature or said combination is not explicitly indicated in the patent claims or exemplary embodiments.