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PHOTON COUNTING CONE-BEAM CT APPARATUS WITH MONOLITHIC CMOS INTEGRATED PIXEL DETECTORS

20170055923 · 2017-03-02

    Inventors

    Cpc classification

    International classification

    Abstract

    CBCT including monolithic photon counting FPD for medical applications requiring real-time 3D imaging, like mammography, interventional guided procedures or external beam radiotherapy, includes CMOS processed readout electronics monolithically integrated with a single crystalline X-ray absorber by covalent wafer bonding near room temperature and adapted for single photon counting providing high energy, temporal and spatial resolution.

    Claims

    1. A cone beam computer tomography (CBCT) system, comprising a. at least one X-ray source, and b. a flat panel detector (FPD) disposed for the direct detection of X-rays, wherein at least one absorber made from single crystal material communicates with at least one CMOS processed readout unit with which it forms a monolithic unit, and wherein the absorber is disposed to transform X-ray photons into electrical signals which are collected by the readout unit, and c. one or more devices providing data collection, computation and/or storage functionality, arranged and connected to receive electrical signals from the FPD and to generate computed tomography images on at least one computer screen.

    2. The system of claim 1, wherein the at least one X-ray source and the FPD are mounted on a C-arm permitting interventional radiology.

    3. The system of claim 1, wherein the at least one X-ray source and the FPD are mounted on a C-arm permitting 3D imaging for mammography.

    4. The system of claim 1, wherein the FPD comprises a. at least one CMOS processed readout unit, and b. at least one X-ray absorber electrically communicating with the at least one readout unit by electrically transparent, oxide-free covalent wafer bonding, and wherein the FPD is configured to provide photon counting capability to permit energy resolved single photon counting.

    5. The system of claim 1, wherein the at least one CMOS processed readout unit comprises at least one thinned silicon wafer with a thickness of about 10-100 m.

    6. The system of claim 1, wherein the at least one CMOS processed readout unit comprises at least one thinned silicon wafer with a thickness of about 10-20 m.

    7. The system of claim 2, wherein the at least one absorber is bonded in an oxide-free covalent wafer bond onto a back surface of the at least one CMOS processed readout unit.

    8. The system of claim 1, wherein the FPD comprises buttable tiles and wherein the FPD comprises an area of at least 2020 cm.sup.2.

    9. The system of claim 8, wherein the spacing between buttable tiles is in the range of 50-100 m.

    10. The system of claim 1, wherein the FPD is adapted to provide a spatial resolution in the range of 100-200 m.

    11. The system of claim 1, wherein the FPD is adapted to provide a spatial resolution in the range of 50-100 m.

    12. The system of claim 1, wherein the at least one X-ray source, FPD and the one or more devices providing data collection, computation and/or storage functionality are adapted for use in one of a group of applications consisting of projection radiography, mammography and interventional radiology.

    13. The system of claim 1, wherein the at least one X-ray source, FPD and the one or more devices providing data collection, computation and/or storage functionality are adapted for use in mammography.

    14. The system of claim 1, wherein the absorber comprises at least one element with an atomic number larger than that of Si.

    15. The system of claim 1, wherein the absorber is made from at least one of a group of absorber materials consisting of Si, Si.sub.1-xGe.sub.x alloys with Ge fractions 0x1, GaAs, CdTe, and Cd.sub.1-xZn.sub.xTe with x of about 10%.

    16. The system of claim 1, wherein the absorber is made from a Si.sub.1-xGe.sub.x alloy with a Ge fraction of 0x1.

    17. The system of claim 16, wherein the absorber is a 100-200 m thick epitaxial layer on a Si substrate.

    18. The system of claim 1, wherein the absorber is made from a Si.sub.1-xGe.sub.x alloy with a Ge fraction of 0.6x0.8.

    19. The system of claim 18, wherein the absorber is a 100-200 m thick epitaxial layer on a Si substrate.

    20. The system of claim 1, wherein the at least one CMOS processed readout unit comprises implants configured to receive the analog electrical signals generated by absorbed X-ray photons in the at least one absorber, and wherein further circuitry amplifies, shapes and transforms these electrical signals into digital signals to be further processed in the one or more devices providing data collection, computation and/or storage functionality to be displayed as a computed tomography image on at least one computer screen.

    21. A method for performing tomography, the method comprising steps of a. providing at least one X-ray source; b. using a FPD from at least one single crystal absorber covalently bonded to at least one CMOS processed readout unit, the at least one readout unit having single-photon counting capability; c. with the at least one X-ray source and the FPD mounted on a C-arm and a patient positioned in an appropriate operation position, activating the at least one readout unit to communicate with at least one device providing data collection, computation and storage functionality; d. disposing the at least one device to receive electrical signals from the FPD, and e. scanning the patient; and f. generating computed tomography images on at least one computer screen.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0032] FIG. 1 is a graph showing the dependence of the band gap of Si1-xGex alloys as a function of the Ge content x.

    [0033] FIG. 2 is a schematic diagram of a C-arm cone-beam computed tomography unit.

    [0034] FIG. 3A is a cross-sectional view of a monolithic pixel detector with the absorber on the backside of the wafer and the CMOS processed readout unit on the front side.

    [0035] FIG. 3B is a top view of 9 buttable pixel detector tiles making up part of a FPD.

    [0036] FIG. 3C is a cross-sectional view of two buttable pixel detector tiles making up part of a FPD.

    [0037] FIG. 4A is a cross-sectional view of a monolithic pixel detector with a bonded absorber crystal on the back of a CMOS processed readout unit.

    [0038] FIG. 4B is a cross-sectional view of a monolithic pixel detector with a pixelated absorber crystal bonded to the back of a CMOS processed readout unit.

    [0039] FIG. 4C is a cross-sectional view of a monolithic pixel detector with a substrate with an epitaxial absorber layer bonded to the back of a CMOS processed readout unit.

    [0040] FIG. 4D is a cross-sectional view of a monolithic pixel detector with a substrate with a pixelated epitaxial absorber layer bonded to the back of a CMOS processed readout unit.

    [0041] FIG. 5A is a cross-sectional view of a CMOS processed wafer with a readout unit.

    [0042] FIG. 5B is a cross-sectional view of a CMOS processed wafer with a readout unit and a handling wafer.

    [0043] FIG. 5C is a cross-sectional view of a thinned CMOS processed wafer bonded to a handling wafer.

    [0044] FIG. 5D is a cross-sectional view of a thinned CMOS processed wafer with a readout unit and an absorber layer.

    [0045] FIG. 5E is a cross-sectional view of a thinned CMOS processed wafer with a readout unit and a handling wafer bonded to the front, and an absorber layer bonded to the back.

    [0046] FIG. 5F is a cross-sectional view of a thinned CMOS processed wafer with a readout unit, a handling wafer bonded to the front, and a pixelated and passivated absorber layer bonded to the back.

    [0047] FIG. 5G is a cross-sectional view of a thinned CMOS processed wafer with a readout unit, a handling wafer bonded to the front, and a pixelated, passivated and contacted absorber layer bonded to the back.

    [0048] FIG. 6A is a cross-sectional view of a CMOS processed wafer with a readout unit.

    [0049] FIG. 6B is a cross-sectional view of a wafer with a pixelated and passivated epitaxial absorber layer.

    [0050] FIG. 6C is a cross-sectional view of a CMOS processed wafer with a readout unit and a handling wafer.

    [0051] FIG. 6D is a cross-sectional view of a wafer with a pixelated and passivated epitaxial absorber layer and a handling wafer.

    [0052] FIG. 6E is a cross-sectional view of a thinned CMOS processed wafer bonded to a handling wafer.

    [0053] FIG. 6F is a cross-sectional view of a thinned substrate with a pixelated epitaxial absorber layer bonded to a handling wafer.

    [0054] FIG. 6G is a cross-sectional view of a flipped over thinned substrate with a pixelated epitaxial absorber layer bonded to a handling wafer.

    [0055] FIG. 6H is a cross-sectional view of a thinned CMOS processed wafer bonded to a thinned substrate with a pixelated epitaxial absorber layer.

    [0056] FIG. 6I is a cross-sectional view of a thinned CMOS processed wafer bonded to a thinned wafer with a pixelated epitaxial absorber layer after removal of the handling wafer.

    [0057] FIG. 6J is a cross-sectional view of a thinned CMOS processed wafer bonded to a thinned wafer with a pixelated epitaxial absorber layer after removal of handling wafer and bonding residues.

    [0058] FIG. 6K is a cross-sectional view of a thinned CMOS processed wafer bonded to a thinned wafer with a pixelated, electrically contacted epitaxial absorber layer.

    [0059] FIG. 7A is a cross-sectional view of a CMOS processed wafer with a readout unit.

    [0060] FIG. 7B is a cross-sectional view of a wafer with a pixelated and passivated epitaxial absorber layer.

    [0061] FIG. 7C is a cross-sectional view of a CMOS processed wafer with a readout unit and a handling wafer.

    [0062] FIG. 7D is a cross-sectional view of a wafer with a pixelated and passivated epitaxial absorber layer after chemical mechanical polishing.

    [0063] FIG. 7E is a cross-sectional view of a thinned CMOS processed wafer bonded to a handling wafer.

    [0064] FIG. 7F is a cross-sectional view of a thinned CMOS processed wafer bonded to a pixelated epitaxial absorber layer.

    [0065] FIG. 7G is a cross-sectional view of a thinned CMOS processed wafer bonded to a pixelated epitaxial absorber layer after substrate removal.

    [0066] FIG. 7H is a cross-sectional view of a thinned CMOS processed wafer with a readout unit bonded to a pixelated epitaxial absorber layer after substrate removal and electrical contact formation.

    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

    [0067] It is the aim of this invention to enable a multitude of improved capabilities and new applications for X-ray 3D imaging for example in mammography and in the interventional suite at lower radiation dose by overcoming the limits of actual absorption materials in detectors and manufacturing processes.

    [0068] The invention solves in particular the problems of materials incompatibility preventing the fabrication of sensitive, large area monolithic pixel detectors (FPD) employing high-Z materials to enhance absorption especially of X-ray photons with energies typically above 40 keV for use for example in C-arm Cone Beam Computed Tomography (CBCT) units. It is based on low-temperature direct wafer bonding techniques, preferably below 100 C. or even at room temperature, by means of which a CMOS processed readout unit and a single crystal absorber are combined in a monolithic detector structure. The invention is applicable in principle to any absorber material of which large wafers consisting of high quality single crystals are available or may become available in the future, such as for example GaAs, Ge, CdTe, Cd.sub.1-xZn.sub.xTe with x typically around 10% and SiGe. Alternatively, the invention is applicable to absorber materials which can be grown epitaxially on large Si wafers, provided they are substantially defect-free. One preferred class of materials identified to be suitable in particular for mammography applications are Si.sub.1-xGe.sub.x alloys with a Ge content x between about 0.2x0.8 or even more preferably between about 0.6x0.8. The band structure of Si.sub.1-xGe.sub.x alloys is Si-like with band gaps above 0.9 eV for 0x0.8 according to FIG. 1 (see for example J. Weber et al. in Phys. Rev. B 40, 5683 (1989), the entire disclosure of which is hereby incorporated by reference). These band gaps are large compared to that of Ge amounting to 0.66 eV. The thermal generation of charge carriers will therefore be correspondingly lowered, resulting in a much higher resistivity and hence lower dark current of detectors based on such alloy absorbers. This in turn is expected to greatly relax the cooling requirements for these detectors.

    [0069] Referring now to FIG. 2, a CBCT unit with energy integrating FPD based on indirect detection by scintillators and thin film photodiodes or on direct detectors having polycrystalline or amorphous absorber layers and thin film transistors known in the art is replaced with CBCT system 1 having FPD 8 equipped with a single crystal absorber communicating with a CMOS processed readout unit in which analog electrical signals generated by X-rays in the absorber are further amplified, shaped and transformed into digital signals. The readout unit has photon counting capability, enhancing the sensitivity for X-ray detection by approximately a factor of ten compared to polycrystalline or amorphous absorber systems. FPD 8 has a high spatial resolution up to about 100 m or about 50 m or even about 20 m and is mounted on C-arm 2 along with at least one X-ray source 9. The readout unit communicates with one or more devices providing data collection, computation and/or storage functionality (e.g. a data collection device, a computation device and a storage device), disposed to receive electrical signals from the FPD and to generate computed tomography images on at least one computer screen.

    [0070] Referring now to generic embodiment 100 of a FPD of FIG. 3A, the embodiment has a monolithic CMOS integrated pixel detector consisting of CMOS processed chip 12 with readout unit 14 on the front side 16 and absorber 18 attached by direct wafer bonding on the back side 20. CMOS processed chip 12 is preferably a Si chip as known in the art. X-rays 22 incident on absorber 18 may create electron-hole pairs 24 which may be pulled apart, the individual charges drifting towards the front side 16 of chip 12 and the surface 34 of absorber 18, respectively, when an electric field represented by electric field lines 26 is present in absorber 18 of thickness h and in drift region 28 of Si chip 12 of thickness d. One preferred way of establishing this electric field is to use very low doping giving a first conductivity type to chip 12 (for example n-doping). Preferably, the low doping of chip 12 results in a high resistivity of 0.5-2 kcm or 2-5 kcm or even 5-20 kcm. Similarly, absorber wafer 18 is preferably undoped or low doped as well, and exhibits a conductivity of opposite type to that of chip 12 (for example p-doping). Absorber wafer 18 need not be actively doped at all as long as its conductivity type is opposite to that of chip 12. Chip 12 and absorber 18 therefore form a heterojunction p-n diode characterized by the presence of a large electric field in the space charge region when the diode is reverse biased by applying voltage 30 of the appropriate sign.

    [0071] Depending on the doping sequence and the sign of the voltage 30 applied to the metallized back contact 32 of absorber 18, either holes 42 or electrons 44 may drift along the electric field lines 26 towards the front side 16 of chip 12 to be collected by implants 38 defining the pixels of the detector of size L. The pixel size L may be in the range of about 5-200 m, or preferably in the range of about 10-100 m, or even more preferably in the range of about 20-50 m. The electrical signals induced by the charges 42 or 44 collected by implants 38 may subsequently be processed by circuits 40 of readout unit 14. It is advisable to keep the thickness d of drift region 28 low in order to limit voltage 30 required for its depletion. Preferably the thickness d is in the range of 10-200 m or even more preferably about 10-50 m. The optimum thickness h of absorber 18 depends on the absorber material and the energies of the particles to be detected. It may range from about 20 m to 200 m or from 200 m to 1 mm or even to several mm. For example for mammography applications a 100-200 m thick Ge-rich Si.sub.1-xGe.sub.x absorber may be sufficient. For applications requiring X-ray energies substantially above 30 keV thicker absorbers must be used and/or absorbers from materials with higher Z. Fully CMOS processed chip 12, including all metallization layers, may for example have a size of about 22 cm.sup.2 or larger such as 44 cm.sup.2 or 66 cm.sup.2 or 1010 cm.sup.2 or even 1515 cm.sup.2 or yet more, depending on the available size of absorber 18. In the limiting case, chip 12 may for example cover a substantial part of a complete 200 mm wafer or even a 300 mm wafer.

    [0072] Referring now to FIG. 3B, a major advantage of the direct wafer bonding approach of the invention is that, for example, readout chips 54-78 are buttable, preferably on four sides, with minimal dead space 80, 84 between the tiles. Spacings 80, 84 may, for example, be smaller than 100 m or even smaller than 50 m. In the example of FIG. 3B CMOS processed readout chips are direct-wafer-bonded to absorber wafer 50 which may for example be as large as 200 mm or even 300 mm. Note that many more tiles than shown in FIG. 3B may be bonded to absorber wafer 50. In principle, the whole CMOS processed readout wafer may be bonded to absorber 50. Alternatively, when absorber areas are of smaller size, for example of the size of single readout chips, the absorber pieces may be bonded to the readout wafer by direct wafer bonding. Much larger than wafer scale FPD can be made for example by tiling several of the structures of FIG. 3B, n this way, FPD with a size for example of 2020 cm.sup.2 or even larger, for example about 4040 cm.sup.2, can be made.

    [0073] Referring now to FIG. 3C, another major advantage of the direct wafer bonding approach of the invention is that electrical contacts to the readout wafer do not require the fabrication of TSV. In fact, all electrical contacts, with the possible exception of guard ring contacts in the case of small absorber areas, can be made on the front side 16 of readout chips 12. This is a big difference compared with the approach of bump bonded pixel detectors, wherein the absorber covers the upper side 16 of readout chips 12, such that TSV are needed to contact the chips electrically. Especially for absorber materials for which no large wafers are available, it may be advantageous to implant guard rings around the periphery of the tiles prior to direct wafer bonding. In this case, the guard rings are preferably contacted by TSV. Alternatively, the guard rings may be foreseen on the readout chip itself, in which case no TSV are needed at all.

    [0074] Referring now to FIG. 4A, the first embodiment 200 of monolithically integrated pixel detector 210 is made up of a CMOS processed wafer 212 with readout unit 214 on the front side 216 and absorber 218 on the back side 220. Embodiment 200 may be suitable especially for absorber layers 218, the thermal expansion coefficients of which do not deviate strongly from that of Si, such as for example SiC. It may also be applicable to absorber layers 218 which are thermally mismatched with Si, such as for example GaAs, Ge, CdTe and CdZnTe as long as the operating temperature of detector 210 does not deviate much from room temperature. A temperature rise to 50 C. or even 100 C. may still be considered to be permissible. Single crystalline absorber layer 218 is bonded by direct wafer bond 250 at or near room temperature to the backside 220 of CMOS processed wafer 212. Direct wafer bond 250 is preferably a covalent bond, providing an intimate electrical contact, preferably with few or no interface states or interface states passivated for example by hydrogen to improve interfacial charge transport (i.e. to attain ohmic behavior), between absorber layer 218 and drift region 228 across the entire backside 220 of wafer 212. In order for an intimate electrical contact to be established the backside of wafer 212 and the bonding surface of absorber layer 218 have to be atomically flat and particle-free as well as oxide-free. It may be advisable to subject the backside 220 of wafer 212 and the bonding surface of absorber layer 218 to a chemical-mechanical polishing step prior to the surface treatment required for oxide-free covalent bonding. The bonding process may comprise steps of optional pre-bonding annealing of the as yet oxidized surfaces to reduced moisture and optional mild post-bonding annealing. Pre- and post-bonding annealing are carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C. In any case they must be below about 450 C. in order to avoid disintegration of the metallization of CMOS processed wafer 212.

    [0075] When a large voltage 230 is applied to metallized back contact 232 of the absorber, resulting substantially in the depletion of absorber 218 and drift region 228 of CMOS processed wafer 212, e-h pairs generated by absorbed high energy material particles or photons are separated in the associated electric field and collected by implants 238, defining the pixel size, and metal electrode 232, respectively.

    [0076] Referring now to FIG. 4B, the second embodiment 200 of monolithically integrated pixel detector 210 is made up of CMOS processed wafer 212 with readout unit 214 on the front side 216 and absorber 218 on the back side 220. Embodiment 200 may be of suitable especially for absorber layers 218 which are lattice matched but thermally mismatched with Si, such as for example GaP. It may be applicable also to absorber layers 218 which are thermally and lattice mismatched with Si, such as for example GaAs, Ge, CdTe, CdZnTe and SiC. Absorber layer 218 is pixelated, i.e. it is made up of distinct absorber patches 252 of width w.sub.1, separated by trenches 254 of width w.sub.2. The width w.sub.1 of distinct absorber patches 252 may be larger, equal or smaller than the pixel size L defined by implants 238. The width w.sub.2 of trenches 254 is preferably smaller than the width w.sub.1 of distinct absorber patches 252 or even more preferably much smaller. The width w.sub.2 of trenches 254 may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques known in the art (see for example X. Li et al., in Sensors and Actuators A87, 139 (2001) and E. H. Klaassen, in Sensors and Actuators A52, 132 (1996), the entire disclosure of which are hereby incorporated by reference). Preferably backside 220 of CMOS processed wafer 212 and absorber patches 252 are bonded by covalent bonds 250 providing an intimate electrical contact, preferably with few or no interface states or interface states passivated for example by hydrogen to improve interfacial charge transport (i.e. to attain ohmic behavior), between absorber layer 218 and drift region 228 across the entire backside 220 of wafer 212. In order for an intimate electrical contact to be established the backside of wafer 212 and the bonding surface of absorber layer 218 have to be atomically flat and particle-free as well as oxide-free. It may be advisable to subject backside 220 of wafer 212 and the bonding surface of absorber layer 218 to a chemical-mechanical polishing step prior to the surface treatment required for oxide-free covalent bonding. The bonding process preferably includes steps of optional pre-bonding annealing to reduced moisture on the as yet oxidized surfaces and post-bonding annealing. Patterning of absorber 218 into absorber patches 252 is preferably carried out after the optional low temperature pre-bonding anneal in order to avoid stress exerted during the optional higher temperature post-bonding anneal because of different thermal expansion coefficients of wafer 212 and absorber layer 218. Pre- and post-bonding annealing are carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C. In any case they must be below about 450 t in order to avoid disintegration of the metallization of CMOS processed wafer 212. Distinct absorber patches 252 may be electrically connected by metallized back contact 232 extending substantially across the whole surface of the absorber.

    [0077] When a large voltage 230 is applied to metallized back contact 232 of absorber 218, resulting substantially in the depletion of absorber 218 and drift region 228 of CMOS processed wafer 212, e-h pairs generated by absorbed high energy material particles or photons are separated in the associated electric field and collected by implants 238, defining the pixel size L, and metal electrode 232, respectively.

    [0078] Referring now to FIG. 4C, the third embodiment 200 of monolithically integrated pixel detector 210 is made up of CMOS processed wafer 212 with readout unit 214 on the front side 216 and absorber 218 on the back side 220. Embodiment 200 is most suitable especially for absorber layers 218 which cannot be grown in the form of large single crystals suitable for wafer fabrication, but which can be grown in the form of epitaxial layers on a large Si substrate 256. Absorber layer 218 is preferably made from a semiconductor material which is substantially lattice matched to the Si substrate, such as for example GaP, in order to avoid a high density of misfit dislocations to be present at interface 258 between substrate and epitaxial layer. It may also comprise compositionally graded layers, where the layers closest to the interface with the Si substrate are lattice matched, such as GaP.sub.1-xAs.sub.x with x ranging from 0 to 1 within a thickness of several m, after which the full lattice mismatch of about 4% characteristic of pure GaAs is reached. Depending on the grading rate, i.e., the rate at which the composition x is changed as a function of layer thickness, dislocations are distributed over a smaller or larger volume of the graded layer. The smaller the grading rate, the lower the density of misfit dislocations per volume fraction of the layer. The density of threading dislocations extending to the growth front of the graded layer is correspondingly reduced with decreasing grading rate.

    [0079] In embodiment 200, direct wafer bond 250 is a covalent SiSi bond between back side 220 of CMOS processed wafer 212 and substrate 256 on which absorber 218 is epitaxially grown. In order for an intimate electrical contact to be established, the backside of wafer 212 and the bonding surface of substrate 256 have to be atomically flat and particle-free as well as oxide-free. It may be advisable to subject the backside 220 of wafer 212 and the bonding surface of substrate 256 to a chemical-mechanical polishing step prior to the surface treatment required for oxide-free covalent bonding. The bonding process preferably includes steps of optional pre-bonding annealing to reduce moisture on the as yet oxidized surfaces and post-bonding annealing. Pre- and post-bonding annealing are carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C. In any case they must be below about 450 C. in order to avoid disintegration of the metallization of CMOS processed wafer 212.

    [0080] When a large voltage 230 is applied to metallized back contact 232 of the absorber, resulting substantially in the depletion of absorber 218 and drift region 228 of CMOS processed wafer 212, c-h pairs generated by absorbed high energy material particles or photons are separated in the associated electric field and collected by implants 238, defining the pixel size L, and metal electrode 232, respectively.

    [0081] Referring now to FIG. 4D, the fourth embodiment 200 of monolithically integrated pixel detector 210 is made up of CMOS processed wafer 212 with readout unit 214 on the front side 216 and pixelated absorber 218 on the back side 220. Embodiment 200 is the preferred embodiment for absorber layers 218 which cannot be grown in the form of large single crystals suitable for wafer fabrication, but which can be grown in the form of epitaxial patches of width w.sub.3 separated by trenches 254 of width w.sub.4 on a large Si substrate 256. The width w.sub.3 of distinct absorber patches 252 may be larger, equal or smaller than the pixel size L defined by implants 238. The width w.sub.4 of trenches 254 are preferably smaller that the width w.sub.3 of absorber patches 252 and even more preferably much smaller. For absorber patches 252 defined by the spacing of dielectric mask openings in ART, they may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques, for example 1-5 m. The width w.sub.4 of trenches obtained by self-limited lateral growth of absorber patches 252 may be even smaller, for example 100 nm-1 m, or even 20 nm-100 nm.

    [0082] Embodiment 200 is the most preferred embodiment for absorber layers which are both lattice and thermally mismatched with the Si substrate 256. The most preferred material of absorber layers 218 may be a Si.sub.1-xGe.sub.x alloy which may preferably have a Ge content above 20%. In a preferred aspect of the embodiment the Si.sub.1-xGe.sub.x alloy may have a high Ge content x of about 0.6x0.8. When having such SiGe alloy absorbers with a thickness of about 100-200 m, embodiment 200 is especially well suited for applications limited to X-ray energies below 40 keV, such as mammography applications. In an even more preferred aspect of the embodiment, the Si.sub.1-xGe.sub.x alloy may be compositionally graded to a high Ge content x of about 0.6x0.8 and optionally have a cap region of constant composition substantially equal to the final composition of the graded part, which may for example be graded linearly. In a most preferred aspect of embodiment 200 interface 258 between Si substrate 256 and pixelated absorber 218 is substantially defect-free. This can be achieved for example by choosing width w.sub.3 of semiconductor patches 252 forming pixelated absorber 218 and the grading rate both sufficiently small to permit elastic relaxation of the misfit stress during the epitaxial growth of absorber 218 (see for example M. Salvalaglio et al. in J. Appl. Phys. 116, 104306 (2014), and F. Isa et al. in Acta Materialia 114, 97 (2016), the entire disclosures of which are hereby incorporated by reference). The grading rate may preferably be chosen below about 3%, or below about 2%, or even below 1%. In other aspects of the embodiment interface areas 258 between substrate 256 and patches 252 of pixelated absorber 218 may not be substantially defect-free, but of sufficiently small size to keep dark currents at acceptable levels, when a large voltage 230 is applied to metallized back contact 232 of absorber 218 and implants 238 of CMOS processed wafer 212. As known to one skilled in the art, such small interface regions are commonly employed for example in techniques of aspect ratio trapping (ART), wherein threading dislocations are trapped at the sidewalls of windows in a dielectric mask into which a semiconductor is selectively grown (see for example I. berg et al., IEDM San Francisco, 2010, the entire disclosure of which is hereby incorporated by reference). With the help of ART, in addition, other absorber materials may be used apart from SiGe, such as GaAs, CdTe or CdZnTe.

    [0083] The width w.sub.4 of trenches 254 is preferably smaller (ratio of about 1:2_) than the size w.sub.3 of absorber patches 252 or even more preferably much smaller (ratio of about 1_:10 or even 1:100). The width w.sub.4 of trenches may be below 1 m or below 200 nm or even below 100 nm, when a self-limited epitaxial growth process and deeply patterned substrates are used to define the size w.sub.3 of absorber patches 252 (see for example International Patent Application No. WO 2011/135432 to von Knel, the entire disclosure of which is hereby incorporated by reference). Alternatively, when a method of ART is used to define the size w.sub.3 of absorber patches 252, the width we of trenches 254 may be defined by the spacing of dielectric windows, which may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques used for patterning the dielectric mask. Preferably backside 220 of CMOS processed wafer 212 and substrate 256 are bonded by covalent bonds 250 providing an intimate electrical contact, preferably with few or no interface states or interface states passivated for example by hydrogen to improve interfacial charge transport (i.e. to attain ohmic behavior), between absorber layer 218 and drift region 228 across the entire backside 220 of wafer 212. In order for an intimate electrical contact to be established, backside 220 of wafer 212 and the bonding surface of substrate 256 also have to be atomically flat and particle-free as well as oxide-free. It may be advisable to subject backside 220 of wafer 212 and the bonding surface of absorber layer 256 to a chemical-mechanical polishing step prior to the surface treatment required for oxide-free covalent bonding. The bonding process preferably includes steps of optional pre-bonding annealing to reduced moisture on the as yet oxidized surfaces and optional post-bonding annealing. Pre- and post-bonding annealing steps are carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C. In any case they must be below about 450 C. in order to avoid disintegration of the metallization of CMOS processed wafer 212. Distinct absorber patches 252 may be electrically connected by metallized back contact 232 extending substantially across the whole surface of the absorber.

    [0084] When a large voltage 230 is applied to metallized back contact 232 of absorber 218, resulting substantially in the depletion of absorber 218 and drift region 228 of CMOS processed wafer 212, e-h pairs generated by absorbed high energy material particles or photons are separated in the associated electric field and collected by implants 238, defining the pixel size L, and metal electrode 232, respectively.

    [0085] Referring now to FIGS. 5A-5G, fabrication 300 of monolithic pixel detector 310 may include the following steps. In a first step (FIG. 5A) Si wafer 312 which may be lightly n-doped or lightly p-doped with a resistivity preferably above 500 cm is CMOS processed to obtain readout electronics 314, the part 340 of which may be contained in every pixel of size L, defined by the spacing of charge collection implants 338. In a second step (FIG. 5B), handling wafer 360 may be bonded onto the optionally chemically-mechanically polished surface 316 of wafer 312. The bond 370 between surface 316 of CMOS wafer 312 and surface 362 of handling wafer 360 may not be a permanent bond, but must be strong enough to permit thinning of the CMOS wafer in a third step (FIG. 5C) for example in a chemical-mechanical polishing step to reduce the thickness d.sub.1 of lightly doped region 328 to below 200 m. In a preferred aspect of the embodiment, the thickness d.sub.1 is below 100 m, and in an even more preferred aspect it may be as low as for example 10-20 m. In a fourth step (FIG. 5D) surface 320 of thinned CMOS wafer 312 and upper surface 336 of absorber wafer 318 (having lower surface 334) of thickness d.sub.2, which may also have undergone chemical-mechanical polishing and an optional shallow hydrogen implant, may be prepared for oxide-free covalent bonding for example by sputter etching the surface oxide in a neutralized plasma as known in the art (see for example C. Fltgen in ECS Trans. 64, 103 (2014), the entire disclosure of which is hereby incorporated by reference). An optional pre-bonding anneal and optional post-bonding anneal at low temperature in a fifth step (FIG. 5E), preferably in the range between about 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C., provides strong and electrically conductive bond 350 between backside 320 of CMOS processed and thinned wafer 312 and surface 336 of absorber wafer 318. The optional post-bonding anneal may help in eliminating any interfacial barriers blocking electrical charge transport across the bonding interface, for example by causing optionally implanted hydrogen to passivate the dangling bonds so that ohmic behavior is attained.

    [0086] If the absorber material is characterized by a large mismatch of the thermal expansion coefficients with respect to those of Si wafer 312, absorber wafer 318 is preferably patterned in the form of distinct patches 352 of width w.sub.1 separated by trenches 354 of width w.sub.2 in a sixth step (FIG. 5F) before the post-bonding anneal in order to avoid any undesirable thermal stress. The width w.sub.1 of distinct absorber patches 352 may be larger, equal or smaller than the pixel size L defined by implants 338. The width w.sub.2 of trenches 354 is preferably smaller than the size wt of absorber patches 352 or even more preferably much smaller. The width w.sub.2 of trenches 354 may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques known in the art (see for example X. Li et al., in Sensors and Actuators A87, 139 (2001) and E. H. Klaassen, in Sensors and Actuators A52, 132 (1996), the entire disclosure of which are hereby incorporated by reference). It may be advisable to coat sidewalls 374 of distinct absorber patches 352 with a dielectric film 376 providing a surface passivation and thereby reducing leakage currents during the operation of the pixel sensor. In a seventh step (FIG. 5G) trenches 354 may be optionally filled with insulating material 372, and metallic contact 332 may be formed preferably as a continuous metallization layer connecting distinct absorber patches 352 in parallel.

    [0087] When a large voltage 330 is applied to metallized back contact 332 of absorber 318, resulting substantially in the depletion of absorber 318 and drift region 328 of thinned CMOS processed wafer 312, e-h pairs generated by absorbed high energy material particles or photons are separated in the associated electric field and collected by implants 338 of pixel detector 310.

    [0088] Referring now to FIGS. 6A-6K, fabrication 400 of monolithic pixel detector 410, may include the following steps, although not necessarily executed in the order shown. In a first step (FIG. 6A), Si wafer 412 with front side 416 and backside 420, which may for example be lightly n-doped or lightly p-doped with a resistivity preferably above 500 cm, is CMOS processed to obtain readout electronics 414 part 440 of which may be contained in every pixel of size L, defined by the spacing of charge collection implants 438. In a second step (FIG. 6B), Si wafer 456 may be patterned and cleaned in order to serve as a substrate for absorber 418 to be epitaxially grown in the form of distinct patches 452 of width w.sub.3 and height h.sub.2 separated by trenches 454 of width w.sub.4. The width w.sub.3 of distinct absorber patches 452 may be larger, equal or smaller than the pixel size L defined by implants 438. The width w.sub.4 of trenches may be below 1 m or below 200 nm or even below 100 nm, when a self-limited epitaxial growth process and deeply patterned substrates are used to define the size w.sub.3 of absorber patches 452 as known in the art (see for example International Patent Application No. WO 2011/135432 to von Knel, the entire disclosure of which is hereby incorporated by reference). Alternatively, when a method of ART is used to define the size w.sub.3 of absorber patches 452, the width of trenches w.sub.4 may be defined by the spacing of dielectric windows, which may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques known in the art (see for example X. Li et al., in Sensors and Actuators A87, 139 (2001) and E. H. Klaassen, in Sensors and Actuators A52, 132 (1996), the entire disclosure of which are hereby incorporated by reference). After the epitaxial growth, sidewalls 474 of distinct patches 452 may optionally be passivated by a dielectric passivation layer. The passivation layer may comprise for example first dielectric layer 436 designed to control surface leakage along sidewalls 474 when pixel detector 410 is in operation. First dielectric layer may be a thermal oxide or an oxide formed by atomic layer deposition (ALD). The passivation layer may optionally comprise second dielectric layer 476, which may provide additional protection of sidewalls 474 against environmental influences. It may for example be made of Al.sub.2O.sub.3 which may be deposited by atomic layer deposition as known in the art. Trenches 454 may additionally be filled by dielectric filling material 472 to provide stability in an optional step of chemical mechanical polishing as a preparation of absorber surface 434 for a subsequent wafer bonding step.

    [0089] Referring to FIG. 6C, in third step, surface 416 of Si wafer 412 may undergo an optional chemical mechanical polishing step before being bonded to surface 462 of handling wafer 460 as a means to provide mechanical stability in the subsequent thinning of drift region 428 for example in a chemical mechanical polishing step. Referring to FIG. 6D, in a fourth similar step, surface 434 of epitaxial absorber 418 may be bonded to surface 482 of handling wafer 480 as a means to provide mechanical stability in the subsequent thinning of substrate 456 for example in a chemical mechanical polishing step. Referring now to FIG. 6E, in the fifth step, drift region 428 of CMOS processed wafer 412 is thinned for example in a plasma etching or chemical mechanical polishing step. Thinned wafer 412 with drift region 428 has a thickness d.sub.1 which is preferably between about 10-100 m, and even more preferably between about 10-20 m. Referring now to FIG. 6F, in a sixth step, substrate 456 is thinned for example in a plasma etching or chemical mechanical polishing step. Thinned substrate 456 has a thickness d.sub.2 which is preferably between about 10-100 m, and even more preferably between about 10-20 m. Surface 420 of thinned wafer 412 and surface 490 of thinned substrate 456 may optionally be provided with a shallow hydrogen implant and prepared for covalent bonding for example by sputter etching the surface oxide in a neutralized plasma as known in the art (see for example C. Fltgen in ECS Trans. 64, 103 (2014), the entire disclosure of which is hereby incorporated by reference). Referring now to FIG. 6G, in a seventh step, thinned substrate 456 or thinned CMOS wafer 412 is flipped upside down, such that surfaces 420 and 490 prepared for wafer bonding face each other to be joined in covalent bond 450 in an eighth step (FIG. 6H) after an optional pre-bonding anneal prior to the removal of the surface oxide. Optional pre- and post-bonding annealing steps are both carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C., or between 200 C. and 300 C., or between 300 C. and 400 C. In any case, they must be below about 450 C. in order to avoid disintegration of the metallization of CMOS processed wafer 412. The optional post-bonding anneal may help in eliminating any interfacial barriers blocking electrical charge transport across the bonding interface, for example by causing optionally implanted hydrogen to passivate the dangling bonds so that ohmic behavior is attained. After the optional post-bonding anneal handling wafer 480 is removed in a ninth step (FIG. 6I), whereby surfaces 434 of absorber patches 452 is again exposed. Referring now to FIG. 6J, in a tenth step, surfaces 434 of absorber patches 452 may be subjected to an optional cleaning step to remove the bonding residues of handling wafer 480. Subsequently, trenches 454 may be optionally be filled by filling material 472 unless said trenches have already been filled by filling material 472 in the second step (FIG. 6B). Referring now to FIG. 6K, in an eleventh step, complete pixel detector 410 is finally obtained by metallizing surfaces 434 of absorber patches 452 with metal layer 432 acting as a metallic contact to which high voltage lead 430 may be attached to deplete drift regions 428, 456 and absorber 418.

    [0090] Fabrication 400 may be the most preferred fabrication method of pixel detector 410 for absorber layers 418 which are both lattice and thermally mismatched with the Si substrate 456. The preferred material of absorber layers 418 may be a Si.sub.1-xGe.sub.x alloy which may preferably have a Ge content above 20%. A Si.sub.1-xGe.sub.x alloy with a high Ge content x of about 0.6x0.8 may be an especially suitable alloy for absorber layer 418. Absorber layers with a thickness of 100-200 m made from Si.sub.1-xGe.sub.x alloys with high Ge content are especially well suited for applications limited to X-ray energies below 40 keV, such as mammography applications. The most preferred Si.sub.1-xGe.sub.x alloy may be compositionally graded to a high Ge content x of about 0.6x0.8 and optionally have a cap region of constant composition substantially equal to the final composition of the graded part, which may for example be graded linearly. In the most preferred fabrication 400 of pixel detector 410, interface 458 between Si substrate 456 and pixelated absorber 418 is substantially defect-free. This may for example be achieved by choosing width w.sub.3 of semiconductor patches 452 forming pixelated absorber 418 and the grading rate both sufficiently small to permit elastic relaxation of the misfit stress during the epitaxial growth of absorber 418 as proven to be effective in the simpler example of step graded SiGe nanostructures (see for example M. Salvalaglio et al., in J. Appl. Phys. 116, 104306 (2014), and F. Isa et al. in Acta Materialia 114, 97 (2016), the entire disclosures of which are hereby incorporated by reference). The grading rate may preferably be chosen below about 3%, or below about 2%, or even below 1%. In other aspects of the embodiment, interface areas 458 between substrate 456 and patches 452 of pixelated absorber 418 may not be substantially defect-free, but of sufficiently small size to keep dark currents at acceptable levels, when a large voltage 430 is applied to metallized back contact 432 of absorber 418 and implants 438 of thinned CMOS processed wafer 412. Such small interface regions are commonly employed for example in techniques of aspect ratio trapping (ART), wherein threading dislocations are trapped at the sidewalls of windows in a dielectric mask into which a semiconductor is selectively grown (see for example I. berg et al., in IEDM 2014, the entire disclosure of which is hereby incorporated by reference). With the help of ART also other absorber materials may be used apart from SiGe, such as GaAs, Ge, CdTe or CdZnTe.

    [0091] Referring now to FIGS. 7A-7H, alternative fabrication 500 of monolithic pixel detector 510, may include the following steps, although not necessarily executed in the order shown. Referring now to FIG. 7A, in a first step, Si wafer 512 with front side 516 and backside 520, which may for example be lightly n-doped or lightly p-doped with a resistivity preferably above 500 cm, is CMOS processed to obtain readout electronics 514, part 540 of which may be contained in every pixel of size L, defined by the spacing of charge collection implants 538. Referring now to FIG. 7B, in a second step, Si wafer 556 may be patterned and cleaned in order to serve as a substrate for absorber 518 to be epitaxially grown in the form of distinct patches 552 forming interface 558 with Si substrate 556. Patches 552 have width w.sub.3 and height h.sub.2 and are separated by trenches 554 of width w.sub.4. The width w.sub.3 of distinct absorber patches 552 may be larger, equal or smaller than the pixel size L defined by implants 538. The height of absorber patches 552 may be about 20-50 m or preferably about 50-100 m or even more preferably about 100-200 m. The width w.sub.4 of trenches may be below 1 m or below 200 nm or even below 100 nm, when a self-limited epitaxial growth process and deeply patterned substrates are used to define the size w.sub.3 of absorber patches 552 as known in the art (see for example International Patent Application No. WO 2011/135432 to von Knel, the entire disclosure of which is hereby incorporated by reference). Alternatively, when a method of ART is used to define the size w.sub.3 of absorber patches 552, the width of trenches w.sub.4 may be defined by the spacing of dielectric windows, which may be as narrow as the minimum width achievable by the lithography and deep reactive ion etching techniques known in the art (see for example X. Li et al., in Sensors and Actuators A87, 139 (2001) and E. H. Klaassen, in Sensors and Actuators A52, 132 (1996), the entire disclosure of which are hereby incorporated by reference). After the epitaxial growth sidewalls 574 of distinct patches 552 may optionally be passivated by a dielectric passivation layer. The passivation layer may comprise for example first dielectric layer 536 designed to control surface leakage along sidewalls 574 when pixel detector 510 is in operation. First dielectric layer may be a thermal oxide or an oxide formed by atomic layer deposition (ALD). The passivation layer may optionally comprise second dielectric layer 576, which may provide additional protection of sidewalls 574 against environmental influences. It may for example be made of Al.sub.2O.sub.3 which may be deposited by atomic layer deposition as known in the art. Trenches 554 may additionally be filled by dielectric filling material 572 to provide stability in an optional step of chemical mechanical polishing as a preparation of absorber surface 534 for a subsequent covalent wafer bonding step.

    [0092] Referring now to FIG. 7C, in third step, surface 516 of Si wafer 512 may undergo an optional chemical mechanical polishing step before being bonded to surface 562 of handling wafer 560 as a means to provide mechanical stability in the subsequent thinning of drift region 528 for example in a chemical mechanical polishing step. Referring now to FIG. 7D, in a fourth step, surface 534 of epitaxial absorber 518 may subjected to a chemical mechanical polishing step whereby the height of epitaxial absorber may be slightly reduced for example by 1-4 m to the height h.sub.3. Referring now to FIG. 7E, in a fifth step, drift region 528 of CMOS processed wafer 512 is thinned for example in a plasma etching or chemical mechanical polishing step. Thinned wafer 512 with drift region 528 thereby assumes a thickness d.sub.1 which is preferably between about 10-100 m, and even more preferably between about 10-20 m. In a sixth step surface 520 of thinned wafer 512 and surface 534 of absorber 518 may optionally be provided with a shallow hydrogen implant and prepared for covalent bonding for example by sputter etching the surface oxide in a neutralized plasma as known in the art (see for example C. Fltgen in ECS Trans. 64, 103 (2014), the entire disclosure of which is hereby incorporated by reference) and joined in covalent bond 550 after an optional pre-bonding anneal (FIG. 7F). Covalent bond 550 may then be subjected to an optional post-bonding anneal. Optional pre- and post-bonding annealing steps are both carried out at low temperature. Annealing temperatures may range between 100 C. and 200 C. or between 200 C. and 300 C., or between 300 C. and 400 C. In any case they must be below about 450 C. in order to avoid disintegration of the metallization of CMOS processed wafer 512. The optional post-bonding anneal may help in eliminating any interfacial barriers blocking electrical charge transport across the bonding interface, for example by causing optionally implanted hydrogen to passivate the dangling bonds so that ohmic behavior is attained. After the optional post-bonding anneal substrate 556 of epitaxial absorber 518 may be removed in a seventh step (FIG. 7G), either by a chemical mechanical polishing or a plasma etching step to expose surfaces 558 of absorber patches 552. It may be advantageous to etch away also part of absorber patches 552 during this etching step to reduce their height to h.sub.4, especially if their interface with substrate 512, 512 is not defect-free. Height h.sub.4 may be smaller by a few m than height h.sub.3, so that in addition to misfit dislocations also threading dislocations are removed in this etching step. Referring now to FIG. 7H, in an eighth step, complete pixel detector 510 is finally obtained by metallizing surfaces 558 of absorber patches 552 with metal layer 532 acting as a metallic contact to which high voltage lead 530 may be attached to deplete drift regions 528 and absorber 518.

    [0093] Fabrication 500 of pixel detector 510 has the advantage that only the thickness d.sub.1 of thinned drift region 528 along with the height h.sub.4 of absorber patches 552 need to be depleted during detector operation. It may also be a preferred fabrication method of pixel detector 510 for absorber layers 518 which are both lattice and thermally mismatched with the Si substrate 556. The preferred material of absorber layers 518 may be a Si.sub.1-xGe.sub.x alloy which may preferably have a Ge content above 20%. A Si.sub.1-xGe.sub.x alloy with a high Ge content x of about 0.6x0.8 may be an especially suitable alloy for absorber layer 518. Absorber layers with a thickness of 100-200 m made from Si.sub.1-xGe.sub.x alloys with high Ge content are also especially suited for applications limited to X-ray energies below 40 keV, such as mammography applications. The most preferred Si.sub.1-xGe.sub.x alloy may be compositionally graded to a high Ge content x of about 0.6x0.8 and optionally have a cap region of constant composition substantially equal to the final composition of the graded part, which may for example be graded linearly. In the most preferred fabrication 500 of pixel detector 510 interface 558 between Si substrate 556 and pixelated absorber 518 is substantially defect-free. This may for example be achieved by choosing width w.sub.3 of semiconductor patches 552 forming pixelated absorber 518 and the grading rate both sufficiently small to permit elastic relaxation of the misfit stress during the epitaxial growth of absorber 518 as proven to be effective in the simpler example step graded SiGe nanostructures of (see for example M. Salvalaglio et al., in J. Appl. Phys. 116, 104306 (2014), and F. Isa et al. in Acta Materialia 114, 97 (2016), the entire disclosures of which are hereby incorporated by reference). The grading rate may preferably be chosen below about 3%, or below about 2%, or even below 1%. In other aspects of the embodiment interface areas 558 between substrate 556 and patches 552 of pixelated absorber 518 may not be substantially defect-free, but of sufficiently small size to keep dark currents at acceptable levels, when a large voltage 530 is applied to metallized back contact 532 of absorber 518 and implants 538 of thinned CMOS processed wafer 512. As known to one skilled in the art, such small interface regions are commonly employed for example in techniques of aspect ratio trapping (ART), wherein threading dislocations are trapped at the sidewalls of windows in a dielectric mask into which a semiconductor is selectively grown (see for example I. berg et al., in IEDM San Francisco, 2010, the entire disclosure of which is hereby incorporated by reference). With the help of ART also other absorber materials may be used apart from SiGe, such as GaAs, Ge, CdTe or CdZnTe.

    Exemplary Applications of Photon Counting CBCT with Monolithic CMOS Integrated Pixel Detector

    [0094] The CBCT of the present invention is integrated into and used in methods of the following medical applications, either human or veterinary, and other applications as described below.

    Projection Radiography Example

    [0095] The CBCT of the invention is used as a digital radiography system in which the X-rays transmitted through an object are converted into electrical signals in the FPD, generating digital information, which is transmitted and converted into an image displayed on a computer screen either locally or remotely.

    [0096] There are many disease states in which classic diagnosis is obtained by plain radiographs, in combination with systems and methods incorporating the CBCT of the present invention. Examples of systems and method include those to diagnose various types of arthritis and pneumonia, bone tumors, fractures, congenital skeletal anomalies, and the like.

    Interventional Radiology Example

    [0097] The introduction of the monolithic CMOS integrated pixel FPD allows for the replacement of the cesium iodide (CsI) screen in fluoroscope designs. Therefore four dimensional CT (4DCT) is more accurate than fluoroscopy to define the CBCT of the invention even if the field of applications is the same. The photon counting CBCT with monolithic CMOS integrated pixel detectors allows real-time imaging of anatomical structures in motion, and the method is optionally augmented with a radio-contrast agent. Radio-contrast agents are administered by swallowing or injecting into the body of the patient to delineate anatomy, function of the blood vessels and various systems, e.g. the genitor-urinary system or the gastro-intestinal tract. Two radio-contrast agents are presently in common use. Barium sulfate (BaSO4) is administered to the subject orally or rectally for evaluation of the gastro-intestinal tract. Iodine in various formulations is given by oral, rectal, intra-arterial or intravenous pathways. These radio-contrast agents absorb or scatter X-rays, and in conjunction with real-time imaging, permit the imaging of dynamic physiological processes in the digestive tract or blood flow in the vascular system. Iodine contrast agents are also concentrated in abnormal areas in different concentrations than in normal tissues to make abnormalities (e.g. tumors, cysts, inflamed areas) visible.

    [0098] More generally, the CBCT is used in interventional radiology systems and methods. Interventional radiology includes minimally invasive procedures that are guided by imaging systems utilizing systems and methods having the FPD described herein. These procedures are diagnostic or involve treatments, such as angiographic intervention and the systems used therewith. Exemplary systems include those procedures to diagnose and/or treat peripheral vascular disease, renal artery stenosis, inferior vena cava filter placement, gastrostomy tube placement, biliary stent intervention, and hepatic intervention. Non-angiographic procedures such as image guided orthopedic, thoracic, abdominal, head and neck, and neuro surgery, biopsies, brachytherapy or external beam radiotherapy, percutaneous drain and stent placement or radiofrequency ablation are also included. Images created with the assistance of the systems utilizing the pixel detector are used for guidance. The images created with the assistance of the photon counting FPD provide maps that permit the interventional radiologist to guide instruments through the body of a subject to the areas containing disease conditions. These systems and methods minimize the physical tissue trauma to the subject, reduce infection rates, recovery times, and hospitalization stays, such as in angiographic interventions, or non-angiographic procedures like image guided orthopedic, thoracic, abdominal, head and neck, and neuro surgery, biopsies, brachytherapy or external beam radiotherapy, percutaneous drain and stent placement or radiofrequency ablation.

    Addendum

    [0099] The following US patent documents, foreign patent documents, and Additional Publications are incorporated herein by reference thereto and relied upon:

    US Patent Documents

    [0100]

    TABLE-US-00001 5,712,484 January 1998 Harada et al. 6,787,885 B2 September 2004 Esser et al. 8,237,126 B2 August 2012 von Knel et al. 8,378,310 B2 February 2009 Bornefalk et al. 8,792,965 B2 July 2014 Ning et al.

    Other Patent Documents

    [0101]

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