High power positive logic switch

Abstract

A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

Claims

1. A stack of FET switches, at least one FET switch of the stack of FET switches requiring a relatively negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, the stack of FET switches series-coupled on at least one end to a respective end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one of the respective end-cap FETs is configured to be coupled to a corresponding RF signal source and has a gate couplable to the corresponding RF signal source through an associated switch circuit.

2. The invention of claim 1, wherein the switch circuit includes an NMOSFET.

3. The invention of claim 1, wherein the switch circuit includes an NMOSFET series-coupled to a PMOSFET.

4. The invention of claim 1, wherein the switch circuit includes a diode series-coupled to a NMOSFET.

5. The invention of claim 1, wherein the switch circuit includes a diode, NMOSFET, and PMOSFET coupled in series.

6. The invention of claim 1, wherein the switch circuit includes a capacitor series-coupled to a NMOSFET.

7. The invention of claim 1, wherein the switch circuit includes a capacitor, NMOSFET, and PMOSFET coupled in series.

8. A stack of FET switches, at least one FET switch of the stack of FET switches requiring a relatively negative V.sub.GS to turn OFF and configured to operate with positive control voltages, the stack of FET switches series-coupled on at least one end to a respective end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one of the respective end-cap FETs is configured to be coupled to a corresponding RF signal source and has a gate couplable to the corresponding RF signal source through an associated switch circuit.

9. The invention of claim 8, wherein the switch circuit includes an NMOSFET.

10. The invention of claim 8, wherein the switch circuit includes an NMOSFET series-coupled to a PMOSFET.

11. The invention of claim 8, wherein the switch circuit includes a diode series-coupled to a NMOSFET.

12. The invention of claim 8, wherein the switch circuit includes a diode, NMOSFET, and PMOSFET coupled in series.

13. The invention of claim 8, wherein the switch circuit includes a capacitor series-coupled to a NMOSFET.

14. The invention of claim 8, wherein the switch circuit includes a capacitor, NMOSFET, and PMOSFET coupled in series.

15. A FET switch stack, including: (a) one or more positive-logic FETs requiring a relatively negative V.sub.GS to turn OFF and configured so as to not require a negative voltage; (b) a first end-cap FET that turns OFF when the V.sub.GS of the first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs, wherein the first end-cap FET has a gate and is configured to be coupled to a corresponding RF signal source; and (c) at least one switch circuit, each coupled between the gate of the first end-cap FET and the corresponding RF signal source.

16. The invention of claim 15, wherein the switch circuit includes an NMOSFET.

17. The invention of claim 15, wherein the switch circuit includes an NMOSFET series-coupled to a PMOSFET.

18. The invention of claim 15, wherein the switch circuit includes a diode series-coupled to a NMOSFET.

19. The invention of claim 15, wherein at least one of the at least one switch circuit includes a diode, NMOSFET, and PMOSFET coupled in series.

20. The invention of claim 15, wherein the switch circuit includes a capacitor series-coupled to a NMOSFET.

21. The invention of claim 15, wherein the switch circuit includes a capacitor, NMOSFET, and PMOSFET coupled in series.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified schematic circuit of a common prior art series-shunt RF switch circuit configuration.

(2) FIG. 2 is a schematic circuit of a prior art RF switch circuit using FET stacks.

(3) FIG. 3 is a schematic circuit of an RF switch circuit using a stack of “positive logic” FETs, where the stack has zero-V.sub.GS end-cap FETs with selectable gate connections.

(4) FIG. 4A is a schematic circuit of a first embodiment of a switch circuit Sw that may be used in the RF switch circuit of FIG. 3.

(5) FIG. 4B is a schematic circuit of a second embodiment of a switch circuit Sw that may be used in the RF switch circuit of FIG. 3.

(6) FIG. 4C is a schematic circuit of a third embodiment of a switch circuit Sw that may be used in the RF switch circuit of FIG. 3.

(7) FIG. 4D is a schematic circuit of a fourth embodiment of a switch circuit Sw that may be used in the RF switch circuit of FIG. 3.

(8) FIG. 4E is a schematic circuit of a fifth embodiment of a switch circuit Sw that may be used in the RF switch circuit of FIG. 3.

(9) FIG. 4F is a schematic circuit of a sixth embodiment of a switch circuit that may be used in the RF switch circuit of FIG. 3.

(10) FIG. 4G is a schematic circuit of a seventh embodiment of a switch circuit that may be used in the RF switch circuit of FIG. 3.

(11) Like reference numbers and designations in the various drawings indicate like elements unless the context suggest otherwise.

DETAILED DESCRIPTION

(12) The invention encompasses an improved FET-based RF switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors.

(13) FIG. 3 is a schematic circuit of an RF switch circuit 300 using a stack of “positive logic” FETs, where the stack has zero-V.sub.GS end-cap FETs with selectable gate connections. More specifically, the RF switch circuit 300 includes a stack of one or more series-coupled positive-logic FETs M1-Mx (i.e., zero-Vt, low-Vt, or high-Vt FETs of a type that require a negative V.sub.GS to turn OFF but are configured so as to not require a negative voltage), series-coupled on at least one end to an “end-cap” FET M.sub.0, where “M.sub.0” designates a FET of a high-Vt type that turns OFF when the V.sub.GS of such FET is essentially zero volts. The end-cap M.sub.0 FETs selectably provide either a capacitive DC blocking function or a resistive signal path. Some embodiments may comprise a stack of only M.sub.0 FETs, or a mix of positive-logic FETs and M.sub.0 FETs, so long as at least one end-cap FET is an M.sub.0 FET. Optional end-cap capacitors (not shown) in parallel with the end-cap M.sub.0 FETs may be included to prevent early breakdown of corresponding end-cap M.sub.0 FETs.

(14) In the illustrated embodiment, each positive-logic FET M1-Mx includes a dedicated gate resistor Rg coupled between the corresponding FET gate and a non-negative gate bias voltage Vgate. In addition, the source and drain of each positive-logic FET M1-Mx is coupled to a non-negative drain-source (DS) bias voltage Vdrain through a corresponding drain-source resistor Rds (some of the resistors Rds are shared by adjacent FETs). Alternative embodiments may use other bias networks, such as taught in U.S. patent application Ser. No. 15/939,132 referenced above, including various combinations of series-connected bias resistor ladders (a “rail” configuration) and/or parallel-connected bias resistor ladder (a “rung” configuration) and/or a combination of rail-and-rung bias resistor ladders.

(15) While the RF switch circuit 300 of FIG. 3 is similar in many respects to the RF switch circuit 200 of FIG. 2, an important difference is that the terminal capacitors C.sub.S, C.sub.D coupled between an adjacent RF terminal RF1, RF2 and the gate of a respective terminal FET 202, 204 are replaced with a switch circuit Sw 302 (note that the control line to each switch Sw 302 is omitted in FIG. 3, but shown in FIGS. 4A-4G).

(16) The function of the switch circuits Sw 302 is to reduce the voltage swing across the terminal M.sub.0 FETs 202, 204 to make sure they do not turn ON at higher RF power levels when the RF switch circuit 200 is in an OFF state, yet allow normal function of the terminal M.sub.0 FETs 202, 204 when the RF switch circuit 200 is in an ON state. For example, when the RF switch circuit 200 is in an OFF state, the switch circuits Sw 302 are set to an essentially CLOSED (conductive) state such that the gate voltage for the terminal M.sub.0 FET 202, 204 to which power is applied follows the voltage applied to the source of that terminal M.sub.0 FET. Conversely, when the RF switch circuit 200 is in an ON state, the switch circuits Sw 302 are set to an essentially OPEN (blocking) state such that the gate voltage for the terminal M.sub.0 FET to which power is applied is set only by Vgate, and not by any component of DC or RF applied to node.

(17) Described below are a number of circuits for implementing the switch circuits Sw 302, which need not be identical. However, it should be understood that other circuits may be used to implement the switch circuits Sw 302 without departing from the teachings of this disclosure.

(18) Embodiments of Switch Circuit Sw

(19) FIG. 4A is a schematic circuit of a first embodiment of a switch circuit Sw 302a that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302a includes a switch 402 coupled to a control signal Ctrl1. The switch 402 would be coupled between a terminal RFx (e.g., RF1 or RF2) and the gate of a terminal M.sub.0 FET 202, 204.

(20) The switch 402 may be implemented in any suitable technology compatible with fabrication of the RF switch circuit 300, including (but not limited to) FET, MOSFET, micro-electro-mechanical systems (MEMS) switches, bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.

(21) In operation, the switch 402 is set by the control signal Ctrl1 to an essentially CLOSED state when the RF switch circuit 200 is in an OFF state, and to an essentially OPEN state when the RF switch circuit 200 is in an ON state. In general, the ON or OFF state of the control signal Ctrl1 is opposite the state (i.e., OFF or ON) of the RF switch circuit 300 as set by Vgate (see FIG. 3). However, in some embodiments, there may be brief periods of time where the control signal Ctrl1 and the RF switch circuit 300 are in the same state.

(22) FIG. 4B is a schematic circuit of a second embodiment of a switch circuit Sw 302b that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302b includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R to a control signal Ctrl1. The NMOSFET M.sub.N would be coupled between a terminal RFx (e.g., RF1 or RF2) and the gate of a terminal M.sub.0 FET 202, 204 (keeping in mind that the source and drain terminals of the NMOSFET M.sub.N are generally interchangeable).

(23) In essence, switch circuit Sw 302b is an NMOSFET implementation of the switch 402 of FIG. 4A. In operation, the NMOSFET M.sub.N is set by the control signal Ctrl1 to an essentially CLOSED state when the RF switch circuit 200 is in an OFF state, and to an essentially OPEN state when the RF switch circuit 200 is in an ON state. In general, the ON or OFF state of the control signal Ctrl1 is opposite the state (i.e., OFF or ON) of the RF switch circuit 300 as set by Vgate. However, again, in some embodiments there may be brief periods of time where the control signal Ctrl1 and the RF switch circuit 300 are in the same state.

(24) If the gate-drain voltage difference for the NMOSFET M.sub.N becomes too great due to high RF power applied to the RFx terminal of switch circuit Sw 302b in FIG. 4B, the NMOSFET M.sub.N may itself be forced to turn ON. Accordingly, for applications in which such levels of high RF power may be encountered, the switch function of the NMOSFET M.sub.N of FIG. 4B can be enhanced so as to withstand a higher voltage.

(25) For example, FIG. 4C is a schematic circuit of a third embodiment of a switch circuit Sw 302c that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302c includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R1 to a control signal Ctrl1, and a series-connected PMOSFET M.sub.P having its gate coupled through a gate resistor R2 to a control signal Ctrl2. The NMOSFET M.sub.N and the PMOSFET M.sub.P would be coupled between a terminal RFx (e.g., RF1 or RF2) and the gate of a terminal M.sub.0 FET 202, 204 (note the order of the NMOSFET M.sub.N and the PMOSFET M.sub.P may be reversed from the illustrated example).

(26) In operation, the NMOSFET M.sub.N and the PMOSFET M.sub.P are biased by Ctrl1 and Ctrl2 such that, when the NMOSFET M.sub.N is set to OFF, then the PMOSFET M.sub.P is set to OFF, and vice versa. Thus, the NMOSFET M.sub.N and the PMOSFET M.sub.P normally switch between ON and OFF states in unison. However, if the gate-drain voltage difference for the NMOSFET M.sub.N becomes too great due to high RF power applied to the RFx terminal, thus forcing the NMOSFET M.sub.N to an ON state, that same gate-drain voltage difference will force the PMOSFET M.sub.P to an even “harder” OFF state, due to the complementary switching behavior of NMOS and PMOS FETs.

(27) It should be noted that a switch comprising a series-connected NMOSFET M.sub.N and PMOSFET M.sub.P (or a stack of such switches) may be quite useful in other applications in which an NMOSFET M.sub.N (or a stack of such transistors) alone may be forced into an ON (conducting) state by a gate-drain voltage difference.

(28) It has been found that it may be useful to include a diode as part of a switch circuit Sw 302. For example, FIG. 4D is a schematic circuit of a fourth embodiment of a switch circuit Sw 302d that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302d includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R to a control signal Ctrl1. The NMOSFET M.sub.N is shown as coupled between a terminal RFx (e.g., RF1 or RF2) through a diode D, and to the gate of a terminal M.sub.0 FET 202, 204. However, the diode D may be positioned on the other side of NMOSFET M.sub.N. The diode D may be implemented in known fashion as a diode-connected MOSFET, in which the gate and drain of a MOSFET are directly connected.

(29) When the RF switch circuit 300 is OFF, when the voltage (V.sub.S) at RFx starts to drop below the voltage (V.sub.G) at the gate of the M.sub.0 FET during the negative cycle of an applied RF signal, the diode D turns ON (is unidirectionally conductive), essentially making the voltage at the gate of the M.sub.0 FET follow the voltage at RFx. Conversely, when V.sub.S starts to rise above V.sub.G during the positive cycle of an applied RF signal, the diode D essentially turns OFF (is unidirectionally blocking), essentially preventing the voltage V.sub.S at RFx from being applied to the gate of the M.sub.0 FET, thereby preventing the terminal M.sub.0 FETs 202, 204 from being forced ON.

(30) It should be noted that if the diode D was connected directly between a terminal RFx (e.g., RF1 or RF2) and the gate of a terminal M.sub.0 FET 202, 204, then when the RF switch circuit 300 is ON, the diode D would turn ON when the gate of the associated terminal M.sub.0 FET 202, 204 is biased at a sufficiently high level (e.g., 1.8V). The ON state of the diode D would prevent the associated terminal M.sub.0 FET 202, 204 from turning ON state. Accordingly, an NMOSFET M.sub.N having its gate coupled through a gate resistor R1 to a control signal Ctrl1 may be interposed between the diode D and the gate of the associated terminal M.sub.0 FET 202, 204. The NMOSFET M.sub.N functions as a switch as in the switch circuit Sw 302b of FIG. 4B so as to disconnect the diode D from the gate of the associated terminal M.sub.0 FET 202, 204 when the RF switch circuit 300 is ON. Thus, the NMOSFET M.sub.N is OFF (blocking) when the RF switch circuit 300 is ON, and the NMOSFET M.sub.N is ON (conducting) when the RF switch circuit 300 is OFF.

(31) The switch circuit Sw 302d of FIG. 4D works well in applications where the OFF power applied to the RF switch circuit 300 may be high, but the ON power is low. However, in applications where the ON power applied to the RF switch circuit 300 may be high, the NMOSFET M.sub.N may be forced ON when it is supposed to be OFF. Accordingly, for applications in which such levels of high RF power may be encountered, the switch function of the NMOSFET M.sub.N of FIG. 4D can be enhanced so as to withstand a higher voltage.

(32) For example, FIG. 4E is a schematic circuit of a fifth embodiment of a switch circuit Sw 302e that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302e includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R to a control signal Ctrl1. The NMOSFET M.sub.N is shown as coupled to a terminal RFx (e.g., RF1 or RF2) through a diode D. As with the switch circuit Sw 302c of FIG. 4C, a PMOSFET M.sub.P having its gate coupled through a gate resistor R2 to a control signal Ctrl2 is series-connected to the NMOSFET M.sub.N and to the gate of a terminal M.sub.0 FET 202, 204. However, the diode D may be positioned on either side of either the NMOSFET M.sub.N or the PMOSFET M.sub.P, and the order of the NMOSFET M.sub.N and the PMOSFET M.sub.P may be reversed from the illustrated example. Stated another way, the diode D, the NMOSFET M.sub.N, and the PMOSFET M.sub.P may be series-coupled in any order. The diode D may be implemented in known fashion as a diode-connected MOSFET.

(33) As with the switch circuit Sw 302c of FIG. 4C, in operation, the NMOSFET M.sub.N and the PMOSFET M.sub.P are biased by Ctrl and Ctrl2 such that, when the NMOSFET M.sub.N is set to OFF, then the PMOSFET M.sub.P is set to OFF, and vice versa. Thus, the NMOSFET M.sub.N and the PMOSFET M.sub.P normally switch between ON and OFF states in unison. When both the NMOSFET M.sub.N and the PMOSFET M.sub.P are OFF, the diode D is disconnected from the gate of the associated terminal M.sub.0 FET 202, 204 (the desired state when the RF switch circuit 300 is ON). However, if the gate-drain voltage difference for the NMOSFET M.sub.N becomes too great due to high RF power applied to the RFx terminal, thus forcing the NMOSFET M.sub.N to an ON state, that same gate-drain voltage difference will force the PMOSFET M.sub.P to an even “harder” OFF state, thereby keeping the diode D disconnected from the gate of the associated terminal M.sub.0 FET 202, 204.

(34) Further, as with the switch circuit Sw 302d of FIG. 4D, when the RF switch circuit 300 is OFF, then both the NMOSFET M.sub.N and the PMOSFET M.sub.P are set to ON and the diode D is connected to the gate of the associated terminal M.sub.0 FET 202, 204. When the voltage (V.sub.S) at RFx starts to drop below the voltage (V.sub.G) at the gate of the M.sub.0 FET during the negative cycle of an applied RF signal, the diode D turns ON (is unidirectionally conductive), essentially making the voltage at the gate of the M.sub.0 FET follow the voltage at RFx. Conversely, when V.sub.S starts to rise above V.sub.G during the positive cycle of an applied RF signal, the diode D essentially turns OFF (is unidirectionally blocking), essentially preventing the voltage V.sub.S at RFx from being applied to the gate of the M.sub.0 FET, thereby preventing the terminal M.sub.0 FETs 202, 204 from being forced ON.

(35) FIG. 4F is a schematic circuit of a sixth embodiment of a switch circuit Sw 302f that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302f includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R to a control signal Ctrl1. The NMOSFET M.sub.N is shown as coupled between a terminal RFx (e.g., RF1 or RF2) through a capacitor C, and to the gate of a terminal M.sub.0 FET 202, 204. The capacitor C allows the gate of the M0 FET to track the RF signal when the NMOSFET M.sub.N is switched to a CLOSED (conducting) state. The capacitor C may be positioned on either side of the NMOSFET M.sub.N. Operation is otherwise the same as the embodiment of FIG. 4B.

(36) FIG. 4G is a schematic circuit of a seventh embodiment of a switch circuit Sw 302g that may be used in the RF switch circuit 300 of FIG. 3. The illustrated switch circuit Sw 302g includes an NMOSFET M.sub.N having its gate coupled through a gate resistor R1 to a control signal Ctrl1, and a series-connected PMOSFET M.sub.P having its gate coupled through a gate resistor R2 to a control signal Ctrl2. The NMOSFET M.sub.N is shown as coupled to a terminal RFx (e.g., RF1 or RF2) through a capacitor C, and the PMOSFET M.sub.P is shown as coupled to the gate of a terminal M.sub.0 FET 202, 204 (note the order of the NMOSFET M.sub.N and the PMOSFET M.sub.P may be reversed from the illustrated example). The capacitor C allows the gate of the M0 FET to track the RF signal when the NMOSFET M.sub.N and the PMOSFET M.sub.P are both set to a conducting state. The capacitor C, the NMOSFET M.sub.N, and the PMOSFET M.sub.P may be series-coupled in any order. Operation is otherwise the same as the embodiment of FIG. 4C.

(37) Diode Rectifying Effect

(38) A beneficial aspect of including the diode D in the switch circuits Sw 302d, 302e of FIGS. 4D and 4E, respectively, is a rectifying effect when the RF switch circuit 300 is OFF. An RF voltage applied at the RFx terminal will generally have an average DC voltage of zero due to equal positive and negative AC excursions. However, the presence of the diode D will cause the voltage V.sub.GS between RFx and the gate of the M.sub.0 FET to have an average negative DC value, essentially creating a self-generating negative voltage that will drive the associated terminal M.sub.0 FET 202, 204 to a “harder” OFF state. This “harder” OFF state has the effect of reducing signal compression compared to RF switch circuit 200 that utilize terminal capacitors C.sub.S, C.sub.D to prevent forced-ON states for the terminal M.sub.0 FETs 202, 204.

(39) For example, in one simulation of a series-shunt two-port RF switch circuit similar to the circuit of FIG. 1 using an RF switch circuit 200 (i.e., having terminal capacitors C.sub.S, C.sub.D) for the shunt switch 106 (the other switches 102, 104 were modeled as ideal switches), with input power at the TX port being greater than or equal to about 35 dBm, the shunt switch 106 caused compression of about 1 dB at the ANT1 port. While the 1 dB compression point could be adjusted by increasing either the stack height of the shunt switch 106 or the value of the compensation terminal capacitors C.sub.S, C.sub.D, doing so would hurt the small signal performance of the RF switch circuit 200.

(40) In contrast, under similar modeling conditions but using an RF switch circuit 300 (i.e., having a diode-based switch circuit Sw 302d, 302e) for the shunt switch 106 (the other switches 102, 104 were modeled as ideal switches), with input power at the TX port being greater than or equal to about 35 dBm, the shunt switch 106 caused essentially no compression at the ANT1 port.

(41) Benefits

(42) All of the switch circuits Sw 302x described above have the advantage of lower IC area compared to using terminal capacitors C.sub.S, C.sub.D to prevent forced-ON states for the terminal M.sub.0 FETs 202, 204. In addition, the switch circuits Sw 302x that include a diode provide the benefits of rectification described above.

(43) Methods

(44) Another aspect of the invention includes methods for enabling a FET-based RF switch stack to withstand application of a high voltage RF signal without requiring terminal capacitors. For example, one such method applies to a stack of FET switches, at least one FET switch requiring a negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts. The method includes: coupling a switch circuit between the RF signal source and the gate of at least one end-cap FET; closing the switch circuit(s) when the stack of FET switches is in an OFF state; and opening the switch circuit(s) when the stack of FET switches is in an ON state. Examples of such switch circuits are shown in FIGS. 4A-4G.

(45) Fabrication Technologies & Options

(46) The term “MOSFET”, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

(47) As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

(48) Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

(49) Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

(50) Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

CONCLUSION

(51) A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

(52) It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).