Piezoelectric MEMS resonators based on porous silicon technologies

Abstract

A piezoelectric MEMS resonator is provided. The resonator comprises a single crystal silicon microstructure suspended over a buried cavity created in a silicon substrate and a piezoelectric resonance structure located on the microstructure. The resonator is designed and fabricated based on porous silicon related technologies including selective formation and etching of porous silicon in silicon substrate, porous silicon as scarified material for surface micromachining and porous silicon as substrate for single crystal silicon epitaxial growth. All these porous silicon related technologies are compatible with CMOS technologies and can be conducted in a standard CMOS technologies platform.

Claims

1. A piezoelectric MEMS resonator based on porous silicon related technologies, the resonator comprising: a microstructure including: a silicon substrate, a single crystal silicon epitaxial layer, a buried cavity; a single crystal silicon plate and two flexible single crystal silicon beams each made of the single crystal silicon epitaxial layer and suspended over the buried cavity, wherein the single crystal silicon plate is anchored to the silicon substrate through the two flexible single crystal silicon beams; a piezoelectric resonance element including: a bottom electrode, a middle piezoelectric layer, a top drive electrode, a top sense electrode, and a top electrode isolation gap which are all vertically stacked on the single crystal silicon plate; and several electric connecting elements including: two bonding pads connecting to the bottom electrode and two bonding pads connecting to the drive electrode and the sense electrode respectively, wherein the resonator is configured to operate in lateral resonance mode.

2. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the buried cavity is created by selective etching of a porous silicon layer formed in the silicon substrate.

3. The piezoelectric MEMS resonator based on porous silicon related technologies of claim 1, wherein the buried cavity is allowed to have a vertical gap with a common range of 1 to 5 μm and narrow enough to prevent the microstructure from damage when a vertical external force such as a mechanical shock to occur.

4. The piezoelectric MEMS resonator based on porous silicon related technologies of claim 1, wherein the surface of the bottom of the buried cavity is made rough enough by etching of a porous silicon layer so as to prevent the microstructure from sticking to the bottom when the microstructure occasional touches the bottom.

5. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the single crystal silicon layer is grown on the entire surface of the silicon substrate including a surface of a porous silicon layer by chemical vapor deposition (CVD).

6. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the single crystal silicon layer has a specification allowed to be optimized for RF CMOS IC design and fabrication.

7. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the single crystal silicon layer has a vertical thickness with a common range of 1 to 30 μm and allowed to be optimized for RF piezoelectric MEMS resonator design and fabrication.

8. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the bottom electrode, the top drive electrode and the top sense electrode are all made of Cr/Au or Pt/Au.

9. The piezoelectric MEMS resonator is based on porous silicon related technologies of claim 1, wherein the middle piezoelectric layer is made of Pb(Zr,Ti)O.sub.3(PZT)), ZnO or AlN.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure may be better understood with reference to the following figures. Matching reference numerals designate corresponding parts throughout the figures, which are not necessarily drawn to scale.

(2) FIG. 1 is a perspective view of a piezoelectric MEMS resonator based on porous silicon related technologies which is provided by the present invention.

(3) FIGS. 2-9 illustrate the method for fabricating a piezoelectric MEMS resonator based on porous silicon related technologies which is provided by the present invention.

(4) FIG. 2 illustrates a first mask being used to form a porous silicon layer in a silicon substrate.

(5) FIG. 3 illustrates a single crystal silicon layer is formed on the porous silicon layer through chemical vapor deposition (CVD).

(6) FIG. 4 illustrates a silicon dioxide layer is formed on the surface of the silicon substrate including the silicon epitaxial layer.

(7) FIG. 5 illustrates a pattern of a bottom electrode layer that is formed on the surface of the silicon dioxide layer using a second mask.

(8) FIG. 6 illustrates a pattern of a piezoelectric layer that is formed on the surface of the bottom electrode layer using a third mask.

(9) FIG. 7 illustrates a pattern of a top electrode layer that is formed on the surface of the piezoelectric layer using a forth mask.

(10) FIG. 8 illustrates a trench is formed to divide the silicon substrate into a central region and a surrounding region so that the central region is positioned on the top of the porous silicon layer.

(11) FIG. 9 illustrates a buried cavity that is formed by selective etching of the porous silicon layer in the process of finishing the fabrication process.

DETAILED DESCRIPTION

(12) Radio frequency (RF) communication circuits like reference oscillators, filters, and mixers based on such micro-electro-mechanical system (MEMS) resonators can be utilized for meeting the increasing count of RF components likely to be demanded by the next-generation multi-band/multi-mode wireless devices. MEMS based on-chip resonators have shown significant potential for sensing and high frequency signal processing applications. This is due to their excellent features like small size, large frequency-quality factor product, low power consumption, low cost batch fabrication, and integrability with complementary Metal-Oxide Semiconductor integrated circuit (CMOS IC) technology.

(13) The utilization of the conventional CMOS IC technology as a platform for design and fabrication of the fast-growing RF MEMS devices has led to development of porous silicon related MEMS technologies. The porous silicon related MEMS technologies include selective formation and etching of porous silicon in silicon substrate, porous silicon as scarified material for surface micromachining and porous silicon as substrate for single crystal silicon epitaxial growth. The present invention provides a piezoelectric MEMS resonator designed and fabricated based on the porous silicon related technologies. Since the porous silicon related technologies are compatible with CMOS technologies the piezoelectric MEMS resonator can be realized using a standard CMOS technologies platform.

(14) FIG. 1 shows a piezoelectric MEMS resonator based on porous silicon related technologies which is provided by the present invention. The MEMS resonator comprises: a microstructure including: a silicon substrate 101, a single crystal silicon epitaxial layer 103, a buried cavity 102 created by selective etching of a porous silicon layer formed in the silicon substrate 101, a single crystal silicon plate made of the single crystal epitaxial layer 103 and anchored to the silicon substrate 101 through two flexible single crystal silicon beams 110 made of the single crystal silicon epitaxial layer 102, which are all suspended over the buried cavity 102; a piezoelectric resonance element including: a silicon dioxide layer 104, a bottom electrode 105, a middle piezoelectric layer 106, a top drive electrode 107, a top sense electrode 108, and a top electrode isolation gap 109, which are all vertically stacked on the single crystal silicon plate; and several electrical connecting elements including: bonding pad 112 and 113 connecting to top drive electrode 107 and top sense electrode 108 respectively, and bonding pad 114 and 115 both connecting to the bottom electrode 105, wherein the MEMS resonator is configured to operate in lateral resonance mode.

(15) The piezoelectric MEMS resonator based on porous silicon related technologies can be operate in one-port mode resonator or two-port mode resonator which depends on the drive electrode and the sense electrode shared or separated. As shown in FIG. 1, the present resonator is configured as a two-port mode, since there are two pairs of electrodes: the drive electrode 208a and the sense electrode 208b are separately arranged on the top of the piezoelectric layer 209. In operation of the resonator the signal applied to the drive electrode is converted to an acoustic vibration in the device and the sense electrode converts the vibration back to an electrical signal. The vibration is an elastic-wave motion transverse to the applied electric field. The resonance frequency of the excited lateral mode is mostly dependent on the in-plane dimensions of the device structure.

(16) The advantage of utilizing the lateral mode is that since the lateral dimension of the resonator is defined lithographically, the operation frequency of the devices fabricated on a single substrate can span a wide range (from few MHz to a few GHz). Whereas, thickness mode resonators (one-port mode) fabricated on a substrate, are bound to have almost the same center frequency since the device thickness is the same all over the substrate. On the other hand, the piezoelectric materials used to make the piezoelectric MEMS resonators are sputtered polycrystalline materials which are mostly transversely isotropic. In other words, the z axis (orthogonal to the plane) has an infinite order of symmetry and it has the largest piezoelectric coefficient (d33). Therefore, compared to lateral mode resonators where (d31) is utilized to excite the resonance mode the electromechanical coupling is larger for thickness mode resonators. Consequently, the motional impedance of a thickness-mode resonator is lower considering the same-size actuation (electrode) area.

(17) It has been shown that porous silicon is emerging in micromachining technology as an excellent material for use as a sacrificial layer. This is largely due to the ease to obtain by electrochemical dissolution of silicon wafers in aqueous HF solutions. The rate of pore formation is heavily dependent upon the doping type and concentration of the silicon, allowing patterned porous silicon formation through selective doping of the substrate. Silicon that has been made porous can be quickly and easily removed in a dilute hydroxide solution, as low as 1%. Porous silicon technology offers the unique ability to fabricate free-standing structures in single-crystal silicon with separation distances from the substrate ranging from a few microns to over one hundred microns.

(18) It has been reported that silicon grown by the epitaxial process on porous silicon is one of the powerful technologies for growth of low-cost high-efficiency silicon for photovoltaic applications. It has been shown that excellent minority carrier lifetimes and diffusion lengths of several hundred micrometers can be achieved on a thin epitaxial silicon epitaxial layer which is commonly used for CMOS IC fabrication.

(19) As shown in FIG. 1, the buried cavity 102 is created by selective etching of a porous silicon layer formed in the silicon substrate 101. The vertical gap of the buried cavity 102 can be adjusted according to the resonator design. Since the suspending structure of the resonator is supported by the two flexible single crystal silicon beams 110 it may bend down to the cavity 102 when an external force such as a mechanical shock occurs. In order to prevent the suspending structure from breaking, the vertical gap of the buried cavity 102 is made in a range of 1 to 5 μm and less than the maximum displacement of the suspending structure. If not the suspending structure will be broken.

(20) Stiction or adhesion of the suspending structure to the bottom of the buried cavity 102 is a major failure mechanism in the MEMS resonators. It is interesting to know that the surface of the bottom of the buried cavity 102 is made to be inherently rough so as to prevent the suspending structure from sticking to the bottom when the suspending structure occasionally touches the bottom. The inherent rough of the bottom of the buried cavity 102 is produced by selective etching of the porous silicon layer.

(21) The silicon epitaxial layer 102 is grown on the porous silicon layer by chemical vapor deposition. The porous silicon layer is made to have a double layer structure with a top layer of ˜20% porosity and a bottom layer of 50% porosity. The thickness of the silicon epitaxial layer 102 is allowed to be optimized for CMOS IC fabrication and also can be adjusted in the range of 3 to 30 μm depending on the resonator design.

(22) The bottom electrode 105, the top drove electrode 107 and the top sense electrode 108 are made of Cr/Au or Pt/Au double metal layers. The Cr/Au or Pt/Au pattern is made by sputtering and then patterned by lift-off process. In a lift-off process, a pattern is exposed into photoresist and a metal layer is deposited over the entire area, then the photoresist is washed away to leave behind the metal layer only in the patterned area.

(23) The piezoelectric resonance layer 106 is made of Pb(Zr,Ti)O.sub.3 (PZT)), ZnO or AlN thin film which is deposited by sputtering and patterned by lift-off process.

(24) PZT thin film has been broadly applied in various kinds of MEMS devices, such as ferroelectric random access memory, digital switch, vibration energy harvesting, and piezoelectric proton exchange membrane fuel cells. PZT thin film could be utilized in these applications due to the fact that it possesses low leakage current density, large electromechanical coupling coefficient, and excellent dielectric properties.

(25) Piezoelectric ZnO films are widely used for the generation and detection of acoustic waves in non-piezoelectric substrates. In recent years these films have been combined with standard bipolar or CMOS IC processes to realize acoustic wave devices integrated with electronic circuits.

(26) The non-ferroelectric polar wurtzite aluminium nitride (AlN) material has been shown to have potential for various sensor applications both utilizing the piezoelectric effect directly for pressure sensors or indirectly for acoustic sensing of various physical, chemical and biochemical sensor applications. Sputter deposited AlN thin films have played a central role for successful development of the thin film electro-acoustic technology. The development has been primarily driven by one device—the thin film bulk acoustic resonator with its primary use for high frequency filter applications for the telecom industry. AlN has been the dominating choice for commercial application due to compatibility with the integrated circuit technology, low acoustic and dielectric losses and high acoustic velocity in combination with comparably high electromechanical coupling.

(27) It has been revealed that single crystal silicon is a preferred material for fabricating MEMS resonators. The advantages of the MEMS resonators have been summarized as: (1) Q values greater than 100,000 are possible, (2) it has an energy density three orders greater than quartz, (3) it has ideal extensional modes of resonance not found in any other materials, and (4) its material properties are stable, well-characterized and repeatable to enable design for manufacturability, and it enables a high-yield fabrication technology. Finally, a piezoelectric transduction scheme is employed in lieu of capacitive transduction for its greater electromechanical coupling. It has been demonstrated that the single crystal silicon substrate together with the piezoelectric film also enables resonator configuration and mode of operation that has superior power handling, a greater quality factor at ultra high frequency frequencies, and exceptional manufacturability.

(28) According to the present invention a method for fabricating a piezoelectric MEMS resonator based on porous silicon related technologies comprises fabrication steps:

(29) Forming a porous silicon layer in a silicon substrate by anodic etching of crystalline silicon in hydrofluoric acid;

(30) Growing a single crystal silicon layer on the entire surface of the silicon substrate including the surface of the porous silicon layer by chemical vapor deposition (CVD);

(31) Depositing a silicon dioxide layer on the entire surface of the silicon epitaxial layer by plasma enhanced chemical vapor deposition (PECVD);

(32) Creating a bottom electrode and two bonding pads on the surface of the silicon dioxide layer by metal sputtering and lift-off process;

(33) Creating a piezoelectric resonance layer on the surface of the bottom electrode by piezoelectric material sputtering and lift-off process;

(34) Creating a top drive electrode, a top sense electrode, a top electrode isolation gap and two bonding pads so that the top drive electrode, the top sense electrode, and the top electrode isolation gap located on the surface of the piezoelectric resonance element and the bonding pads on the surface of the silicon dioxide layer by metal sputtering and lift-off process;

(35) Creating a dividing trench by plasma etching so as to separate the silicon substrate into two regions: a central region including the top electrode, the top sense electrode and the top electrode isolation gap and a surrounding region including the bonding pads connecting to the bottom electrode and the bonding pads connecting to the top drive electrode and the top sense electrode, wherein the trench is separated by two symmetrical supporting beams which connect the two separated regions, the upper of the trench is created by previews steps and lower of the trench is created by plasma etching of the silicon dioxide layer and the single crystal silicon epitaxial layer so to reveal the buried porous silicon layer; and

(36) Removing the porous silicon layer by selective etching of the porous silicon layer so as to result in a buried cavity, a central region, and two supporting beams which all are suspended over the buried cavity.

(37) FIGS. 2-9 illustrate the method for fabricating a piezoelectric MEMS resonator based on porous silicon related technologies according to the present invention.

(38) Reference to FIG. 2, a porous silicon layer 202 is formed in a silicon substrate 201. The silicon substrate 201 is preferably a (100) p-type silicon substrate with a resistivity ranging in 0.01 to 0.02 Ω-cm. Before porous silicon formation an ohmic contact is created on the back surface of the silicon substrate 201 by heavily p-type doping. Then a 100 nm thick silicon carbide layer is deposited on the front surface of the silicon substrate 201 by PECVD and a silicon carbide mask is created by a photolithographic process.

(39) Afterwards, a double (two-layer structure) porous silicon layer 202 is formed in the silicon substrate 201 by anodization (note: porous silicon is a sponge-like structure of single crystalline silicon). The anodization is carried out in a mixture of 40% HF acid and ethanol (1:1 in volume ratio) as the electrolyte. In order to obtain porosities of ˜20% for the top layer and ˜50% for the bottom layer of the double porous silicon layer, the anodic current densities are selected to be 5 and 20 mA/cm.sup.2 for the low- and high-porosity layers, respectively. The corresponding thicknesses of the layers are set to be 0.5 μm and 0.5 to 4.5 μm, respectively. The top shape of the porous silicon layer is preferably configured to be square with a side length of 300 to 800 μm.

(40) Reference to FIG. 3, a single crystal silicon epitaxial layer 203 is grown on the entire surface of the silicon substrate 201 including the surface of the porous silicon layer 202 by chemical vapor deposition (CVD). To do this the porous silicon layer 202 is slightly oxidized in O.sub.2 ambient at 400° C. for 1 h. This is for passivating the pore walls of the porous silicon layer 202 for suppressing structural change in the pore feature size during the following thermal processes. Then the silicon carbide layer on the surface of the silicon substrate is removed by dry etching. In the CVD process, the porous silicon layer 202 is annealed in an epitaxial reactor at ˜1130° C. in 1 atm of dry hydrogen ambient for 5 to 10 min. As a result, the pores of the top layer of the porous silicon layer 202 are closed so as to form a densified silicon layer as a seed layer for the epitaxial growth. Then an n-type single silicon epitaxial layer 203 is grown so as to have a resistivity of ˜7.5 Ω-cm and a thickness of 1 to 30 μm according to the device design. The specification of the single silicon epitaxial layer 203 is preferably to be set by a designed resonator with a CMOS IC in a single crystal silicon substrate.

(41) Reference to FIG. 4, a silicon dioxide layer 204 is deposited on the entire surface of the silicon substrate 201 including the surface of the single silicon epitaxial layer 203 by plasma enhanced chemical vapor deposition (PECVD).

(42) Reference to FIG. 5, a bottom electrode layer 205 and two bonding pads 206a and 206b are created on the surface of the silicon dioxide layer 204. The bottom electrode layer 206 and two bonding pads 206a and 206b are made of a Cr/Au or Pt/Au double metal layer. Cr or Pt as adhesion layer with thickness 90 nm and Au as conduction layer with 500 to 1000 nm are deposited through sputtering. The pattern of the bottom electrode is created by the lift-off process.

(43) Patterning of multilayer containing such as Pt, Au, Cr metals or such as PZT, ZnO, AlN piezoelectric materials, will be performed using lift-off process. For these materials, dry etching techniques are not readily available. In the lift-off process, an inverse pattern is first formed in a sacrificial layer deposited on a substrate, using lithographic techniques. Next, the thin film is deposited over the entire layer and in the openings of the pattern. Those portions of the thin film which are deposited on the sacrificial layer are removed (lifted-off) when the substrate is immersed in a suitable solvent, leaving behind the desired thin film pattern.

(44) Reference to FIG. 6, a pattern of a piezoelectric layer including a resonance layer 207, two edge electrode insulation layer 208a and 208b, is created on the surface of the bottom electrode layer 206. The pattern is made of a PZT, ZnO, or AlN layer and patterned by the lift-off process.

(45) A 150 to 600 nm thick PZT layer is deposited from a PZT ceramic target through RF sputtering. In order to eliminate the formation of the pyrochlore phase in the PZT layer, the annealing treatment is implemented in the air with a rapid thermal process at 500 to 700° C. Then the PZT layer is cooled down to room temperature naturally.

(46) As an alternative, a ZnO layer with a thickness of 300 to 700 nm is deposited by RF magnetron sputtering, using a high-purity (99.999%) zinc oxide ceramic target. Argon and oxygen are used as sputtering gases, The percentage of oxygen flow in the process gas varied over the range 7.3-12.5% (deposition time:90 min), and an additional layer without oxygen in the gas composition was fabricated (using 100% argon, with 60 min of deposition time).

(47) As another alternative, an AlN layer is deposited on silicon substrates using pure Al targets reactively sputtered in nitrogen and argon environments with the application of negative DC voltage on the cathode. A Ti under-layer (seed layer) is used as the adhesion layer for the AlN layer and also a seed layer for the texture growth of the functional AlN layer. With the processing parameter: 250 W, 3 mT, pure Nitrogen, 3 h and ˜50V bias, a 500-700 nm thick AlN layer can be prepared. The layer undergoes a post-annealing treatment of 600° C. for two hours to improve its electrical properties.

(48) Reference to FIG. 7, a top electrode pattern includes a top drive electrode 209a, a top sense electrode 209b, and a top electrode isolation gap 210, which all is arranged on the surface of the piezoelectric resonance layer 207, and two bonding pads 211a and 211b both arranged on the surface of the silicon dioxide layer 204. The bottom electrode pattern is made of a Cr/Au or Pt/Au double metal layer. Cr or Pt as adhesion layer with thickness 90 nm and Au conduction layer with a thickness of 500 to 100 nm are deposited through sputtering. The top electrode pattern is created by the lift-off process, and a top electrode isolation gap 210 is also formed.

(49) Reference to FIG. 8, a trench including a part 212a and a part 212b is created by plasma etching so as to divide the silicon substrate 201 into two regions: a central region including the top drive electrode 209a, the top sense electrode 209b and the top electrode isolation gap 210 and a surrounding region including the bonding pads 206a and 206b connecting to the bottom electrode and the bonding pads 211a and 211b connecting to the top drive electrode 209a and the top sense electrode 209b respectively. The trench is separated by two symmetrical supporting beams 110 as shown in FIG. 1, which connect the two separated regions. The upper of the trench is created by previous fabrication steps and the lower of the trench is created through etching of the silicon dioxide layer 204 and the single crystal silicon epitaxial layer 203 so as to reveal the buried porous silicon layer 202.

(50) Reference to FIG. 9, a buried cavity 213 is created by selective etching of the porous silicon layer 202 through the trench part 212a and trench part 212b and then a suspended resonance structure is resulted which includes the bottom electrode 205, the piezoelectric resonance layer 207, the top drive electrode 209a, the top sense electrode 209b and the two supporting beams 110 as shown in FIG. 1.

(51) To avoid any damage of the Al interconnection during a CMOS compatible process, a tetramethylammonium hydroxide (TMAH) solution with silicon powder and (NH.sub.4).sub.2S.sub.2O.sub.8 solution is used to remove the porous silicon layer 202.

(52) If the piezoelectric MEMS resonator is not integrated with a CMOS IC, it is preferred to conduct a post MEMS process for releasing the suspended structure. In this process the porous silicon layer is removed by a diluted KOH solution so as to finish the fabrication flow for the piezoelectric MEMS resonator.

(53) Thus, a piezoelectric MEMS resonator based on porous silicon related technologies has been disclosed. It is to be understood that the above-described embodiments are merely illustrative of some of the many specific embodiments that represent applications of the principles discussed above. Clearly, numerous and other arrangements can be readily devised by those skilled in the art without departing from the scope of the invention.