SUPER-LATTICE CASTELLATED FIELD EFFECT TRANSISTOR (SLCFET) SWITCH SYSTEM

Abstract

One example includes a super-lattice castellated field effect transistor (SLCFET) system. The system includes a plurality of SLCFETs arranged in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RF) signal between the first port and the second port in response to activation of the SLCFETs. The system also includes a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port to which an activation signal is provided to concurrently activate the SLCFETs. The system further includes a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when activated.

Claims

1. A super-lattice castellated field effect transistor (SLCFET) system comprising: a plurality of SLCFETs arranged in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RF) signal between the first port and the second port in response to activation of the SLCFETs; a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port to which an activation signal is provided to concurrently activate the SLCFETs; and a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when activated.

2. The system of claim 1, wherein the balancing resistors are configured to provide a current path for a balancing current associated with the RF signal, wherein the balancing current is approximately equal to a gate current through each of the gate resistors when the SLCFETs are activated.

3. The system of claim 2, further comprising a DC-blocking capacitor coupled to one of the balancing resistors, wherein the DC-blocking capacitor is configured to filter DC current in the current path.

4. The system of claim 3, wherein the balancing resistors comprise a first balancing resistor and a plurality of remaining balancing resistors, wherein one of the SLCFETs is coupled to the first port, wherein the first balancing resistor is arranged in series with the DC-blocking resistor between a gate terminal and a drain terminal of the respective one of the SLCFETs.

5. The system of claim 4, wherein each of the remaining balancing resistors are arranged as interconnecting the gate terminals of a pair of the SLCFETs.

6. The system of claim 2, further comprising a plurality of DC-blocking capacitors, wherein each of the DC-blocking capacitors is arranged in series with a respective one of the balancing resistors between a gate terminal and a drain terminal of a respective one of the SLCFETs, wherein each of the DC-blocking capacitors is configured to filter DC current in the current path associated with the respective one of the SLCFETs.

7. The system of claim 1, further comprising: a plurality of feedforward capacitors arranged in parallel with each of the respective plurality of SLCFETs; and a plurality of shunt resistors arranged in parallel with each of the respective plurality of SLCFETs.

8. A complementary switch system comprising the SLCFET system of claim 1, wherein the SLCFET system is a first SLCFET system coupled to a complement node at the first port and a low-voltage terminal at the second port, the complementary switch system further comprising: an input/output (I/O) port impedance matching network arranged between an I/O port and the complement node; a second SLCFET system coupled between the complement node at the first port of the second SLCFET system and a common node at the second port of the SLCFET system, wherein the SLCFETs of the second SLCFET system are activated via a complement of the activation signal; and an I/O terminal impedance matching network arranged between an I/O terminal and the common node.

9. An RF switch system comprising the complementary switch system of claim 8, wherein the RF switch system comprises a plurality of complementary switch systems, wherein the I/O port impedance matching network of each of the complementary switch systems is arranged between the I/O port and the complement node of the respective one of the complementary switch systems, wherein the second SLCFET system of each of the complementary switch systems is coupled between the complement node of the respective one of the complementary switch systems and the common node.

10. An RF antenna system comprising the RF switch system of claim 9, further comprising: an antenna coupled to the I/O terminal, the antenna being configured to transmit a transmit RF signal during a transmit mode and to receive a received RF signal during a receive mode; at least one low-noise amplifier coupled to the I/O port of at least one of the complementary switch systems to amplify the received RF signal propagating through the second SLCFET system of the at least one of the complementary switch systems during the receive mode, the transmitted RF signal being shunted through the first SLCFET system of the at least one of the complementary switch systems during the transmit mode; and at least one high-power amplifier coupled to the I/O port of at least one other of the complementary switch systems to amplify the transmitted RF signal propagating through the second SLCFET system of the at least one other of the complementary switch systems during the transmit mode, the received RF signal being shunted through the first SLCFET system of the at least one of the complementary switch systems during the receive mode.

11. A method for fabricating a super-lattice castellated field effect transistor (SLCFET), the method comprising: forming a plurality of SLCFETs in a series stack between a first port and a second port; forming a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port; and forming a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs.

12. The method of claim 11, further comprising forming a DC-blocking capacitor coupled to the first port, wherein forming the balancing resistors comprises: forming a first balancing resistor in series with the DC-blocking capacitor between the first port and the gate terminal of a first one of the SLCFETs; and forming the remaining balancing resistors interconnecting gate terminals of each of consecutive pairs of the SLCFETs.

13. The method of claim 11, wherein forming the balancing resistors comprises forming a plurality of DC-blocking capacitors in a series connection with a respective one of the balancing resistors between a gate terminal and a drain terminal of each of the SLCFETs.

14. The method of claim 11, further comprising: forming a plurality of feedforward capacitors in parallel with each of the respective plurality of SLCFETs; and forming a plurality of shunt resistors in parallel with each of the respective plurality of SLCFETs.

15. The method of claim 11, wherein forming the plurality of SLCFETs comprises forming a source terminal of a first one of the SLCFETs and forming a drain terminal of a second one of the SLCFETs as integral with respect to a metal material for the respective source and drain terminals.

16. A complement switch system comprising: an input/output (I/O) port impedance matching network arranged between an I/O port and a complement node; an I/O terminal impedance matching network arranged between an I/O terminal and the common node; a first super-lattice castellated field effect transistor (SLCFET) system comprising: a first plurality of SLCFETs arranged in a first series stack between the complement node and a low voltage rail to provide a propagation path of a radio frequency (RF) signal between the complement node and the low-voltage rail in response to activation of the first SLCFETs; a first plurality of gate resistors interconnecting gate terminals associated with each of the respective first SLCFETs and a first activation port to which an activation signal is provided to concurrently activate the first SLCFETs; and a first plurality of balancing resistors coupled to the gate terminals associated with each of the respective first SLCFETs, the first balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the first SLCFETs when activated; and a second SLCFET system comprising: a second plurality of SLCFETs arranged in a second series stack between the common node and the complement node to provide a propagation path of the RF signal between the common node and the complement node in response to activation of the second SLCFETs; a second plurality of gate resistors interconnecting the gate terminals associated with each of the respective second SLCFETs and a second activation port to which a complement of the activation signal is provided to concurrently activate the second SLCFETs; and a second plurality of balancing resistors coupled to the gate terminals associated with each of the respective second SLCFETs, the second balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the second SLCFETs when activated.

17. The system of claim 16, wherein each of at least one of the first balancing resistors are arranged as interconnecting the gate terminals of a pair of the first SLCFETs, wherein the first SLCFET system further comprises a first DC-blocking capacitor coupled to one of the first balancing resistors to filter DC current in a first current path through the first balancing resistors, wherein each of at least one of the second balancing resistors are arranged as interconnecting the gate terminals of a pair of the second SLCFETs, wherein the second SLCFET system further comprises a second DC-blocking capacitor coupled to one of the second balancing resistors to filter DC current in a second current path through the second balancing resistors.

18. The system of claim 16, wherein the first SLCFET system comprises a plurality of first DC-blocking capacitors, wherein each of the first DC-blocking capacitors is arranged in series with a respective one of the first balancing resistors between a gate terminal and a drain terminal of a respective one of the first SLCFETs, wherein each of the first DC-blocking capacitors is configured to filter DC current in a current path associated with the respective one of the first SLCFETs, wherein the second SLCFET system comprises a plurality of second DC-blocking capacitors, wherein each of the second DC-blocking capacitors is arranged in series with a respective one of the second balancing resistors between a gate terminal and a drain terminal of a respective one of the second SLCFETs, wherein each of the second DC-blocking capacitors is configured to filter DC current in a current path associated with the respective one of the second SLCFETs.

19. An RF switch system comprising the complementary switch system of claim 16, wherein the RF switch system comprises a plurality of complementary switch systems, wherein the I/O port impedance matching network of each of the complementary switch systems is arranged between the I/O port and the complement node of the respective one of the complementary switch systems, wherein the second SLCFET system of each of the complementary switch systems is coupled between the complement node of the respective one of the complementary switch systems and the common node.

20. An RF antenna system comprising the RF switch system of claim 19, further comprising: an antenna coupled to the I/O terminal, the antenna being configured to transmit a transmit RF signal during a transmit mode and to receive a received RF signal during a receive mode; at least one low-noise amplifier coupled to the I/O port of at least one of the complementary switch systems to amplify the received RF signal propagating through the second SLCFET system of the at least one of the complementary switch systems during the receive mode, the transmitted RF signal being shunted through the first SLCFET system of the at least one of the complementary switch systems during the transmit mode; and at least one high-power amplifier coupled to the I/O port of at least one other of the complementary switch systems to amplify the transmitted RF signal propagating through the second SLCFET system of the at least one other of the complementary switch systems during the transmit mode, the received RF signal being shunted through the first SLCFET system of the at least one of the complementary switch systems during the receive mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates an example block diagram of a SLCFET switch system.

[0007] FIG. 2 illustrates an example circuit diagram of a SLCFET switch system.

[0008] FIG. 3 illustrates an example diagram of current flow in a SLCFET switch system.

[0009] FIG. 4 illustrates another example circuit diagram of a SLCFET switch system.

[0010] FIG. 5 illustrates an example of an RF switch system.

[0011] FIG. 6 illustrates an example diagram of an RF antenna system.

[0012] FIG. 7 illustrates an example of a method for fabricating a SLCFET switch system.

DETAILED DESCRIPTION

[0013] The present disclosure relates generally to communication systems, and specifically to a super-lattice castellated field effect transistor (SLCFET) switch system. The SLCFET switch system can be implemented in any of a variety of high-frequency high-power RF communications applications, such as for switching signal paths between transmit and receive in an antenna system. The SLCFET switch system can provide for propagation of an RF signal therethrough in an activated state to provide for low-losses and for mitigating non-linearities of the RF signal. As an example, the SLCFET switch system can be implemented in a complementary switch system that provides a signal path and a shunt path for the RF signal in an RF switching application.

[0014] The SLCFET switch system can include a plurality of SLCFETs that are arranged in a series stack. As an example, the SLCFETs can be any of a variety of SLCFET devices, such as a metal semiconductor field effect transistor (MESFET). As described herein, the terms series and series stack refer to a coupling of the source of one SLCFET to a drain of a next SLCFET in a sequence along the series stack of SLCFETs. Therefore, in response to concurrent activation of the SLCFETs, the channels of the SLCFETs through the drain-to-source connections can provide for a propagation path of an RF signal. As also described herein, the terms activate and activation, as describing a transistor (e.g., the SLCFETs herein), refer to providing sufficient bias (e.g., gate-source voltage) to operate the transistor device in resistive mode. Similarly, the terms deactivate and deactivation, as describing a transistor (e.g., the SLCFETs herein), refer to removing bias to operate the transistor device in cutoff mode. Therefore, the propagation path of the RF signal through the series stack of the SLCFETs can be such that the series stack of the activated SLCFETs can accommodate approximately the full amplitude of the current associated with the RF signal without saturating the SLCFETs.

[0015] The series arrangement of the SLCFETs can be such that the peak voltage of the RF signal can be distributed across each of the SLCFETs (e.g., as VDS). As an example, the SLCFETs can be fabricated in a manner such that the drain and source metals of respective SLCFET devices in the series sequence can be overlapping or integral to mitigate parasitic capacitance. Additionally, the SLCFET switch system can include a plurality of feedforward capacitors and feedforward resistors that are each arranged in parallel with each other and with the drain-source channels of each of the respective SLCFETs. Therefore, the feedforward capacitors and shunt resistors can provide for a substantially balanced voltage swing of the RF signal in a deactivated state, as well, without the high-power RF signal conducting through the channels of the SLCFETs in the series stack.

[0016] In addition, as described herein, the SLCFET switch system can include a plurality of balancing resistors that are configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when the respective SLCFETs are activated. For example, the balancing resistors can provide a current path for a balancing current associated with the RF signal that propagates between from a drain to a gate of each of the SLCFETs. Because a portion of the AC current associated with the RF signal can propagate through a gate resistor associated with each of the SLCFETs, the balancing current can be provided as approximately equal to the gate current through each of the gate resistors when the SLCFETs are activated to compensate for the gate current to balance the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs. Accordingly, the balanced drain-gate voltage and a gate-source voltage associated with each of the SLCFETs can provide for a more linear propagation of the RF signal with minimal losses.

[0017] FIG. 1 illustrates an example block diagram of a SLCFET switch system 100. The SLCFET switch system 100 can be implemented in any of a variety of high-frequency high-power RF communications applications, such as for switching signal paths between transmit and receive in an antenna system.

[0018] The SLCFET switch system 100 includes a plurality of SLCFETs 102 that can be arranged in a series stack, and are thus demonstrated in the example of FIG. 1 as a SLCFET STACK. As an example, the SLCFETs can be any of a variety of SLCFET devices, such as a metal semiconductor field effect transistor (MESFET). Therefore, in response to concurrent activation of the SLCFETs 102, the channels of the SLCFETs 102 through the drain-to-source connections can provide for a propagation path of an input RF signal. The RF signal is demonstrated as being input to the SLCFET switch system 100 as an input RF signal RF.sub.IN and as being output from the SLCFET switch system 100 as an output RF signal RF.sub.OUT, having propagated through the activated SLCFETs 102. Therefore, the propagation path of the RF signal (described hereinafter as the RF signal RF.sub.IN) through the series stack of the SLCFETs 102 can be such that the series stack of the activated SLCFETs 102 can accommodate approximately the full amplitude of the current associated with the RF signal without saturating the SLCFETs 102.

[0019] The series arrangement of the SLCFETs 102 can be such that the peak voltage of the RF signal can be distributed across each of the SLCFETs 102 (e.g., as VDS). As an example, the SLCFETs 102 can be fabricated in a manner such that the drain and source metals of respective SLCFETs 102 in the series sequence can be overlapping or integral to mitigate parasitic capacitance. In the example of FIG. 1, the SLCFET switch system 100 includes a plurality of feedforward capacitors and shunt resistors 104, demonstrated as FEEDFORWARD CAPACITORS/SHUNT RESISTORS) that can each be arranged in parallel with each other and with the drain-source channels of each of the respective SLCFETs 102. Therefore, the feedforward capacitors and shunt resistors 104 can provide for a substantially balanced voltage swing of the RF signal RF.sub.IN in a deactivated state, as well, without the high-power RF signal RF.sub.IN conducting through the channels of the SLCFETs 102 in the series stack.

[0020] As an example, the gate terminals of each of the SLCFETs 102 can include a gate resistor that can facilitate a sufficient maximum control voltage (e.g., Vas) for activation of the SLCFETs 102. However, in response to conduction of AC current associated with the RF signal RF.sub.IN through the SLCFETs 102, a portion of the AC current is conducted through the gate resistors. As a result, absent any compensation current, the current flow through the gate resistor can unbalance the current that flows between the drain and the gate of the SLCFETs 102 and that flows between the gate and the source of the SLCFETs 102. Such current imbalance can thus result in an imbalance between the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs 102. The RF signal RF.sub.IN could thus exhibit non-linearities and/or losses based on the imbalanced drain-gate and gate-source voltages.

[0021] To balance the AC currents, and thus the drain-gate and gate-source voltages, of the SLCFETs 102, the SLCFET switch system 100 can include a plurality of balancing resistors 106 that are configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs 102 when the respective SLCFETs 102 are activated. The balancing resistors 106 can be coupled to provide a current path for a balancing current that can be approximately equal (e.g., equal and opposite) to the gate current through the gate resistors. As a first example, the balancing resistors 106 can include a first balancing resistor 106 that is coupled between a gate and a drain of a first one of the SLCFETs 102, and the remaining balancing resistors 106 can interconnect the gate terminals of pairs of the SLCFETs 102 in the sequence. In the first example, the SLCFET switch system 100 can include a DC-blocking capacitor arranged in series with the first balancing resistor 106 to provide DC filtering of the AC current associated with the RF signal RF.sub.IN. As a second example, each of the balancing resistors 106 can be arranged in series with a DC-blocking capacitor between the gate and the drain of each of the SLCFETs 102. In either example, the balancing resistors 106 compensate for the portion of the AC current flow associated with the RF signal RF.sub.IN through the gate resistors, thereby balancing the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs 102. Accordingly, the balanced drain-gate voltage and a gate-source voltage associated with each of the SLCFETs 102 can provide for a more linear propagation of the RF signal with minimal losses.

[0022] FIG. 2 illustrates an example circuit diagram of a SLCFET switch system 200. The SLCFET switch system 200 can correspond to the SLCFET switch system 100 in the example of FIG. 1. Therefore, reference is to be made to the example of FIG. 1 in the following description of the example of FIG. 2.

[0023] The SLCFET switch system 200 includes a plurality N of SLCFETs, demonstrated as N-FET devices N.sub.1 through N.sub.N, where N is an integer greater than one. The SLCFETs N.sub.1 through N.sub.N are demonstrated as arranged in a series stack such that the source of one SLCFET is coupled to a drain of a next SLCFET in the series sequence. Therefore, in response to concurrent activation of the SLCFETs N.sub.1 through N.sub.N, the channels of the SLCFETs N.sub.1 through N.sub.N through the drain-to-source connections can provide for a propagation path of the input RF signal RF.sub.IN provided to the SLCFET switch system 200 at a first port 202 and provided from a second port 204 as an output RF signal RF.sub.OUT. Therefore, as described above, the propagation path of the RF signal (described hereinafter as the RF signal RF.sub.IN) through the series stack of the SLCFETs N.sub.1 through N.sub.N can provide that the peak voltage of the RF signal RF.sub.IN is distributed across each of the SLCFETs N.sub.1 through N.sub.N (e.g., as VDS) to accommodate approximately the full amplitude of the current associated with the RF signal RF.sub.IN without saturating the SLCFETs N.sub.1 through N.sub.N.

[0024] In the example of FIG. 2, the SLCFET switch system 200 includes a plurality of feedforward capacitors C.sub.FF1 through CFEN and shunt resistors R.sub.S1 through R.sub.SN. The feedforward capacitors C.sub.FF1 through CFEN are each arranged in parallel with the drain-source channels of each of the respective SLCFETs N.sub.1 through N.sub.N, and the shunt resistors R.sub.S1 through R.sub.SN are each arranged in parallel with the feedforward capacitors C.sub.FF1 through CFEN and with the drain-source channels of each of the respective SLCFETs N.sub.1 through N.sub.N. Therefore, the feedforward capacitors C.sub.FF1 through CFEN and shunt resistors R.sub.S1 through R.sub.SN can provide for a substantially balanced voltage swing of the RF signal RF.sub.IN in a deactivated state of the SLCFETs N.sub.1 through N.sub.N without the high-power RF signal RF.sub.IN conducting through the channels of the SLCFETs N.sub.1 through N.sub.N in the series stack.

[0025] As also demonstrated in the example of FIG. 2, the SLCFET switch system 200 includes a set of gate resistors R.sub.G1 through R.sub.GN that are each coupled between an activation port 206 and a gate terminal of a respective one of the SLCFETs N.sub.1 through N.sub.N. The activation port 206 is configured to receive an activation signal ACT to concurrently activate the SLCFETs N.sub.1 through N.sub.N. As an example, the gate resistors R.sub.G1 through R.sub.GN can have resistance values that are selected based on the desired switching speed of the SLCFET switch system 200 and to facilitate a sufficient maximum control voltage (e.g., Vas) for activation of the SLCFETs N.sub.1 through N.sub.N.

[0026] The SLCFET switch system 200 further includes a DC-blocking capacitor C.sub.DC and a set of balancing resistors R.sub.B1 through R.sub.BN. The DC-blocking capacitor C.sub.DC and a first one of the balancing resistors R.sub.BN are provided in series between a gate of the first SLCFET N.sub.N and the first port 202. The remaining balancing resistors R.sub.B1 through R.sub.BN-1 are provided between gate terminals of pairs of the SLCFETs N.sub.1 through N.sub.N. The DC-blocking capacitor C.sub.DC and the balancing resistors R.sub.B1 through R.sub.BN can provide a current path for a balancing current during activation of the SLCFETs N.sub.1 through N.sub.N. The balancing current can thus compensate for the gate current through the gate resistors R.sub.G1 through R.sub.GN. Therefore, balancing current through the balancing resistors R.sub.B1 through R.sub.BN can balance the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs N.sub.1 through N.sub.N.

[0027] The resistance values R.sub.B1 through R.sub.BN (italicized to distinguish resistance values from balancing resistor labels) of the respective balancing resistors R.sub.B1 through R.sub.BN can be selected to provide the balancing current for each of the SLCFETs to be approximately equal to the gate current for the respective one of the gate resistors R.sub.G1 through R.sub.GN. Therefore, the resistance values R.sub.B1 through R.sub.BN can be selected to properly compensate for the gate currents to balance the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs N.sub.1 through N.sub.N. As an example, the resistance value R.sub.k of each of the respective balancing resistors R.sub.B1 through R.sub.BN, where k is the index number of the respective one of the balancing resistors (k=1 through N), can be selected based on the following equations:

Resistance R.sub.B1 (k=1) of the last balancing resistor (R.sub.B1):

[00001]$\begin{array}{cc}{R}_{B1}=2*R_g& \mathrm{Equation}1\end{array}$ [0028] Where: R.sub.g is the resistance value of the gate resistors R.sub.G1 through R.sub.GN.
Resistance R.sub.k (k=2 through N1) of each of the intermediate balancing resistors (R.sub.B2 through R.sub.BN-1):

[00002]$\begin{array}{cc}{R}_k={\left(\frac{1}{R_{k-1}}+\frac{2N-1}{R_g}\right)}^{-1}& \mathrm{Equation}2\end{array}$ [0029] Where: N is the quantity of SLCFETs/balancing resistors.
Resistance R.sub.BN (k=N) of the first balancing resistor (R.sub.BN):

[00003]$\begin{array}{cc}{R}_{\mathrm{BN}}={\left(\frac{2}{R_{N-1}}+\frac{2N-1}{R_g}\right)}^{-1}& \mathrm{Equation}3\end{array}$

[0030] FIG. 3 illustrates an example diagram 300 of current flow in the SLCFET switch system 200. The diagram 300 in the example of FIG. 3 demonstrates the AC currents associated with the RF signal RF.sub.IN in the SLCFET switch system 200. Therefore, like reference numbers and labels are used in the example of FIG. 3 as are provided in the example of FIG. 2.

[0031] The diagram 300 only demonstrates a portion of the SLCFET switch system 200, and thus just the first two of the SLCFETs N.sub.1 and N.sub.2. In the example of FIG. 3, the activation signal ACT is provided at the activation port 206 to concurrently activate the SLCFETs N.sub.1 through N.sub.N. In response, the RF signal RF.sub.IN is provided to the first port 202. As a result, an AC current portion of the RF signal RF.sub.IN flows through the SLCFETs N.sub.1 through N.sub.N. The DC-blocking capacitor C.sub.DC filters the DC component of the current associated with the RF signal RF.sub.IN through the balancing resistors R.sub.B1 through R.sub.BN. Thus, in the example of FIG. 3, the AC currents are demonstrated as bidirectional based on the AC current flow of the RF signal RF.sub.IN.

[0032] The AC currents associated with the RF signal RF.sub.IN include currents through the first SLCFET N.sub.N. The currents through the first SLCFET N.sub.N include a drain-gate current I.sub.DGN and a gate-source current I.sub.GSN. The drain-gate current I.sub.DGN thus provides for a drain-gate voltage V.sub.DGN between the drain and the gate of the first SLCFET N.sub.N, and the gate-source current I.sub.GSN thus provides for a gate-source voltage V.sub.GSN between the gate and the source of the first SLCFET N.sub.N. If the amplitudes of the drain-gate voltage V.sub.DGN and the gate-source voltage V.sub.GSN are approximately equal, then the SLCFET N.sub.N can exhibit suitable operational characteristics to provide for enhanced linearity and low-loss propagation of the high-frequency and high-power RF signal RF.sub.IN.

[0033] However, absent the current compensation described in greater detail below, because of the arrangement of the gate resistor R.sub.GN at the gate of the first SLCFET N.sub.N, a portion of the amplitude of the AC current of the RF signal RF.sub.IN flows through the gate resistor R.sub.GN. For example, in a first cycle of the AC current flow, a portion of the drain-gate current I.sub.DGN flows from the gate of the SLCFET N.sub.N to the activation port 206 through the gate resistor R.sub.GN as a gate current I.sub.GN, thereby providing the drain-gate current I.sub.DGN as being greater than the gate-source current I.sub.GSN by an amplitude that is approximately equal to the gate current I.sub.GN. Similarly, in a second cycle of the AC current flow, a portion of the gate-source current I.sub.GSN flows from the activation port 206 to the gate of the SLCFET N.sub.N through the gate resistor R.sub.GN as the gate current I.sub.GN, thereby providing the gate-source current I.sub.GSN as being greater than the drain-gate current I.sub.DGN by an amplitude that is approximately equal to the gate current I.sub.GN. Therefore, in the first cycle of the AC current flow, the gate-source voltage V.sub.GSN is greater than the drain-gate voltage V.sub.DGN, and in the second cycle of the AC current flow, the drain-gate voltage V.sub.DGN is greater than the gate-source voltage V.sub.GSN. The oscillation of the imbalanced drain-gate voltage V.sub.DGN and the gate-source voltage V.sub.GSN can thus result in nonlinearity of the RF signal RF.sub.IN propagating through the SLCFET switch system 200.

[0034] As described above, the balancing resistors R.sub.B1 through R.sub.BN are configured to provide a current path for a balancing current IB. The balancing current I.sub.B can be approximately equal to the gate current to balance the current amplitudes between the drain-gate current I.sub.DGN and the gate-source current I.sub.GSN, and thus approximately equalizes the drain-gate voltage V.sub.DGN and the gate-source voltage V.sub.GSN. For example, in the first cycle of the AC current flow, the portion of the drain-gate current I.sub.DGN flows from the gate of the SLCFET N.sub.N to the activation port 206 through the gate resistor R.sub.GN as the gate current I.sub.GN. However, the balancing current I.sub.BN is likewise provided to the gate of the SLCFET N.sub.N in the first cycle. Because the balancing current I.sub.BN is approximately equal to the gate current I.sub.GN, the net difference between the drain-gate current I.sub.DGN and the gate-source current I.sub.GSN is approximately zero. Similarly, in the second cycle of the AC current flow, the portion of the gate-source current I.sub.GSN flows from the activation port 206 to the gate of the SLCFET N.sub.N through the gate resistor R.sub.GN as the gate current I.sub.GN. However, the balancing current I.sub.BN is likewise provided from the gate of the SLCFET N.sub.N in the second cycle. Because the balancing current I.sub.BN is approximately equal to the gate current I.sub.GN, the net difference between the drain-gate current I.sub.DGN and the gate-source current I.sub.GSN is again approximately zero. Therefore, the drain-gate voltage V.sub.DGN and the gate-source voltage V.sub.GSN can be approximately equalized in each of the cycles of the AC current associated with the RF signal RF.sub.IN.

[0035] The diagram 300 demonstrates a same distribution of the AC current flows associated with the RF signal RF.sub.IN with respect to the second SLCFET N.sub.N-1. Particularly, in the first cycle of the AC current flow, the portion of the drain-gate current I.sub.DGN-1 flows from the gate of the SLCFET N.sub.N-1 to the activation port 206 through the gate resistor R.sub.GN-1 as the gate current I.sub.GN-1 and the balancing current I.sub.BN-1 is likewise provided to the gate of the SLCFET N.sub.N-1. Therefore, the net difference between the drain-gate current I.sub.DGN-1 and the gate-source current I.sub.GSN-1 is approximately zero. Similarly, in the first cycle of the AC current flow, the portion of the drain-gate current I.sub.DGN-1 flows from the gate of the SLCFET N.sub.N-1 to the activation port 206 through the gate resistor R.sub.GN-1 as the gate current I.sub.GN-1 and the balancing current I.sub.BN-1 is likewise provided to the gate of the SLCFET N.sub.N-1. Therefore, the net difference between the drain-gate current I.sub.DGN-1 and the gate-source current I.sub.GSN-1 is approximately zero. The same AC current distribution is provided at each of the SLCFETs N.sub.1 through N.sub.N of the SLCFET switch system 200, thereby providing approximately equalization of the drain-gate voltages VDG and gate-source voltages VGS of the SLCFETs N.sub.1 through N.sub.N to provide for enhanced linearity of the RF signal RF.sub.IN propagating through the SLCFET switch system 200.

[0036] FIG. 4 illustrates another example circuit diagram of a SLCFET switch system 400. The SLCFET switch system 400 can correspond to the SLCFET switch system 100 in the example of FIG. 1. Therefore, reference is to be made to the example of FIG. 1 in the following description of the example of FIG. 4.

[0037] Similar to the SLCFET switch system 200 in the example of FIG. 2, the SLCFET switch system 400 includes a plurality N of SLCFETs, demonstrated as N-FET devices N.sub.1 through N.sub.N, where N is an integer greater than one. The SLCFETs N.sub.1 through N.sub.N are demonstrated as arranged in a series stack such that the source of one SLCFET is coupled to a drain of a next SLCFET in the series sequence. Therefore, in response to concurrent activation of the SLCFETs N.sub.1 through N.sub.N, the channels of the SLCFETs N.sub.1 through N.sub.N through the drain-to-source connections can provide for a propagation path of the input RF signal RF.sub.IN provided to the SLCFET switch system 400 at a first port 402 and provided from a second port 404 as an output RF signal RF.sub.OUT.

[0038] Also similar to the SLCFET switch system 200 in the example of FIG. 2, the SLCFET switch system 400 includes a plurality of feedforward capacitors C.sub.FF1 through C.sub.FFN and shunt resistors R.sub.S1 through R.sub.SN. The feedforward capacitors C.sub.FF1 through CFEN are each arranged in parallel with the drain-source channels of each of the respective SLCFETs N.sub.1 through N.sub.N, and the shunt resistors R.sub.S1 through R.sub.SN are each arranged in parallel with the feedforward capacitors C.sub.FF1 through CFEN and with the drain-source channels of each of the respective SLCFETs N.sub.1 through N.sub.N. Therefore, the feedforward capacitors C.sub.FF1 through C.sub.FFN and shunt resistors R.sub.S1 through R.sub.SN can provide for a substantially balanced voltage swing of the RF signal RF.sub.IN in a deactivated state of the SLCFETs N.sub.1 through N.sub.N without the high-power RF signal RF.sub.IN conducting through the channels of the SLCFETs N.sub.1 through N.sub.N in the series stack.

[0039] As also demonstrated in the example of FIG. 4, the SLCFET switch system 400 includes a set of gate resistors R.sub.G1 through R.sub.GN that are each coupled between an activation port 406 and a gate terminal of a respective one of the SLCFETs N.sub.1 through N.sub.N. The activation port 406 is configured to receive an activation signal ACT to concurrently activate the SLCFETs N.sub.1 through N.sub.N. As an example, the gate resistors R.sub.G1 through R.sub.GN can have resistance values that are selected based on the desired switching speed of the SLCFET switch system 400 and to facilitate a sufficient maximum control voltage (e.g., Vas) for activation of the SLCFETs N.sub.1 through N.sub.N.

[0040] The SLCFET switch system 400 further includes a plurality of DC-blocking capacitors C.sub.DC1 through C.sub.DCN and a set of balancing resistors R.sub.B1 through R.sub.BN. Each of the DC-blocking capacitors C.sub.DC1 through C.sub.DCN and a respective one of the balancing resistors R.sub.B1 through R.sub.BN are provided in series between a gate and a drain of a respective one of the SLCFETs N.sub.1 through N.sub.N. Therefore, each of the DC-blocking capacitors C.sub.DC1 through C.sub.DCN and the respective one of the balancing resistors R.sub.B1 through R.sub.BN can provide a separate respective current path for one of the balancing currents I.sub.B1 through I.sub.BN that is provided through a respective one of the balancing resistors R.sub.B1 through R.sub.BN in parallel with a respective one of the drain-gate currents I.sub.DG1 through I.sub.DGN. Similar to as described above, the balancing current I.sub.B can thus compensate for the gate current through the gate resistors R.sub.G1 through R.sub.GN. Therefore, balancing current through the balancing resistors R.sub.B1 through R.sub.BN can balance the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs N.sub.1 through N.sub.N.

[0041] Similar to as described above, the resistance values R.sub.B1 through R.sub.BN of the balancing resistors R.sub.B1 through R.sub.BN can be selected to provide the balancing current for each of the SLCFETs to be approximately equal to the gate current for the respective one of the gate resistors. Therefore, the resistance values R.sub.B1 through R.sub.BN can be selected to properly compensate for the gate currents to balance the drain-gate voltage and a gate-source voltage associated with each of the SLCFETs N.sub.1 through N.sub.N. As an example, the resistance values R.sub.B1 through R.sub.BN of the balancing resistors R.sub.B1 through R.sub.BN can be selected based on the following equation:

[00004]$\begin{array}{cc}{R}_k=\left(\frac{R_g}{2*k-1}\right)& \mathrm{Equation}4\end{array}$

[0042] Where: k is the index number of the respective one of the balancing resistors.

[0043] FIG. 5 illustrates an example of an RF switch system 500. The RF switch system 500 includes a plurality X of complementary switch systems 502, where X is an integer greater than zero. The RF switch system 500 can be implemented in any of a variety of applications in which an RF signal is switched between multiple inputs and/or outputs, such as an antenna system.

[0044] Each of the complementary switch systems 502 includes an input/output port, demonstrated as I/O port 1 through I/O port X that can correspond to one of an input or an output for the respective complementary switch system 502. Each of the complementary switch systems 502 also includes an I/O port matching network 504 that can correspond to an impedance matching network for an RF signal that propagates into or from the respective I/O port. Each of the complementary switch systems 502 further includes a first SLCFET switch system 506 and a second SLCFET switch system 508. The first SLCFET switch system 506 is demonstrated as interconnecting a complement node 510 and a low-voltage rail (e.g., ground), and the second SLCFET switch system 508 is demonstrated as interconnecting the complement node 510 and a common node 512. Each of the complementary switch systems 502 is provided a respective activation signal, demonstrated as ACT1 through ACTX. The respective activation signal ACT is provided to the second SLCFET switch system 508 in each of the complementary switch systems 502 and to an inverter 514 that provides a complement of the activation signal ACT to the first SLCFET switch system 506. Therefore, one of the SLCFET switch systems 506 and 508 is activated at a given time to either couple the respective I/O port to ground or to couple the I/O port to the common node 512 via the complement node 510.

[0045] The common node 512 is coupled to an I/O terminal via an I/O terminal matching network 516. The I/O matching network can correspond to an impedance matching network for the RF signal that propagates into or from the respective I/O terminal. Therefore, the I/O terminal can correspond to a common input or output terminal for an RF signal to propagate to and/or from a given one of the I/O ports at a given time based on the logic states of the activation signals ACT1 through ACTX. For example, a given one of the activation signals ACT can be asserted at a given time to activate the second SLCFET switch system 508 of a first one of the complementary switch systems 502 to route an RF signal from the respective I/O port of the complementary switch system 502 to the I/O terminal. In this example, the other activation signals can be de-asserted to activate the first SLCFET switch systems 506 of each of the other complementary switch systems 502 to couple the respective I/O terminals of the other complementary switch systems 502 to ground. Therefore, the I/O ports of the other complementary switch systems 502 can be isolated from the I/O terminal to facilitate RF communication between the I/O port of the first one of the complementary switch systems 502 and the I/O terminal.

[0046] FIG. 6 illustrates an example diagram of an RF antenna system 600. The RF antenna system 600 includes an antenna controller 602. The antenna controller 602 can correspond to an example of the RF switching system 500 in the example of FIG. 5. Therefore, reference is to be made to the example of FIG. 5 in the following description of the example of FIG. 6.

[0047] In the example of FIG. 6, the antenna controller 602 includes a first complementary transmit switch system 604, a second complementary transmit switch system 606, and a complementary receive switch system 608. Each of the complementary switch systems 604, 606, and 608 can correspond to a respective one of the complementary switch systems 502 in the example of FIG. 5, and can thus each include a first SLCFET switch system 506 interconnecting a complement node 510 to ground and a second SLCFET switch system 508 interconnecting the complement node 510 and the common node 512. Additionally, each of the complementary switch systems 604, 606, and 608 are demonstrated as coupled to an antenna 610 that is configured to transmit and receive wireless RF signals. The antenna 610 can be coupled to the I/O terminal in the example of FIG. 5, and can thus be coupled to the common node 512 via the I/O terminal matching network 516.

[0048] The RF antenna system 600 also includes a first high power amplifier (HPA) 612 that is coupled to the first complementary transmit switch system 604 and a second high power amplifier (HPA) 614 that is coupled to the second complementary transmit switch system 606. The first high power amplifier 612 is configured to amplify a first transmit signal TX1 that is provided to the first complementary transmit switch system 604 and the second high power amplifier 614 is configured to amplify a second transmit signal TX2 that is provided to the second complementary transmit switch system 606. Additionally, the RF antenna system 600 includes a low noise amplifier (LNA) 616 that is coupled to the complementary receive switch system 608. The LNA 616 is configured to amplify a receive signal RX that is provided from the complementary receive switch system 608.

[0049] As a first example, the activation signal ACT of the first complementary transmit switch system 604 can be asserted to activate the SLCFETs of the second SLCFET switch system 508 of the first complementary transmit switch system 604. The activation signals ACT of the second complementary transmit switch system 606 and the complementary receive switch system 608 can be de-asserted to activate the SLCFETs of the first SLCFET switch system 506 of each of the second complementary transmit switch system 606 and the complementary receive switch system 608. Therefore, the first transmit signal TX1 can be amplified by the first high power amplifier 612 and routed to the antenna 610 via the second SLCFET switch system 508 of the first complementary transmit switch system 604 for transmission from the antenna 610. The signal paths for the second transmit signal TX2 and the receive signal RX can be isolated via the first SLCFET switch system 506 of each of the second complementary transmit switch system 606 and the complementary receive switch system 608.

[0050] As a second example, the activation signal ACT of the second complementary transmit switch system 606 can be asserted to activate the SLCFETs of the second SLCFET switch system 508 of the second complementary transmit switch system 606. The activation signals ACT of the first complementary transmit switch system 604 and the complementary receive switch system 608 can be de-asserted to activate the SLCFETs of the first SLCFET switch system 506 of each of the first complementary transmit switch system 604 and the complementary receive switch system 608. Therefore, the second transmit signal TX2 can be amplified by the second high power amplifier 614 and routed to the antenna 610 via the second SLCFET switch system 508 of the second complementary transmit switch system 606 for transmission from the antenna 610. The signal paths for the first transmit signal TX1 and the receive signal RX can be isolated via the first SLCFET switch system 506 of each of the first complementary transmit switch system 604 and the complementary receive switch system 608.

[0051] As a third example, the activation signal ACT of the complementary receive switch system 608 can be asserted to activate the SLCFETs of the second SLCFET switch system 508 of the complementary receive switch system 608. The activation signals ACT of the first and second complementary transmit switch systems 604 and 606 can be de-asserted to activate the SLCFETs of the first SLCFET switch system 506 of each of the first and second complementary transmit switch systems 604 and 606. Therefore, the receive signal RX can be received from the antenna 610, routed through the second SLCFET switch system 508 of the complementary receive switch system 608, and amplified by the LNA 616. The signal paths for the first and second transmit signals TX1 and TX2 can be isolated via the first SLCFET switch system 506 of each of the first and second complementary transmit switch systems 604 and 606.

[0052] What has been described above are examples. It is, of course, not possible to describe every conceivable combination of components or methodologies, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Accordingly, the disclosure is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. As used herein, the term includes means includes but not limited to, the term including means including but not limited to. The term based on means based at least in part on. Additionally, where the disclosure or claims recite a, an, a first, or another element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements.