Abstract
A Ga.sub.2O.sub.3 heterojunction bipolar device includes a first electrode, a second electrode, a -Ga.sub.2O.sub.3 substrate between the first electrode and the second electrode, and a NiO.sub.x layer in contact with (201), (001), or (010) plane of the -Ga.sub.2O.sub.3 substrate. A surface of the -Ga.sub.2O.sub.3 substrate defines a (201), (001), or (010) plane, and the interface between the NiO.sub.x layer and the -Ga.sub.2O.sub.3 substrate is a p-n heterojunction. Fabricating the Ga.sub.2O.sub.3 heterojunction bipolar device includes depositing a first electrode on a surface of a Ga.sub.2O.sub.3 substrate defining a (201), (001), or (010) plane of the -Ga.sub.2O.sub.3 substrate, depositing a NiO.sub.x layer on an opposite surface of the substrate, and depositing a second electrode on the NiO.sub.x layer to yield the device.
Claims
1. A method of fabricating a Ga.sub.2O.sub.3 heterojunction bipolar device, the method comprising: depositing a first electrode on a first surface of a substrate, wherein first the surface of the substrate comprises -Ga.sub.2O.sub.3 defining a (201), (001), or (010) crystal plane; depositing a NiO.sub.x layer on a second surface of the substrate; and depositing a second electrode on a surface of the NiO.sub.x layer to yield the device.
2. The method of claim 1, wherein depositing the first electrode on the first surface of the substrate comprises E-beam evaporation of an electrically conductive material on the first surface of the substrate.
3. The method of claim 2, further comprising annealing the first electrode and the substrate.
4. The method of claim 1, further comprising defining a pattern on the substrate before depositing the NiO.sub.x layer on the second surface of the substrate.
5. The method of claim 4, wherein defining the pattern comprises a photolithographic process.
6. The method of claim 4, wherein the pattern is a circular pattern.
7. The method of claim 1, wherein depositing the NiO.sub.x layer comprises E-beam evaporation followed by a lift-off process.
8. The method of claim 1, further comprising annealing the device.
9. The method of claim 8, wherein the annealing comprises heating the device to a temperature in a range between 250 C. and 450 C.
10. The method of claim 9, wherein the temperature is in a range between 300 C. and 400 C.
11. A Ga.sub.2O.sub.3 heterojunction bipolar device comprising: a first electrode; a second electrode; a -Ga.sub.2O.sub.3 substrate between the first electrode and the second electrode, wherein a surface of the -Ga.sub.2O.sub.3 substrate defines a (201), (001), or (010) plane; and a NiO.sub.x layer in contact with (201), (001), or (010) plane of the -Ga.sub.2O.sub.3 substrate, wherein the interface between the NiO.sub.x layer and the -Ga.sub.2O.sub.3 substrate is a p-n heterojunction.
12. The device of claim 11, wherein the -Ga.sub.2O.sub.3 substrate is doped.
13. The device of claim 12, wherein the -Ga.sub.2O.sub.3 substrate is doped with tin.
14. The device of claim 13, wherein a concentration of the tin in the -Ga.sub.2O.sub.3 substrate is in a range of 110.sup.18 cm.sup.3 to 1010.sup.18 cm.sup.3.
15. The device of claim 11, wherein a thickness of the NiO.sub.x layer is in a range of 0.1 m to 0.3 m.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0014] FIG. 1A shows monoclinic crystal structure of -Ga.sub.2O.sub.3 with crystal planes of (201), (001), and (010) labelled. FIG. 1B is a schematic of fabricated NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions.
[0015] FIGS. 2A and 2B show I-V characteristics of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions on three crystallographic orientations in linear scale and semi-log scale, respectively.
[0016] FIGS. 3A and 3B show C-V measurements and 1/C.sup.2-V plots, respectively, of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions for three crystallographic orientations. FIGS. 3C-3E show C-f characteristics with corresponding fitting curves for devices on (201), (001), and (010) planes, respectively.
[0017] FIGS. 4A-4C show temperature dependent I-V curves for the devices on (201), (001), and (010), respectively. Variation of turn-on voltage and ideality factor of corresponding I-V curves are shown in FIGS. 4D-4F.
[0018] FIG. 5A shows recovery of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions on three crystallographic orientations. FIG. 5B shows temperature-dependent reverse recovery of p-n diodes on (201) plane.
DETAILED DESCRIPTION
[0019] This disclosure describes Ga.sub.2O.sub.3 heterojunction bipolar devices and methods of fabricating the devices. FIG. 1A depicts the crystal structure of -Ga.sub.2O.sub.3 and the corresponding planes used as substrates. FIG. 1B depicts Ga.sub.2O.sub.3 heterojunction bipolar device 100. Ga.sub.2O.sub.3 heterojunction bipolar device 100 has first electrode 102, second electrode 104, -Ga.sub.2O.sub.3 substrate 106 between the first electrode and the second electrode, and NiO.sub.x layer 108 in contact with the (201), (001), or (010) plane of -Ga.sub.2O.sub.3 substrate 106. Surface 110 of -Ga.sub.2O.sub.3 substrate 106 defines a (201), (001), or (010) plane. Interface 112 between the NiO.sub.x layer and the -Ga.sub.2O.sub.3 substrate is a p-n heterojunction. As depicted in FIG. 1B, components of Ga.sub.2O.sub.3 heterojunction bipolar device 100 have specific compositions and dimensions. However, other components in other embodiments may have different compositions, dimensions, or both.
[0020] First electrode 102 and second electrode 104 are composed of one or more metals. As depicted in FIG. 1B, first electrode 102 is composed of Ti/Al, and second electrode 104 is composed of Ni/Au. -Ga.sub.2O.sub.3 substrate 106 can be doped (e.g., with tin). A concentration of the dopant is typically in a range of about 110.sup.18 cm.sup.3 to about 1010.sup.18 cm.sup.3 (e.g., about 510.sup.18 cm.sup.3). A thickness of NiO.sub.x layer 108 is typically in a range of about 0.1 m to about 0.3 m (e.g., about 0.2 m).
[0021] Fabricating Ga.sub.2O.sub.3 heterojunction bipolar device 100 includes depositing first electrode 102 on a first surface of substrate 106, depositing NiO.sub.x layer 108 on a second surface of substrate 106, depositing second electrode 104 on a surface of NiO.sub.x layer 108 to yield device 100, and annealing the device. The first the surface of substrate 106 defines a (201), (001), or (010) crystal plane of -Ga.sub.2O.sub.3. Depositing first electrode 102 on the first surface of substrate 106 can be achieved by E-beam evaporation of an electrically conductive material on the first surface of substrate 106. First electrode 102 and substrate 106 can be annealed. A pattern (e.g., a circular pattern) can be defined (e.g., with a photolithographic process) on substrate 106 before depositing NiO.sub.x layer 108 on the second surface of substrate 106. Depositing the NiO.sub.x layer can include E-beam evaporation followed by a lift-off process. Device 100 is annealed by heating to a temperature in a range between 250 C. and 450 C. (e.g., between 300 C. and 400 C.).
[0022] The low crystal symmetry of monoclinic -Ga.sub.2O.sub.3 results in highly anisotropic material with direct impact on several key physical and electronic properties, such as dielectric constant, thermal conductivity, and electron mobility, which are different along different crystallographic directions. This anisotropy poses challenges for device fabrication and results in discrepancies in device performance. This disclosure describes a systematic comparative analysis of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions with (201), (001), and (010) substrate orientations. Results from temperature-dependent electrical measurements, reverse recovery characteristics, and capacitance-frequency (C-f) measurements provide better understanding of the anisotropic nature of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions.
[0023] NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions fabricated on (201), (001), and (010) substrates showed considerable differences in electrical properties in terms of turn-on voltages, ideality factor, on-resistance, and reverse recovery time. The (010) device exhibited the highest turn-on voltage of 2.50 V, the highest ideality factor of 2.13, the largest on-resistance of 6.50 mcm.sup.2, and the lowest recovery time of 62 ns. The C-f measurements indicate an interface trap density of 4.310.sup.10, 7.410.sup.10, and 1.610.sup.11 eV.sup.1 cm.sup.2 for (201), (001), and (010) plane devices, respectively. All devices were fabricated simultaneously and exhibited excellent rectifying behaviors with high on/off ratio of 10.sup.9 and high-quality interfaces between NiO.sub.x and -Ga.sub.2O.sub.3, as confirmed by HRTEM. These differences in device electrical properties are attributed to the different atomic configurations, the density of dangling bonds, and interface trap state densities.
[0024] Edge-defined film-fed grown (201), (001), and (010) -Ga.sub.2O.sub.3 substrates from Novel Crystal Technology were used. The substrates had similar n-type [Sn] doping concentrations of 510.sup.18 cm.sup.3, similar thickness, and good crystalline quality, as verified by XRD measurements. To prepare the substrates, a standard cleaning procedure was implemented, which included cleaning with acetone, isopropyl alcohol, and deionized water, aided by sonication. The back contacts of Ti/Au (20/130 nm) were deposited using electron beam (E-beam) evaporation, followed by rapid thermal annealing at 500 C. in an N.sub.2 environment. All back contacts showed very low contact resistance of <0.01 mcm.sup.2. Standard photolithography was then performed to define circular patterns for the deposition of NiO.sub.x and the anode (diameter of 300 m). 200 nm NiO.sub.x and the anode Ni/Au (20/130 nm) were deposited using E-beam evaporation, followed by a lift-off process. The anode, cathode, and NiO.sub.x layers were deposited simultaneously for all samples to avoid any inconsistencies in fabrication. All NiO.sub.x layers were highly doped with a similar hole density of >218 cm.sup.3, and the Ohmic contacts to NiO.sub.x layers had a similar contact resistance of 0.3 mcm.sup.2. After device fabrication, all samples were annealed at 350 C. in N.sub.2 ambient for 1 minute. This annealing step was expected to improve the device performance by forming an Ohmic contact between the Ni/NiO.sub.x interface and reducing the number of interface states at the NiO.sub.x/-Ga.sub.2O.sub.3 heterojunction.
[0025] Electrical characterization was conducted using a probe station equipped with a controllable thermal chuck, Keithley 4200-SCS parameter analyzer, and ultra-fast pulse measurement units. Cross-sectional transmission electron microscope (XTEM) images were taken for all samples. The TEM samples were prepared using a Thermo Fisher Helios 5UX Dualbeam system with final thinning in a Gatan precision ion-polishing system. The milling started with a Ga-focused ion beam at 30 keV, followed by thinning at 5 and 2 keV, and subsequent Ar-ion thinning at 2 and 1 keV. Devices with (201), (001), and (010) -Ga.sub.2O.sub.3 substrate normals were imaged along their respective [010], [100] and [001] zone axes. High-resolution TEM (HRTEM) images were taken using a Philips CM 200 operated at 200 kV and an image-corrected FEI Titan 80-300 operated at 300 kV. An XTEM image of the full diode structure consisting of the top electrode (Au, Ni), NiO.sub.x, and -Ga.sub.2O.sub.3 substrate was obtained. HRTEM images of the NiO.sub.x/-Ga.sub.2O.sub.3 interface for samples grown on (201), (001) and (010) substrates were also obtained. The polycrystalline nature of NiO.sub.x layers was evident in HRTEM images, and abrupt NiO.sub.x/-Ga.sub.2O.sub.3 interfaces were clearly visible.
[0026] FIG. 2A shows I-V curves for the three NiO.sub.x/-Ga.sub.2O.sub.3 p-n diodes, where the turn-on voltages were 2.09, 2.22, and 2.50 V for (201), (001), and (010) substrates, respectively. Devices on (201) and (001) planes had excellent rectification ratios of 10.sup.10 at 3.75 V. However, (010) devices showed a smaller on/off ratio of about 10.sup.9 at 3.75 V. Furthermore, devices on (201) and (001) planes exhibited specific on-resistances of 2.92 and 1.55 mcm.sup.2, while the (010) device showed a specific on-resistance of 6.50 mcm.sup.2. Ideality factors were 1.95, 2.03, and 2.13 for (201), (001), and (010) planes, respectively. These large ideality factors indicate that the current recombination in the heterojunction is dominant compared to diffusion currents.
[0027] FIG. 3A shows C-V measurements performed at a frequency of 100 kHz. The devices showed built-in potentials of 2.72, 2.74, and 2.63 V on (201), (001), and (010) devices, respectively as shown in FIG. 3B. The built-in voltages were comparable in all three devices since there is no current transport through the devices in C-V measurements. The built-in voltages determined by I-V and C V measurements showed some discrepancies. In general, C-V measurements are mainly affected by the doping concentration of NiO.sub.x and -Ga.sub.2O.sub.3, as well as the charges from the interface states. However, they do not provide information about the current conduction through the interface. Conversely, extraction of built-in voltage through I-V measurements is influenced by the crystal anisotropy and interface states. The effective carrier concentration (N.sub.dN.sub.a+N.sub.t) calculated from the C-V measurements was 4.710.sup.18, 4.510.sup.18, 1.610.sup.18 cm.sup.3 for (201), (001), and (010) devices, respectively, where N.sub.d is the ionized donor concentration, N.sub.a is the ionized acceptor concentration, and N.sub.t is the equivalent charge concentration of traps. Since the -Ga.sub.2O.sub.3 and NiO.sub.x film in the three samples had similar carrier concentrations, the observed variation in the effective carrier concentrations is likely related to the different NiO.sub.x/-Ga.sub.2O.sub.3 heterojunction interfaces caused by the crystal anisotropy, which is verified by C-f measurements.
[0028] FIGS. 3C-3E show C-f measurements for the devices on (201), (001), and (010) substrates to evaluate the interface trap state density (D.sub.it). The C-f measurements are fitted using the equations below, assuming the interface states are distributed in two energy levels.
[00001]
where C.sub.sc is the capacitance of the space charge region, and C.sub.it-1(C.sub.it-2) is the capacitance of the first state (second state) with their corresponding relaxation time .sub.1 (.sub.2). C.sub.it-1 represents an energy level that corresponds to interface states closer to the conduction band with smaller relaxation time, and C.sub.it-2 represents a deep energy level with a considerably larger relaxation time. A similar C.sub.it-2 of 210.sup.12 F was observed with a relaxation time of about 8 s for all devices. This may represent deep-level states (e.g., vacancies) with relaxation time much larger than the interface states. However, C.sub.it-1 varied significantly for devices on different crystal orientations. The relaxation time for C.sub.it-1 was 0.64, 0.43 and 0.34 s for (201), (001), and (010) devices, respectively. C.sub.it-1 changed with crystal orientation, while C.sub.it-2 remained relatively constant. It should be noted that the exact nature of the defect states in NiO.sub.x/-Ga.sub.2O.sub.3 diodes is still unclear and demands further investigation. The extracted interface trap densities (D.sub.it-1) from C.sub.it-1 were 4.310.sup.10, 7.410.sup.10, and 1.610.sup.11 eV.sup.1 cm.sup.2 for (201), (001), and (010) devices, respectively. The interface states derived from C.sub.it-1 are much closer to the conduction band, and thus may play an important role in the device performance. Table 1 summarizes all the parameters extracted through C-f curve fitting.
TABLE-US-00001 TABLE 1 Interface state parameters extracted from C-f curve fitting. D.sub.it 1 D.sub.it 2 Orientation C.sub.it 1 (F) C.sub.it 2 (F) .sub.1 (s) .sub.2 (s) (eV.sup.1cm.sup.2) (eV.sup.1cm.sup.2) (201) 4.80 10.sup.12 2.50 10.sup.12 0.64 10.sup.6 8.69 10.sup.6 4.3 10.sup.10 2.2 10.sup.10 (001) 8.36 10.sup.12 2.27 10.sup.12 0.43 10.sup.6 8.57 10.sup.6 7.4 10.sup.10 2.0 10.sup.10 (010) 1.79 10.sup.11 1.62 10.sup.12 0.34 10.sup.6 8.02 10.sup.6 1.6 10.sup.11 1.4 10.sup.10
[0029] The differences in electrical properties of NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions can be attributed to several factors. First, the difference in interface states may be significantly promoted by the density of dangling bonds. If the number of dangling bonds is high, then the adhesion of NiO.sub.x layer is promoted, exhibiting fewer interface states. Due to the higher dangling bond density in (201) and (001) plane, it is easier to form better-quality NiO.sub.x/-Ga.sub.2O.sub.3 heterojunction with high surface energy. This is analogous to the fact that forming Ohmic contacts on (201) and (001) planes are easier than on (010) plane. Second, different doping concentrations can be induced in the heterojunction due to interface states. The interface states can have a big impact on net charge density. It is likely that there are lower compensating trap states in (201) and (001) NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions as indicated by the C-f measurement, contributing larger net charge densities. This is further evidenced by the different gradients in the 1/C.sup.2-V plot. The observed differences are primarily influenced by the presence of interface states, considering three NiO.sub.x and -Ga.sub.2O.sub.3 in the three samples had similar carrier concentrations. As discussed later, a difference in reverse recovery time (t.sub.rr) of the devices was observed, indicating that carrier recombination on different planes is affected by the crystal anisotropy.
[0030] The temperature-dependent forward characteristics of three NiO.sub.x/-Ga.sub.2O.sub.3 p-n diodes are shown in FIGS. 4A-4C. The observed temperature-dependent behavior was stable and reproducible, and the initial I-V curves were retained even after heating and cooling down, indicating excellent thermal stability of the heterojunction. The device ideality factor and turn-on voltage were extracted as a function of temperature, as shown in FIGS. 4D-4F. The turn-on voltage decreased linearly with the temperature, which can be attributed to the reduction of depletion width facilitating diffusion of holes. The ideality factor varied between 1.95-3.77, 2.03-2.95, and 2.13-4.47 in (201), (001), and (010) devices, respectively. The ideality factor of (201) and (001) devices remained almost constant under high temperatures. However, the ideality factor in (010) devices first increased and then decreased. This behavior can be attributed to the fact that there are 10 times more interface trap states in (010) heterojunction compared to (201) and (001) heterojunctions. With increasing temperature, the carrier emission from interface traps is enhanced, affecting the ideality factor.
[0031] The t.sub.rr of the diode is defined as the time it takes to reach 0.25I.sub.M after switching off, where I.sub.M is the maximum current during the reverse recovery period. The t.sub.rr of the diodes is affected by several factors, including the doping concentration, the width of the depletion region, crystal anisotropy, and the applied voltage. In this work, all three samples were subject to voltages of 5 V to observe the reverse recovery of the diode. The (201) and (001) devices had a t.sub.rr of 68 ns, while (010) devices took 62 ns to recover. The shorter reverse recovery time for (010) is likely due to larger interface defect densities that promote electron/hole recombination with a faster recovery time and mobility variation along different crystal orientations. All devices had a peak current of about 86 mA and showed temperature independence in reverse recovery time, as shown in FIG. 5B, where the y-axis is offset for clarity. This indicates that the junction capacitance and stored charges in the depletion region are independent of temperature. The forward current during the reverse recovery test was 6 mA. Additionally, the di/dt of three samples for the reverse recovery characteristics was 3.95 A/s. The reverse recovery charge was 4.47, 4.54, and 4.26 nC for (201), (001), and (010) devices, respectively. The different t.sub.rr in different crystal orientations indicate carrier recombination is influenced by the interface states. Table 2 summarizes the device parameters of the three NiO.sub.x/-Ga.sub.2O.sub.3 p-n heterojunctions, where D.sub.it of the devices is based on the dominant D.sub.it-1 values.
TABLE-US-00002 TABLE 2 Electrical properties of the NiO.sub.x/-Ga.sub.2O.sub.3 p-n diode heterojunctions grown on (2 01), (001), and (010) substrates. V.sub.on(I V) V.sub.bi(C V) R.sub.sp-on on/off t.sub.rr D.sub.it Orientation (V) (V) (mcm.sup.2) ratio (ns) (eV.sup.1cm.sup.2) (201) 2.09 2.74 2.92 10.sup.10 1.95 68 4.3 10.sup.10 (001) 2.22 2.72 1.55 10.sup.10 2.03 68 7.4 10.sup.10 (010) 2.50 2.63 6.50 10.sup.9 2.13 62 1.6 10.sup.11
[0032] Although this disclosure contains many specific embodiment details, these should not be construed as limitations on the scope of the subject matter or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this disclosure in the context of separate embodiments can also be implemented, in combination, in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments, separately, or in any suitable sub-combination. Moreover, although previously described features may be described as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.
[0033] Particular embodiments of the subject matter have been described. Other embodiments, alterations, and permutations of the described embodiments are within the scope of the following claims as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed (some operations may be considered optional), to achieve desirable results.
[0034] Accordingly, the previously described example embodiments do not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure.
