Transistor element, ternary inverter apparatus comprising same, and method for producing same

Abstract

A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Claims

1. A ternary inverter device comprising: an NMOS transistor device; and a PMOS transistor device, wherein each of the NMOS transistor device and the PMOS transistor device comprises: a well region; a source region, a drain region and a channel region in the well region, the source region and the drain region are spaced apart from each other in a direction parallel to a top surface of the well region, the channel region is between the source region and the drain region; and a pair of constant current generating patterns provided adjacent to the source region and the drain region in the well region, respectively, each of the pair of constant current generating patterns extends below a channel region between the source region and the drain region and is spaced apart from the other, and the pair of constant current generating patterns generate a constant current between the drain region and a lower portion of the well region, and the drain region of the NMOS transistor device and the drain region of the PMOS transistor device are electrically connected to each other and have a same voltage, wherein the drain region of the NMOS transistor device and the drain region of the PMOS transistor device have: a first voltage when the NMOS transistor device has a channel current that is stronger than the constant current and the PMOS transistor device has the constant current that is stronger than its channel current, a second voltage when the NMOS transistor device has the constant current that is stronger than the channel current and the PMOS transistor device has its channel current that is stronger than the constant current, and a third voltage when each of the NMOS transistor device and the PMOS transistor device has the constant current that is stronger than each respective channel current, wherein the second voltage is greater than the first voltage, and the third voltage has a value between the first voltage and the second voltage.

2. The ternary inverter device of claim 1, wherein each of the NMOS transistor device and the PMOS transistor device further comprises: a gate electrode provided on the well region; and a gate insulating film interposed between the gate electrode and the top surface of the well region, and the constant current is independent from a gate voltage applied to the gate electrode.

3. The ternary inverter device of claim 2, wherein the source region of the NMOS transistor device is electrically connected to the well region of the NMOS transistor device and has a same voltage as the well region of the NMOS transistor device, and the source region of the PMOS transistor device is electrically connected to the well region of the PMOS transistor device, and a same voltage as the well region of the PMOS transistor device.

4. The ternary inverter device of claim 1, wherein, in each of the NMOS transistor device and the PMOS transistor device, the well region and the pair of constant current generating patterns have conductivity types identical to each other, and a doping concentration of each of the pair of constant current generating patterns is greater than a doping concentration of the well region.

5. The ternary inverter device of claim 4, wherein, in each of the NMOS transistor device and the PMOS transistor device, the doping concentration of each of the pair of constant current generating patterns is 310.sup.18 cm.sup.3 or greater.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram of a transistor device according to example embodiments.

(2) FIG. 2 shows gate voltage-drain current graphs of NMOS transistor devices of the present disclosure and conventional NMOS transistor devices.

(3) FIG. 3 shows gate voltage-drain current graphs of PMOS transistor devices of the present disclosure and conventional PMOS transistor devices.

(4) FIG. 4 is a diagram for describing a method of manufacturing the transistor device of FIG. 1.

(5) FIG. 5 is a diagram for describing a method of manufacturing the transistor device of FIG. 1.

(6) FIG. 6 is a diagram for describing a method of manufacturing the transistor device of FIG. 1.

(7) FIG. 7 is a diagram for describing a method of manufacturing the transistor device of FIG. 1.

(8) FIG. 8 is a diagram of a ternary inverter device according to example embodiments.

(9) FIG. 9 is a circuit diagram of the ternary inverter device of FIG. 8.

(10) FIG. 10 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8.

(11) FIG. 11 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8.

(12) FIG. 12 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8.

(13) FIG. 13 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8.

(14) FIG. 14 shows gate voltage-drain current graphs of ternary inverter devices of the present disclosure and binary inverter devices.

(15) FIG. 15 shows an input voltage Vin-output voltage Vout graph of the ternary inverter device of the present disclosure and a binary inverter device.

MODE OF DISCLOSURE

(16) Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals refer to like elements, and sizes of elements in the drawings may be exaggerated for clarity and convenience of description. Meanwhile, the following embodiments are merely illustrative, and various modifications may be made from these embodiments.

(17) Hereinafter, an expression above or on used herein may include not only immediately on in a contact manner but also on in a non-contact manner.

(18) An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In addition, when an element includes an element, unless there is a particular description contrary thereto, the element may further include other elements, not excluding the other elements.

(19) Also, the terms described in the specification, such as . . . er (or), . . . unit, etc., denote a unit that performs at least one function or operation, which may be implemented as hardware or software or a combination thereof.

(20) FIG. 1 is a diagram of a transistor device according to example embodiments.

(21) Referring to FIG. 1, a transistor device 10 may be provided. The transistor device 10 may include a substrate 100, a well region 110, a pair of device isolation regions 120, a pair of source/drain regions SD, a pair of constant current generating patterns 400, a gate electrode 210, a gate insulating film 220, and a pair of spacers 300.

(22) The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. The substrate 100 may be an intrinsic semiconductor substrate.

(23) The well region 110 may be provided in the substrate 100. The well region 110 may have a first conductivity type. For example, the first conductivity type may be n-type or p-type. In the case where the conductivity type of the well region 110 is n-type, the well region 110 may include a group V element (e.g., P, As) as an impurity. In the case where the conductivity type of the well region 110 is p-type, the well region 110 may include a group III element (e.g., B, In) as an impurity.

(24) The pair of device isolation regions 120 spaced apart from each other in a first direction DR1 parallel to the top surface of the substrate 100 may be provided on the well region 110. The pair of device isolation regions 120 may extend in a second direction DR2 perpendicular to the top surface of the substrate 100. The pair of device isolation regions 120 may include an insulating material. For example, the pair of device isolation regions 120 may include silicon oxide (e.g., SiO.sub.2).

(25) The pair of source/drain regions SD spaced apart from each other in the first direction DR1 may be provided on the well region 110. One of the pair of source/drain regions SD may be a source of the transistor device. The other one of the pair of source/drain regions SD may be a drain of the transistor device. The pair of source/drain regions SD may have a second conductivity type different from the first conductivity type. In the case where the first conductivity type is n-type, the second conductivity type may be p-type. In the case where the conductivity type of the pair of source/drain regions SD is p-type, the pair of source/drain regions SD may include a group III element (e.g., B, In) as an impurity. In the case where the first conductivity type is p-type, the second conductivity type may be n-type. In the case where the conductivity type of the pair of source/drain regions SD is n-type, the pair of source/drain regions SD may include a group V element (e.g., P, As) as an impurity.

(26) The pair of constant current generating patterns 400 may be provided on the well region 110. The pair of constant current generating patterns 400 may be spaced apart from each other in the first direction DR1. The pair of constant current generating patterns 400 may be provided between the pair of source/drain regions SD. The pair of constant current generating patterns 400 may be electrically connected to the pair of source/drain regions SD, respectively. For example, the pair of constant current generating patterns 400 may directly contact lower portions of the pair of source/drain regions SD, respectively. The pair of constant current generating patterns 400 may overlap the lower portions of the pair of source/drain regions SD in the first direction DR1. The pair of constant current generating patterns 400 may be formed under a channel (not shown) of the transistor device 10. For example, the constant current generating patterns 400 may be provided between a bottom surface of the channel and bottom surfaces of the source/drain regions SD. The channel may be formed between the pair of constant current generating patterns 400 and the top surface of the substrate 100 when the transistor device 10 has an on state.

(27) The pair of constant current generating patterns 400 may have the first conductivity type. In the case where the conductivity type of the pair of constant current generating patterns 400 is n-type, the pair of constant current generating patterns 400 may include a group V element (e.g., P, As) as an impurity. In the case where the conductivity type of the pair of constant current generating patterns 400 is p-type, the pair of constant current generating patterns 400 may include a group III element (e.g., B, In) as an impurity. The doping concentration of each of the pair of constant current generating patterns 400 may be greater than the doping concentration of the well region 110. The doping concentration of each of the pair of constant current generating patterns 400 may be less than the doping concentration of each of the pair of source/drain regions SD. For example, the doping concentration of each of the pair of constant current generating patterns 400 may be 310.sup.18 cm.sup.3 or greater. An electric field may be formed between the constant current generating pattern 400 and the source/drain region SD that are immediately adjacent to each other. For example, the intensity of the electric field may be 10.sup.6 V/cm or greater.

(28) By the pair of constant current generating patterns 400, a constant current may be generated between the source/drain region SD, which is the drain of the transistor device, among the pair of source/drain regions SD, and the well region 110. The constant current may be a band-to-band tunneling (BTBT) current flowing between the source/drain region SD, which is the drain, and the constant current generating pattern 400 immediately adjacent thereto. The constant current may be independent from a gate voltage applied to the gate electrode 210. That is, the constant current may flow regardless of the gate voltage. In the case where the transistor device 10 is an NMOS transistor device, the constant current may flow from the source/drain region SD, which is the drain, to the well region 110 via the constant current generating pattern 400 immediately adjacent thereto. In the case where the transistor device 10 is a PMOS transistor device, the constant current may flow from the well region 110 to the source/drain region SD, which is the drain, via the constant current generating patterns 400 immediately adjacent thereto.

(29) The gate electrode 210 may be provided above the well region 110. The gate electrode 210 may include an electrically conductive material. For example, the gate electrode may include a metal (e.g., Cu) or doped polysilicon (doped-poly Si).

(30) The gate insulating film 220 may be provided between the gate electrode 210 and the top surface of the substrate 100. The gate insulating film 220 may electrically insulate the gate electrode 210 and the well region 110 from each other. The gate insulating film 220 may separate the gate electrode 210 and the substrate 100 from each other. The gate insulating film 220 may include an electrically insulating material. For example, the gate insulating film 220 may include SiO.sub.2 or a high-k dielectric material (e.g., SiON, HfO.sub.2, ZrO.sub.2).

(31) The pair of spacers 300 may be provided on both sidewalls of the gate electrode 210, respectively. The pair of spacers 300 may extend onto both sidewalls of the gate insulating film 220, respectively. The pair of spacers 300 may include an electrically insulating material. For example, the pair of spacers 300 may include SiO.sub.2 or a high-k dielectric material (e.g., SiON, HfO.sub.2, ZrO.sub.2).

(32) In example embodiments, a pair of lightly doped regions (not shown) may be provided on the pair of source/drain regions SD in the well region 110. The pair of lightly doped regions may be arranged between the pair of source/drain regions SD and the pair of spacers 300 immediately adjacent thereto, respectively. The pair of lightly doped regions may extend in the first direction DR1 to contact the pair of device isolation regions 120, respectively. The pair of lightly doped regions may have the second conductivity type. The doping concentration of the pair of lightly doped regions may be lower than the doping concentration of the pair of source/drain regions SD. The pair of lightly doped regions may reduce the occurrence of a short-channel effect and a hot-carrier effect. Accordingly, the electrical characteristics of the transistor device 10 may be improved.

(33) The present disclosure may provide the transistor device 10 in which a constant current flows between the source/drain region SD, which the drain, and the well region 110.

(34) FIG. 3 shows gate voltage-drain current graphs of PMOS transistor devices of the present disclosure and conventional PMOS transistor devices.

(35) Referring to FIG. 3, gate voltage-drain current graphs RGR1 and RGR2 of the conventional PMOS transistor devices, and gate voltage-drain current graphs RGR3, RGR4, and RGR5 of the PMOS transistor devices according to the present disclosure are illustrated.

(36) Drain currents of the conventional PMOS transistor devices did not have a constant current component flowing regardless of a gate voltage.

(37) Drain currents of the PMOS transistor devices of the present disclosure had a constant current component flowing regardless of a gate voltage. For example, even when the PMOS transistor devices of the present disclosure had an off state, a constant current flowed through the PMOS transistor devices of the present disclosure.

(38) FIG. 4 is a diagram for describing a method of manufacturing the transistor device of FIG. 1. FIG. 5 is a diagram for describing a method of manufacturing the transistor device of FIG. 1. FIG. 6 is a diagram for describing a method of manufacturing the transistor device of FIG. 1. FIG. 7 is a diagram for describing a method of manufacturing the transistor device of FIG. 1. For brevity of description, substantially the same descriptions as provided with reference to FIG. 1 may not be provided.

(39) Referring to FIG. 4, the substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. The substrate 100 may be an intrinsic semiconductor substrate.

(40) The pair of device isolation regions 120 may be formed in the substrate 100. A process of forming the pair of device isolation regions 120 may include forming a pair of recess regions by recessing the substrate 100 to a certain depth, and filling the pair of recess regions with an electrically insulating material. For example, the pair of recess regions may be formed by performing an anisotropic etching process on the substrate 100. For example, the electrically insulating material may be provided to the pair of recess regions by a chemical vapor deposition process or a physical vapor deposition process.

(41) The well region 110 may be formed between the pair of device isolation regions 120. The well region 110 may be formed by performing a process of doping the substrate 100 to a certain depth. For example, the doping process may include a diffusion process and/or an ion implantation process. In the case where an upper portion of the substrate 100 is doped with a group V element (e.g., P, As), the conductivity type of the well region 110 may be n-type. In the case where the upper portion of the substrate 100 is doped with a group III element (e.g., B, In), the conductivity type of the well region 110 may be p-type.

(42) Referring to FIG. 5, the gate electrode 210 and the gate insulating film 220 may be formed above the substrate 100. Forming of the gate electrode 210 and the gate insulating film 220 may include performing a process of sequentially depositing an insulating material (e.g., SiO.sub.2, SiON, HfO.sub.2, ZrO.sub.2) and a conductive material (e.g., a metal or doped polysilicon) on the substrate 100, and a process of patterning a deposited layer formed by the deposition process. For example, the deposition process may include a chemical vapor deposition process or a physical vapor deposition process. For example, the patterning process may include forming a mask pattern on the deposited layer, and performing an anisotropic etching process using the mask pattern on the deposited layer as an etch mask. The mask pattern may be removed during the anisotropic etching process or after the anisotropic etching process is completed. Referring to FIG. 6, the pair of constant current generating patterns 400 may be formed on the well region 110. For example, the pair of constant current generating patterns 400 may be formed to be deeper than the channel of the transistor device 10 (FIG. 1) described with reference to FIG. 1, but to be shallower than bottom surfaces of the pair of source/drain regions SD (FIG. 1). Forming of the pair of constant current generating patterns 400 may include performing an ion implantation (IP) process. For example, the pair of constant current generating patterns 400 may be a halo-doped region formed by the ion implantation (IP) process. The pair of constant current generating patterns 400 may have the same conductivity type as the well region 110. In the case where the conductivity type of the well region 110 is n-type, a group V element (e.g., P, As) may be further implanted into an upper portion of the well region 110 to form the pair of n-type constant current generating patterns 400. In the case where the conductivity type of the well region 110 is p-type, a group III element (e.g., B, In) may be further implanted into the upper portion of the well region 110 to form the pair of p-type constant current generating patterns 400.

(43) After an impurity is implanted into the upper portion of the well region 110, the well region 110 may be heat-treated. A thermal budget of a heat treatment process may affect a threshold voltage characteristic and a constant current of the transistor device 10 (FIG. 1). For example, in the case where the thermal budget is greater than that required, the impurity implanted into the upper portion of the well region 110 may be diffused into the channel and thus change a threshold voltage. For example, in the case where the thermal budget is greater than that required, the doping concentration between the pair of source/drain regions SD and the pair of constant current generating patterns 400 may be gradually changed, and thus the magnitude of the constant current may be decreased. When performing the heat treatment process, the thermal budget may be adjusted such that the threshold voltage characteristic of the transistor device 10 (FIG. 1) is not changed or is minimally changed, and the transistor device 10 (FIG. 1) has a required constant current.

(44) Referring to FIG. 7, the pair of spacers 300 may be formed on sidewalls of the gate electrode 210 and the gate insulating film 220, respectively. Forming of the pair of spacers 300 may include forming an insulating film on the substrate 100, the gate electrode 210, and the gate insulating film 220, and performing an anisotropic etching process on the insulating film. For example, the insulating film may be formed by conformally depositing an insulating material (e.g., SiO.sub.2) on the substrate 100, the gate electrode 210, and the gate insulating film 220.

(45) Referring again to FIG. 1, the pair of source/drain regions SD may be formed on the well region 110. Forming of the pair of source/drain regions SD may include performing a process of doping the well region 110 between the spacer 300 and the device isolation region 120 that are immediately adjacent to each other. For example, the doping process may include an ion implantation process. The pair of source/drain regions SD may be formed from the top surface of the substrate 100 to a certain depth. For example, the pair of source/drain regions SD may be formed from the top surface of the substrate 100 to a depth greater than the depth of the pair of constant current generating patterns 400. The pair of source/drain regions SD may have a conductivity type different from the conductivity type of the well region 110. In the case where the conductivity type of the well region 110 is n-type, a group III element (e.g., B, In) may be implanted into the well region 110 between the spacer 300 and the device isolation region 120, which are immediately adjacent to each other, to form the p-type source/drain region SD. In the case where the conductivity type of the well region 110 is p-type, a group V element (e.g., P, As) may be implanted into the well region 110 between the spacer 300 and the device isolation region 120, which are immediately adjacent to each other, to form the n-type source/drain region SD. The pair of source/drain regions SD may be formed such that the lower portions thereof overlap the pair of constant current generating patterns 400 in the first direction DR1. Accordingly, the transistor device 10 may be formed.

(46) In example embodiments, the pair of lightly doped regions (not shown) may be formed on the pair of source/drain regions SD in the well region 110, respectively. The pair of lightly doped regions may be formed from the top surface of the substrate 100 to a certain depth, and the pair of source/drain regions SD may be formed from the certain depth to a depth greater than the depth of the pair of constant current generating patterns 400. The pair of lightly doped regions may be formed by a doping process. For example, the doping process may include an ion implantation process. The pair of lightly doped regions may have been doped to have the same conductivity type as the pair of source/drain regions SD.

(47) FIG. 8 is a diagram of a ternary inverter device according to example embodiments. FIG. 9 is a circuit diagram of the ternary inverter device of FIG. 8. For brevity of description, substantially the same descriptions as provided with reference to FIG. 1 may not be provided.

(48) Referring to FIG. 8, a ternary inverter device 20 may be provided. The ternary inverter device 20 may include the substrate 100, a first well region 112, the device isolation regions 120, a pair of first source/drain regions SDa, a pair of first constant current generating patterns 402, a second well region 114, a pair of second source/drain regions SDb, a pair of second constant current generating patterns 404, the gate electrodes 210, gate insulating films 220, and the spacers 300. The substrate 100 may be substantially the same as that described with reference to FIG. 1.

(49) The device isolation regions 120 may be provided in the substrate 100. Each of the device isolation regions 120 may be substantially the same as each of the pair of device isolation regions 120 described with reference to FIG. 1. The device isolation regions 120 may be arranged in the first direction DR1 parallel to the top surface of the substrate 100. For example, the device isolation regions 120 may be arranged at substantially equal intervals.

(50) The first well region 112 and the second well region 114 may be provided in the substrate 100. The first well region 112 may be spaced apart from the second well region 114 in the first direction DR1. Each of the first well region 112 and the second well region 114 may be provided between the device isolation regions 120 that are immediately adjacent to each other. The conductivity type of the first well region 112 may be n-type. The first well region 112 may include a group V element (e.g., P, As) as an impurity. The conductivity type of the second well region 114 may be p-type. The second well region 114 may include a group III element (e.g., B, In) as an impurity.

(51) The pair of first source/drain regions SDa spaced apart from each other in the first direction DR1 may be provided on the first well region 112. The conductivity type of the pair of first source/drain regions SDa may be p-type. The pair of first source/drain regions SDa may include a group III element (e.g., B, In) as an impurity.

(52) The pair of second source/drain regions SDb spaced apart from each other in the first direction DR1 may be provided on the second well region 114. The conductivity type of the pair of second source/drain regions SDb may be n-type. The pair of second source/drain regions SDb may include a group V element (e.g., P, As) as an impurity.

(53) The pair of first constant current generating patterns 402 and the pair of second constant current generating patterns 404 may be provided in the first well region 112 and the second well region 114, respectively. The pair of first constant current generating patterns 402 may be provided between the pair of first source/drain regions SDa. For example, the pair of first constant current generating patterns 402 may overlap the first source/drain regions SDa in the first direction DR1. For example, the pair of first constant current generating patterns 402 may be provided between a bottom surface of a channel (not shown) that is formed between the first source/drain regions SDa, and bottom surfaces of the first source/drain regions SDa. The conductivity type of the pair of first constant current generating patterns 402 may be n-type. The pair of first constant current generating patterns 402 may include a group V element (e.g., P, As) as an impurity.

(54) The pair of second constant current generating patterns 404 may be provided between the pair of second source/drain regions SDb. For example, the pair of second constant current generating patterns SDb may overlap the second source/drain regions SDb in the first direction DR1. For example, the pair of second constant current generating patterns 404 may be provided between a bottom surface of a channel that is formed between the second source/drain regions SDb, and bottom surfaces of the second source/drain regions SDb. The conductivity type of the pair of second constant current generating patterns 404 may be p-type. The pair of second constant current generating patterns 404 may include a group III element (e.g., B, In) as an impurity.

(55) The gate electrodes 210 may be provided above the first well region 112 and the second well region 114, respectively. The gate insulating films 220 may be provided between the gate electrodes 210 and the top surface of the substrate 100, respectively. The spacers 300 may be provided on sidewalls of the gate electrodes 210, respectively.

(56) The first well region 112, the pair of first source/drain regions SDa, the pair of first constant current generating patterns 402, the gate electrode 210, the gate insulating film 220, and the spacers 300 provided on both sidewalls of the gate electrode 210 may define a PMOS transistor device. The second well region 114, the pair of first source/drain regions SDa, the pair of second constant current generating patterns 404, the gate electrode 210, the gate insulating film 220, and the spacers 300 provided on both sidewalls of the gate electrode 210 may define an NMOS transistor device.

(57) Referring to FIG. 9, a ground voltage may be applied to a source (one of the pair of second source/drain regions of FIG. 8) and a substrate (the second well region of FIG. 8) of the NMOS transistor device. For brevity of description, it is assumed that the ground voltage is 0 volt (V). A driving voltage V.sub.DD may be applied to a source (one of the pair of first source/drain regions of FIG. 8) and a substrate (the first well region of FIG. 8) of the PMOS transistor device. An input voltage Vin may be applied to each of a gate electrode (the gate electrode on the second well region of FIG. 8) of the NMOS transistor device and a gate electrode (the gate electrode on the first well region of FIG. 8) of the PMOS transistor device.

(58) A drain (the other one of the pair of second source/drain regions of FIG. 8) of the NMOS transistor device may be electrically connected to a drain (the other one of the pair of first source/drain regions of FIG. 8) of the PMOS transistor device such that they respectively have identical voltages. The voltages of the drain of the NMOS transistor device and the drain of the PMOS transistor device may be an output voltage Vout of the ternary inverter device 20.

(59) A constant current may flow from the drain to the substrate of the NMOS transistor device. A constant current may flow from the substrate to the drain of the PMOS transistor device. The constant currents may be independent from the input voltage Vin.

(60) In one example, a first input voltage may be applied to the gate electrode of the PMOS transistor device and the gate electrode of the NMOS transistor device, such that the PMOS transistor device has a constant current that is stronger than a channel current and the NMOS transistor device has a channel current that is stronger than a constant current. In this case, the output voltage Vout of the ternary inverter device 20 may be a first voltage.

(61) In another example, a second input voltage may be applied to the gate electrode of the PMOS transistor device and the gate electrode of the NMOS transistor device, such that the NMOS transistor device has a constant current that is stronger than a channel current and the PMOS transistor device has a channel current that is stronger than a constant current. In this case, the output voltage of the ternary inverter device 20 may be a second voltage greater than the first voltage.

(62) In another example, a third input voltage may be applied to the gate electrode of the PMOS transistor device and the gate electrode of the NMOS transistor device, such that each of the NMOS transistor device and the PMOS transistor device has a constant current that is stronger than a channel current. In this case, the output voltage of the ternary inverter device 20 may be a third voltage between the first voltage and the second voltage.

(63) The constant current flowing from the drain to the substrate of the NMOS transistor device and the constant current flowing from the substrate to the drain of the PMOS transistor device may flow regardless of the gate voltages applied to the gate electrodes of the PMOS transistor device and the NMOS transistor device. A current in the ternary inverter device 20 may flow from the substrate of the PMOS transistor device to the substrate of the NMOS transistor device via the drain of the PMOS transistor device and the drain of the NMOS transistor device. The driving voltage V.sub.DD may be divided by a resistance between the substrate of the PMOS transistor device and the drain of the PMOS transistor device, and a resistance between the substrate of the NMOS transistor device and the drain of the NMOS transistor device. The output voltage Vout may be a voltage to which the driving voltage V.sub.DD is dropped by the resistance between the substrate of the PMOS transistor device and the drain of the PMOS transistor device. Accordingly, the output voltage Vout may have a value between the driving voltage VDD and 0 V.

(64) The output voltage Vout may have the first voltage (State 0), the third voltage (State 1) greater than the first voltage, or the second voltage (State 2) greater than the third voltage, according to the input voltage Vin. The present disclosure may provide the ternary inverter device 20 having three states according to the input voltage Vin.

(65) In example embodiments, the lightly doped regions (not shown) may be provided on the pair of first source/drain regions SDa and the pair of second source/drain regions SDb. For example, the lightly doped regions may be respectively arranged between the pair of first source/drain regions SDa and the spacers 300 immediately adjacent thereto, and between the pair of second source/drain regions SDb and the spacers 300 immediately adjacent thereto. Each of the lightly doped regions may extend in the first direction DR1 to contact the device isolation regions 120.

(66) The conductivity type of the lightly doped regions on the pair of first source/drain regions SDa may be n-type. The doping concentration of the lightly doped regions on the pair of first source/drain regions SDa may be less than the doping concentration of the pair of first source/drain regions SDa.

(67) The conductivity type of the lightly doped regions on the pair of second source/drain regions SDb may be p-type. The doping concentration of the lightly doped regions on the pair of second source/drain regions SDb may be less than the doping concentration of the pair of second source/drain regions SDb.

(68) The lightly doped regions may reduce the occurrence of a short-channel effect and a hot-carrier effect. Accordingly, the electrical characteristics of the ternary inverter device 20 may be improved.

(69) FIG. 10 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8. FIG. 11 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8. FIG. 12 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8. FIG. 13 is a diagram for describing a method of manufacturing the ternary inverter device of FIG. 8. For brevity of description, substantially the same descriptions as provided with reference to FIGS. 4 to 7 and FIG. 8 may not be provided.

(70) Referring to FIG. 10, the device isolation regions 120 may be formed in the substrate 100. A process of forming the device isolation regions 120 may be substantially the same as the process of forming the pair of device isolation regions 120 described with reference to FIG. 4.

(71) The first well region 112 may be formed between a pair of device isolation regions 120 that are directly adjacent to each other, among the device isolation regions 120. The first well region 112 may be formed by a process of doping the substrate 100 with a group V element (e.g., P, As). The conductivity type of the first well region 112 may be n-type.

(72) The second well region 114 may be formed between another pair of device isolation regions 120 that are directly adjacent to each other, among the device isolation regions 120. The second well region 114 may be formed by a process of doping the substrate 100 with a group III element (e.g., B, In). The conductivity type of the second well region 114 may be p-type.

(73) Referring to FIG. 11, the gate electrode 210 and the gate insulating film 220 may be formed on each of the first well region 112 and the second well region 114. Forming of the gate electrode 210 and the gate insulation layer 220 may be substantially the same as that described with reference to FIG. 5.

(74) Referring to FIG. 12, the pair of first constant current generating patterns 402 may be formed on the first well region 112. For example, the pair of first constant current generating patterns 402 may be provided between the bottom surface of the channel (not shown) that is formed between the first source/drain regions SDa (FIG. 8) as described above with reference to FIG. 8, and the bottom surfaces of the first source/drain regions SDa (FIG. 8). Forming of the pair of first constant current generating patterns 402 may include a process of implanting a group V element (e.g., P, As) into an upper portion of the first well region 112. For example, the pair of first constant current generating patterns 402 may be halo-doped regions formed by the ion implantation (IP) process. The conductivity type of the pair of first constant current generating patterns 402 may be n-type.

(75) The pair of second constant current generating patterns 404 may be formed on the second well region 114. For example, the pair of second constant current generating patterns 404 may be provided between the bottom surface of the channel (not shown) that is formed between the second source/drain regions SDb (FIG. 8) as described above with reference to FIG. 8, and the bottom surfaces of the second source/drain regions SDb (FIG. 8). Forming of the pair of second constant current generating patterns 404 may include a process of implanting a group III element (e.g., B, In) into an upper portion of the second well region 114. For example, the pair of second constant current generating patterns 404 may be halo-doped (IP) regions formed by an ion implantation process. The conductivity type of the pair of second constant current generating patterns 404 may be p-type.

(76) After impurities are implanted into the first and second well regions 112 and 114, the first and second well regions 112 and 114 may be heat-treated. A thermal budget of the heat treatment process may affect threshold voltage characteristics and constant currents of the transistor devices in the ternary inverter device 20 (FIG. 8). For example, in the case where the thermal budget is greater than that required, the impurities implanted into the upper portions of the first and second well regions 112 and 114 may be diffused into the channels and thus change threshold voltages. For example, in the case where the thermal budget is greater than that required, the doping concentration between the pair of first source/drain regions SDa and the pair of first constant current generating patterns 402 and between the pair of second source/drain regions SDb and the second constant current generating patterns 404 may be gradually changed, and thus the magnitude of the constant currents may be decreased. When performing the heat treatment process, the thermal budget may be adjusted such that the threshold voltage characteristic of the ternary inverter device 20 (FIG. 8) is not changed or is minimally changed, and the ternary inverter device 20 (FIG. 8) has a required constant current.

(77) Referring to FIG. 13, the pair of spacers 300 may be formed. Forming of the pair of spacers 300 may be substantially the same as that described with reference to FIG. 7.

(78) Referring again to FIG. 8, the pair of first source/drain regions SDa may be formed on the first well region 112. Forming of each of the pair of first source/drain regions SDa may include a process of implanting a group III element (e.g., B, In) into the first well region 112 between the spacer 300 and the device isolation region 120 immediately adjacent to each other. The conductivity type of the first source/drain regions SDa may be p-type.

(79) The pair of second source/drain regions SDb may be formed on the second well region 114. Forming of each of the pair of second source/drain regions SDb may include a process of implanting a group V element (e.g., P, As) into the second well region 114 between the spacer 300 and the device isolation region 120 that are directly adjacent to each other. The conductivity type of the second source/drain regions SDb may be n-type.

(80) Accordingly, the ternary inverter device 20 may be provided.

(81) In example embodiments, the lightly doped regions (not shown) may be formed on the pair of first source/drain regions SDa and the pair of second source/drain regions SDb, respectively. The lightly doped regions may be formed from the top surface of the substrate 100 to a certain depth, and the pair of first source/drain regions SDa and the pair of second source/drain regions SDb may be formed from the certain depth to a depth greater than the depth of the pair of first constant current generating patterns 402 and the pair of second constant current generating patterns 404. The lightly doped regions may be formed by a doping process. For example, the doping process may include an ion implantation process. The conductivity type of the lightly doped regions on the pair of first source/drain regions SDa may be the same as that of the pair of first source/drain regions SDa. The conductivity type of the lightly doped regions on the pair of second source/drain regions SDb may be the same as that of the pair of second source/drain regions SDb.

(82) FIG. 14 shows gate voltage-drain current graphs of ternary inverter devices of the present disclosure and binary inverter devices.

(83) Referring to FIG. 14, gate voltage-drain current graphs IGR1 and IGR2 of the binary inverter devices and gate voltage-drain current graphs IGR3, IGR4, and IGR5 of the ternary inverter devices of the present disclosure are illustrated.

(84) Drain currents of the binary inverter devices did not have a constant current component flowing regardless of a gate voltage.

(85) Drain currents of the ternary inverter devices of the present disclosure had a constant current component flowing regardless of a gate voltage. For example, even when the ternary inverter devices of the present disclosure had an off state, a constant current flowed through the ternary inverter devices of the present disclosure.

(86) FIG. 15 shows an input voltage Vin-output voltage Vout graph of the ternary inverter device of the present disclosure and a binary inverter device.

(87) Referring to FIG. 15, the driving voltages V.sub.DD of the ternary inverter device 20 and the binary inverter device were 1.0 V, and a ground voltage GND was 0 V. The input voltages Vin of the ternary inverter device 20 and the binary inverter device were 0 V to 1.0 V.

(88) In the case of the binary inverter device, when the input voltage was changed from 0 V to 1 V, the output voltage Vout rapidly decreased from 1 V to 0 V in the vicinity of an input voltage of 0.5 V. That is, the binary inverter device has two states (e.g., State 0 and State 1).

(89) In the case of the ternary inverter device of the present disclosure, when the input voltage was changed from 0 V to 1 V, the output voltage Vout rapidly decreased from 1 V to 0.5 V, then plateaued at 0.5 V, and then rapidly decreased from 0.5 V to 0 V once more. That is, the ternary inverter device of the present disclosure has three states (e.g., State 0, State 1, and State 2).

(90) The above description of the embodiments of the spirit of the present disclosure provides examples for the description of the spirit of the present disclosure. Therefore, the spirit of the present disclosure is not limited to the above embodiments, and it is apparent that various modifications and changes may be made by one of ordinary skill in the art, within the spirit of the present disclosure, for example, by combining the above embodiments.