Semiconductor device

Abstract

A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.

Claims

1. A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type provided in a semiconductor base containing silicon carbide; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at the front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at the front surface side thereof, and having a plurality of second portions extending parallel to the plurality of first portions; a plurality of gate electrodes respectively provided in the plurality of first trenches; and a diode electrode provided in the second trench, wherein the diode electrode includes: a plurality of inner electrodes provided in the plurality of second portions, and an outer electrode connecting the plurality of inner electrodes and surrounding ends of the first portions in a plan view of the silicon carbide semiconductor device, and in the first direction, the second portions is spaced apart from the ends of the first portions by a predetermined distance.

2. The silicon carbide semiconductor device according to claim 1, wherein the predetermined distance is no smaller than an interval between one of the first portions and an adjacent one of the second portions in a second direction perpendicular to the first direction.

3. The silicon carbide semiconductor device according to claim 1, wherein the plurality of gate electrodes is formed by polysilicon embedded in the first trenches.

4. The silicon carbide semiconductor device according to claim 1, wherein the diode electrode is formed by a polysilicon and a metal film embedded in the second trench.

5. The silicon carbide semiconductor device according to claim 1, wherein the second trench has a plurality of semiconductor regions exposed at inner walls thereof, which form Schottky barrier junctions with the diode electrode.

6. The silicon carbide semiconductor device according to claim 1, further comprising a plurality of source regions of the first conductivity type selectively provided in the base layer and in contact with the first trenches and the second trench.

7. The silicon carbide semiconductor device according to claim 1, further comprising: an active region through which a main current passes; and an edge region that surrounds a periphery of the active region in the plan view of the silicon carbide semiconductor device.

8. The silicon carbide semiconductor device according to claim 7, wherein the edge region has a junction termination extension (JTE) region provided therein.

9. The silicon carbide semiconductor device according to claim 8, wherein the ends of the first portions are provided further inward than is the JTE region in the plan view of the silicon carbide semiconductor device.

10. The silicon carbide semiconductor device according to claim 7, wherein the active region and the edge region have a connecting region provided therebetween.

11. The silicon carbide semiconductor device according to claim 10, further comprising a gate insulating film provided between the first trenches and the gate electrodes, wherein in the connecting region, side surfaces of the first trenches are covered by a semiconductor region of the second conductivity type.

12. The silicon carbide semiconductor device according to claim 10, wherein in the connecting region, side surfaces of the second trench are in contact with a semiconductor region of the first conductivity type.

13. The silicon carbide semiconductor device according to claim 1, further comprising: a first region of the second conductivity type selectively provided to be in contact with a bottom of at least one of the second trench and the first trenches; and a second region of the second conductivity type provided immediately beneath the outer electrode, wherein the first region and the second region are separated from each other in the first direction.

14. The silicon carbide semiconductor device according to claim 10, further comprising an interlayer insulating film provided in the semiconductor base at the front surface side thereof, and covering the gate electrodes, wherein the interlayer insulating film has openings in the connecting region.

15. The silicon carbide semiconductor device according to claim 14, further comprising a gate contact region formed by a polysilicon layer provided in the openings.

16. The silicon carbide semiconductor device according to claim 15, wherein a portion of the second trench is provided at a position facing the gate contact region in a depth direction.

17. The silicon carbide semiconductor device according to claim 15, wherein the outer electrode is provided at a position facing the gate contact region in a depth direction.

18. The silicon carbide semiconductor device according to claim 15, further comprising a gate runner connected to the gate contact region.

19. The silicon carbide semiconductor device according to claim 1, wherein the first portions and the second portions are disposed alternately.

20. A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type provided in a semiconductor base containing silicon carbide; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the plurality of first portions; a plurality of gate electrodes respectively provided in the plurality of first trenches; and a diode electrode provided in the second trench, wherein the diode electrode includes: a plurality of inner electrodes provided in the plurality of second portions, and an outer electrode connecting the plurality of inner electrodes and surrounding ends of the first portions in a plan view of the silicon carbide semiconductor device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a top view depicting a structure of a silicon carbide semiconductor device according to an embodiment.

(2) FIG. 2 is a cross-sectional view of a portion along A-A in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment.

(3) FIG. 3 is a cross-sectional view of a portion along B-B in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment.

(4) FIG. 4 is a cross-sectional view of a portion along C-C in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment.

(5) FIG. 5 is a cross-sectional view of a portion along D-D in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment.

(6) FIG. 6 is a top view depicting an appearance of the silicon carbide semiconductor device according to the embodiment.

(7) FIG. 7 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 1).

(8) FIG. 8 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 2).

(9) FIG. 9 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 3).

(10) FIG. 10 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 4).

(11) FIG. 11 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 5).

(12) FIG. 12 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 1).

(13) FIG. 13 is a cross-sectional view of a portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 1).

(14) FIG. 14 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 2).

(15) FIG. 15 is a cross-sectional view of the portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 2).

(16) FIG. 16 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 3).

(17) FIG. 17 is a cross-sectional view of the portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 3).

(18) FIG. 18 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 4).

(19) FIG. 19 is a cross-sectional view of the portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 4).

(20) FIG. 20 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 5).

(21) FIG. 21 is a cross-sectional view of the portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 5).

(22) FIG. 22 is a top view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 6).

(23) FIG. 23 is a cross-sectional view of the portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture (part 6).

(24) FIG. 24 is a top view depicting a structure of a conventional built-in SBD silicon carbide semiconductor device.

(25) FIG. 25 is a cross-sectional view of a portion along C-C in FIG. 24 depicting the structure of the conventional built-in SBD silicon carbide semiconductor device.

(26) FIG. 26 is a cross-sectional view of a portion along A-A in FIG. 24 depicting the structure of the conventional built-in SBD silicon carbide semiconductor device.

(27) FIG. 27 is a cross-sectional view of a portion along B-B in FIG. 24 depicting the structure of the conventional built-in SBD silicon carbide semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

(28) Problems to be addressed are discussed. FIG. 26 is a cross-sectional view of a portion along A-A in FIG. 24 depicting the structure of the conventional built-in SBD silicon carbide semiconductor device. Further, FIG. 27 is a cross-sectional view of a portion along B-B in FIG. 24 depicting the structure of the conventional built-in SBD silicon carbide semiconductor device. As depicted in FIG. 26 and FIG. 27, in the connecting region 141, the second p.sup.+-type region 104 is provided on the first p.sup.+-type region 103. Further, in a surface layer of the p-type base layer 116, the p.sup.++-type contact regions 118 that are in contact with the trench SBDs 132 are provided. Therefore, in the connecting region 141, the trench SBDs 132 have a structure in which peripheries thereof are surrounded by p-type regions (the p-type base layer 116, the p.sup.++-type contact regions 118, the first p.sup.+-type region 103, and the second p.sup.+-type region 104).

(29) As a result, in the connecting region 141, the trench SBDs 132 do not function as a parasitic Schottky diode and bipolar operation of the parasitic pn diode cannot be inhibited. In an instance in which the parasitic pn diode turns on and conducts, due to the bipolar operation of the parasitic pn diode, hole current flows as indicated by a path D in FIG. 26 and FIG. 27, stacking faults are generated and expand due to energy generated by recombination by the hole current and electron current.

(30) Therefore, the connecting region 141 has a problem in that characteristics change over time (degrade over time) to a greater extent than in the active region 140 due to the bipolar operation of the parasitic pn diode while increases in forward degradation and turn-on loss occur.

(31) One object of the present invention is to provide a semiconductor device of which capability does not drop during freewheeling.

(32) Embodiments of a semiconductor device according to the present invention is described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or . In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described. Further, in the present description, when Miller indices are described, means a bar added to an index immediately after the , and a negative index is expressed by prefixing to the index.

(33) A semiconductor device according to the present invention is configured using a semiconductor having a band gap that is wider than that of silicon (hereinafter, wide band gap semiconductor). Herein, a structure of a semiconductor device (silicon carbide semiconductor device) in which, for example, silicon carbide (SiC) is used as a wide band gap semiconductor is described as an example. FIG. 1 is a top view depicting a structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of a portion along A-A in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view of a portion along B-B in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view of a portion along C-C in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment. Here, FIG. 5 is a cross-sectional view of a portion along D-D in FIG. 1 depicting the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view of the portion along C-C in a connecting region 41 and FIG. 5 is a cross-sectional view of the portion along D-D in an active region through which a main current flows in a thickness direction of the substrate when an element structure is formed and is in an on-state.

(34) As depicted in FIG. 1, a built-in SBD silicon carbide semiconductor device 50 is configured by an active region 40 in which a device element structure is formed and through which a main current passes in the thickness direction of the substrate during an on-state, an edge region 42 that surrounds a periphery of the active region 40 and sustains a breakdown voltage, and the connecting region 41 between the active region 40 and the edge region 42. The active region 40 is a region surrounded by a dotted and dashed line in FIG. 1. The connecting region 41, as depicted in FIG. 4, is a region that does not function as a MOS and in which side surfaces of later-described trench gates 31 are covered by p-type regions. The silicon carbide semiconductor device according to the embodiment depicted in FIGS. 1 to 4 is the built-in SBD silicon carbide semiconductor device 50 that includes MOS gates at a front surface (surface having a later-described p-type base layer 16) of a semiconductor base (silicon carbide base: semiconductor chip) containing silicon carbide.

(35) The silicon carbide base is formed by sequentially growing, epitaxially on an n.sup.+-type silicon carbide substrate (semiconductor substrate of a first conductivity type) 2 containing silicon carbide, silicon carbide layers constituting an n.sup.-type drift layer (first semiconductor layer of the first conductivity type) 1 and a p-type base layer (second semiconductor layer of a second conductivity type) 16. In the active region 40, the MOS gates are configured by the p-type base layer 16, n.sup.+-type source regions (first semiconductor regions of the first conductivity type) 17, a gate insulating film 19, and gate electrodes 20. In particular, in a surface layer of the n.sup.-type drift layer 1, the surface layer being on a source side (side facing a later-described source electrode 22), an n-type region 15 may be provided so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. The n-type region 15, for example, is provided uniformly in a direction parallel to a base front surface (the front surface of the silicon carbide base).

(36) In the n-type region 15 (in an instance in which the n-type region 15 is omitted, the n.sup.-type drift layer 1, hereinafter, simply (1)), first p.sup.+-type regions (second semiconductor regions of the second conductivity type) 3 are selectively provided. The first p.sup.+-type regions 3 are provided so as to be in contact with bottoms of the later-described trench gates (first trenches) 31 and a bottom of a later-described trench SBD (second trench) 32. Further, in the surface layer of the n-type region 15 (1), second p.sup.+-type regions (third semiconductor regions of the second conductivity type) 4 are selectively provided. The second p.sup.+-type regions 4 are provided so that bottoms thereof are in contact with the first p.sup.+-type regions 3.

(37) In an instance in which the n-type region 15 is provided, the first p.sup.+-type regions 3 are provided from a depth position closer to a drain than is an interface between the p-type base layer 16 and the n-type region 15 to a depth not reaching an interface between the n-type region 15 and the n.sup.-type drift layer 1. The first p.sup.+-type regions 3 are provided, whereby near the bottom of the trench SBD 32 and the bottoms of the trench gates 31, pn junctions between the first p.sup.+-type regions 3 and the n-type region 15 (1) may be formed. The first p.sup.+-type regions 3 and the second p.sup.+-type regions 4 have impurity concentrations higher than an impurity concentration of the p-type base layer 16.

(38) Further, the n.sup.+-type source regions 17 are selectively provided in the p-type base layer 16. The n.sup.+-type source regions 17 and p.sup.++-type contact regions (fifth semiconductor regions of the second conductivity type) (not depicted) may be selectively provided so as to be in contact with one another. In this instance, the p.sup.++-type contact regions may have a depth that is, for example, the same as that of the n.sup.+-type source regions 17 or deeper than that of the n.sup.+-type source regions 17.

(39) The trench gates 31 penetrate through the n.sup.+-type source regions 17 and the p-type base layer 16 from the base front surface and reach the n-type region 15 (1). In the trench gates 31, the gate insulating film 19 is provided along sidewalls of the trench gates 31 and on the gate insulating film 19, the gate electrodes 20 are provided. The gate electrodes 20 have ends facing a source and the ends may protrude outward from the base front surface. The gate electrodes 20 are electrically connected to a gate electrode pad (not depicted). An interlayer insulating film 21 is provided on the base front surface so as to cover the gate electrodes 20 embedded in the trench gates 31. The interlayer insulating film 21 has openings in the connecting region 41 and in the openings, the gate electrodes 20 are connected to a gate runner 27 via a gate contact region 26 of a polysilicon layer.

(40) The trench SBD 32 penetrates through the n.sup.+-type source regions 17 and the p-type base layer 16 from the base front surface and reaches the n-type region 15 (1). In the trench SBD 32, sidewalls of the trench SBD 32 are covered by a Schottky metal 29 connected to the source electrode 22 while semiconductor regions exposed at inner walls of the trench SBD 32 and the Schottky metal 29 form Schottky barrier junctions. Further, an oxide film, for example, silicon dioxide (SiO.sub.2) may be provided on the Schottky metal 29.

(41) As depicted in FIG. 1, in the embodiment, the trench SBD 32 surrounds the trench gates 31. As depicted in later-described FIG. 6, surrounding is a need to cross the trench SBD 32 to reach the edge region 42 from any point of the trench gates 31, in a plan view. For example, the trench gates 31 are provided to have a striped pattern in the plan view and the trench SBD 32 has linear portions P1 that are longer than the trench gates 31 and that are provided parallel to the trench gates 31, and an outer peripheral portion P2 that connects the linear portions. As a result, portions of the trench gates 31 in contact with the source electrode 22 are in a region surrounded by the trench SBD 32. Therefore, outside the region surrounded by the trench SBD 32, when a negative bias is applied to a drain side of the built-in SBD silicon carbide semiconductor device, bipolar operation of a parasitic pn diode is eliminated and forward degradation as well as increases in turn-on loss may be suppressed.

(42) Further, as depicted in FIG. 4, in the connecting region 41, the sidewalls of the trench SBD 32 are not in contact with the second p.sup.+-type regions 4. In other words, a portion of p-type regions (the first and the second p.sup.+-type regions 103, 104) embedded in a periphery of the trench SBDs 132 is opened in the conventional built-in SBD silicon carbide semiconductor device, whereby the trench SBD 32 of the embodiment is such that the sidewalls of the trench SBD 32 are in contact with the n-type region 15 (1). As a result, even in the connecting region 41, the trench SBD 32 may be caused to function as a parasitic Schottky diode. Therefore, when a negative bias is applied to the drain side of the built-in SBD silicon carbide semiconductor device, even in the connecting region 41, a parasitic Schottky diode is caused to operate, whereby bipolar operation of the parasitic pn diode may be inhibited and forward degradation as well as increases in turn-on loss may be suppressed.

(43) FIG. 6 is a top view depicting an appearance of the silicon carbide semiconductor device according to the embodiment. As depicted in FIG. 6, the trench gates 31 are provided in a striped pattern in a direction that is the crystal orientation <11-20> of an n.sup.+-type silicon carbide substrate 2. In the edge region 42, which surrounds a periphery of the active region 40 and sustains a breakdown voltage, a JTE region 43 is provided as a junction termination extension (JTE) structure for enhancing the overall breakdown voltage of the high-voltage semiconductor device by mitigating or distributing the electric field. Closer to a chip end than is the JTE region 43, an n.sup.+-type semiconductor region (not depicted) functioning as a channel stopper is provided.

(44) In the embodiment, preferably, a distance W1 between the outer peripheral portion P2 of the trench SBD 32 and ends T of the trench gates 31 may be at least equal to an interval W2 between the trench SBD 32 and each of the trench gates 31. When the distance W1 is shorter than the interval W2, resistance in a current path of the trench SBD 32 increases and capability may drop. Furthermore, preferably, the ends T of the trench gates 31 may be provided farther inward (closer to the active region 40) than is the JTE region 43. Therefore, the outer peripheral portion P2 of the trench SBD 32 is provided at a position facing the gate contact region 26 in a depth direction.

(45) The source electrode 22 is in contact with the n.sup.+-type source regions 17 via contact holes opened in the interlayer insulating film 21 and is electrically insulated from the gate electrodes 20 by the interlayer insulating film 21. In an instance in which the p.sup.++-type contact regions are provided, the source electrode 22 is further in contact with the p.sup.++-type contact regions. Between the source electrode 22 and the interlayer insulating film 21, for example, a barrier metal that prevents diffusion of metal atoms from the source electrode 22 to the gate electrodes 20 may be provided. On the source electrode 22, a source electrode pad (not depicted) is provided. On a back surface (back surface of the n.sup.+-type silicon carbide substrate 2 constituting an n.sup.+-type drain region) of the silicon carbide base, a drain electrode (not depicted) is provided.

(46) Next, a method of manufacturing the semiconductor device according to the embodiment is described. FIG. 7, FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are cross-sectional views depicting states of the silicon carbide semiconductor device according to the embodiment during manufacture. FIG. 12, FIG. 14, FIG. 16, FIG. 18, FIG. 20, and FIG. 22 are top views depicting states of the silicon carbide semiconductor device according to the embodiment during manufacture. Further, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 21, and FIG. 23 are cross-sectional views of a portion along A-A in FIG. 12 depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(47) First, the n.sup.+-type silicon carbide substrate 2 that constitutes the n.sup.+-type drain region is prepared. Next, on the front surface of the n.sup.+-type silicon carbide substrate 2, the n.sup.-type drift layer 1 described above is epitaxially grown. For example, conditions of the epitaxial growth for forming the n.sup.-type drift layer 1 may be set so that the impurity concentration of the n.sup.-type drift layer 1 becomes about 310.sup.15/cm.sup.3. The state up to here is depicted in FIG. 7.

(48) Next, on the n.sup.-type drift layer 1, a lower n-type region 15a (in an instance in which the n-type region 15 is not formed, an n-type layer having an impurity concentration about the same as that of the n.sup.-type drift layer 1, hereinafter, simply n-type layer) is epitaxially grown. For example, conditions of the epitaxial growth for forming the lower n-type region 15a may be set so that the impurity concentration of the lower n-type region 15a becomes about 110.sup.17/cm.sup.3. The lower n-type region 15a is a portion of the n-type region 15. Next, by photolithography and ion implantation of a p-type impurity, the first p.sup.+-type regions 3 are selectively formed in a surface layer of the lower n-type region 15a (the n-type layer). For example, a dose amount during the ion implantation for forming the first p.sup.+-type regions 3 may be set so that the impurity concentration becomes about 510.sup.18/cm.sup.3. The state up to here is depicted in FIG. 8.

(49) Next, on the lower n-type region 15a (the n-type layer) and the first p.sup.+-type regions 3, an upper n-type region 15b (n-type layer) is epitaxially grown. For example, conditions of the epitaxial growth for forming the upper n-type region 15b may be set so that the impurity concentration of becomes about the same as the impurity concentration of the lower n-type region 15a. The upper n-type region 15b is a portion of the n-type region 15 and the lower n-type region 15a and the upper n-type region 15b combined constitute the n-type region 15. Next, by photolithography and ion implantation of a p-type impurity, the second p.sup.+-type regions 4 are selectively formed in a surface layer of the upper n-type region 15b (the n-type layer). For example, a dose amount during the ion implantation for forming the second p.sup.+-type regions 4 may be set so that the impurity concentration becomes about the same as that of the first p.sup.+-type regions 3. A region that is a combination of one of the first p.sup.+-type regions 3 and one of the second p.sup.+-type regions 4 is referred to as the first, the second p.sup.+-type regions 3, 4. When the second p.sup.+-type regions 4 are formed, in the connecting region 41, the second p.sup.+-type regions 4 are formed so as to be apart from the sidewalls of the trench SBDs 32. The state up to here is depicted in FIG. 9.

(50) Next, the p-type base layer 16 is epitaxially grown on the upper n-type region 15b and the second p.sup.+-type regions 4. For example, conditions of the epitaxial growth for forming the p-type base layer 16 may be set so that the impurity concentration of the p-type base layer 16 becomes about 410.sup.17/cm.sup.3.

(51) Next, by photolithography and ion implantation of an n-type impurity, the n.sup.+-type source regions 17 are selectively formed in a surface layer of the p-type base layer 16. For example, a dose amount during the ion implantation for forming the n.sup.+-type source regions 17 may be set so that the impurity concentration becomes about 310.sup.20/cm.sup.3.

(52) Next, by photolithography and ion implantation of a p-type impurity, in the surface layer of the p-type base layer 16, the p.sup.++-type contact regions may be selectively formed so as to be in contact with the n.sup.+-type source regions 17. For example, a dose amount during the ion implantation for forming the p.sup.++-type contact regions may be set so that the impurity concentration becomes about 310.sup.20/cm.sup.3. The sequence in which the n.sup.+-type source regions 17 and the p.sup.++-type contact regions are formed may be interchanged. Next, by photolithography and ion implantation of a p-type impurity, the JTE region 43 is formed in the edge region 42. After all the ion implantations are completed, activation annealing is performed. The state up to here is depicted in FIG. 10.

(53) Next, by photolithography and etching, the trench gates 31 that penetrate through the n.sup.+-type source regions 17 and the p-type base layer 16 and reach the n-type region 15 (1) are formed. The bottoms of the trench gates 31 may reach the first p.sup.+-type regions 3 or may be positioned in the n-type region 15 (1), between the p-type base layer 16 and the first p.sup.+-type regions 3. Subsequently, a mask used to form the trench gates 31 is removed. Further, an oxide film is used as the mask during trench formation. Further, after the trench etching, isotropic etching for removing damage of the trench gates 31 and hydrogen annealing for rounding corners of openings of the trench gates 31 and the bottoms of the trench gates 31 may be performed. The isotropic etching or the hydrogen annealing alone may be performed. Further, the hydrogen annealing may be performed after the isotropic etching is performed.

(54) Next, by photolithography and etching, the trench SBD 32 that penetrates through the n.sup.+-type source regions 17 and the p-type base layer 16, and reaches the n-type region 15 (1) is formed. The bottom of the trench SBD 32 may reach the first p.sup.+-type regions 3 or may be positioned in the n-type region 15 (1), between the p-type base layer 16 and the first p.sup.+-type regions 3. Subsequently, a mask used to form the trench SBD 32 is removed. At this time, the distance W1 between the outer peripheral portion P2 of the trench SBD 32 and each of the ends T of the trench gates 31 is at least equal to the interval W2 between the trench SBD 32 and each of the trench gates 31, and ends of the trench gates 31 are formed so as to be closer to the active region 40 than is the JTE region 43. The state up to here is depicted in FIG. 11.

(55) Next, the gate insulating film 19 is formed along the front surface of the silicon carbide base and the inner walls of the trench gates 31. Next, along the inner walls of the trench SBD 32, a metal film is formed containing, for example, titanium (Ti). Next, for example, a heat treatment (annealing) is performed under a nitrogen (N.sub.2) atmosphere of a temperature that is at most about 500 degrees C., whereby the Schottky barrier junctions between the metal film and semiconductor regions are formed at the inner walls of the trench SBD 32.

(56) Next, a polysilicon is deposited so as to be embedded in the trench gates 31 and the trench SBD 32, the polysilicon further being etched, thereby leaving the polysilicon constituting the gate electrodes 20 in the trench gates 31 and leaving the polysilicon in the trench SBD 32. Here, etchback may be performed and the polysilicon may be etched so as to be left deeper than the base surface. In this manner, the polysilicon is embedded in the trench SBD 32, whereby the trench SBD 32 is formed by heterojunctions between the metal film and the polysilicon. A top view of the state up to here is shown in FIG. 12 while a cross-section along in A-A in FIG. 12 is shown in FIG. 13.

(57) Next, the interlayer insulating film 21 is formed on an entire area of the front surface of the silicon carbide base, so as to cover the gate electrodes 20. The interlayer insulating film 21 is formed by, for example, a non-doped silicate glass (NSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), High Temperature Oxide (HTO), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned and contact holes are formed, thereby exposing the n.sup.+-type source regions 17. In an instance in which the p.sup.++-type contact regions are formed, the n.sup.+-type source regions 17 and the p.sup.++-type contact regions are exposed. The trench gates 31 open the interlayer insulating film 21 only in the connecting region 41. A top view of the state up to here is shown in FIG. 14 while a cross-section along A-A in FIG. 12 of this state is shown in FIG. 15.

(58) Next, the barrier metal is formed so as to cover the interlayer insulating film 21 and is patterned, thereby again exposing the n.sup.+-type source regions 17 and the p.sup.++-type contact regions. Next, the source electrode 22 is formed so as to be in contact with the polysilicon embedded in the n.sup.+-type source regions 17 and the trench SBD 32. The source electrode 22 may be formed so as to cover the barrier metal or may be formed only in the contact holes.

(59) Next, a polysilicon (Poly-Si) is deposited on an entire area of the front surface of the silicon carbide base. A top view of the state up to here is shown in FIG. 16 while a cross-section along A-A in FIG. 12 of this state is shown in FIG. 17. Next, the polysilicon is patterned by etching and is left only in the gate runner direction, whereby the gate contact region 26 is formed. A top view of the state up to here is shown in FIG. 18 while a cross-section along A-A in FIG. 12 of this state is shown in FIG. 19. In this manner, the polysilicon deposition is divided into two sessions, an instance of embedding the polysilicon in the trench SBD 32 and an instance of forming the gate contact region 26, whereby the gate contact region 26 may be formed widely above the trench SBD 32.

(60) Next, the interlayer insulating film 25 is formed on an entire area of the front surface of the silicon carbide base. The interlayer insulating film 25 is formed by, for example, NSG, PSG, HTO, or a combination thereof. A top view of the state up to here is shown in FIG. 20 while a cross-section along A-A in FIG. 12 of this state is shown in FIG. 21. Next, the interlayer insulating film 25 is patterned, forming contact holes and thereby, exposing the gate contact region 26.

(61) Next, a source electrode pad 28 and the gate runner 27 are formed so as to be embedded in the contact holes. A portion of a metal layer deposited to form the source electrode pad 28 may constitute the gate electrode pad. A top view of the state up to here is shown in FIG. 22 while a cross-section along A-A in FIG. 12 of this state is shown in FIG. 23. On the back surface of the n.sup.+-type silicon carbide substrate 2, a metal film such as a nickel (Ni) film, a titanium (Ti) film, etc. is formed in a contact portion of the drain electrode using sputtering deposition or the like. The metal film may be a combination of stacked layers of Ni films and Ti films. Thereafter, annealing such as a rapid heat treatment (rapid thermal annealing (RTA)) is performed so as to convert the metal film into a silicide and thereby form an ohmic contact. Thereafter, for example, a thick film such as a stacked film sequentially containing a Ti film, a Ni film, and gold (Au) film is formed by electron beam (EB) deposition or the like, thereby forming the drain electrode.

(62) In the epitaxial growth and the ion implantations described above, as an n-type impurity (n-type dopant), for example, nitrogen (N), phosphorus (P) arsenic (As), antimony (Sb), etc. that are n-types with respect to silicon carbide may be used. As a p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc. that are p-types with respect to silicon carbide may be used. In this manner, the MOSFET depicted in FIG. 1 to FIG. 4 is completed.

(63) As described above, according to the embodiment, the trench SBD surrounds the trench gates. As a result, portions in contact with the source electrode of the trench gates are inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when negative bias is applied to the drain side of the built-in SBD silicon carbide semiconductor device, bipolar operation of a parasitic pn diode is eliminated, enabling forward degradation as well as increases in turn-on loss to be suppressed.

(64) In the foregoing, the present invention may be variously modified within a range not departing from the spirit of the invention and in the embodiments described above, for example, dimensions, impurity concentrations, etc. of parts may be variously set according to necessary specifications. Further, in the described embodiments, while a MOSFET is described as an example, without limitation hereto, application is further possible to various types of silicon carbide semiconductor devices that conduct and block current by gate-driven control based on a predetermined gate threshold. Gate-driven controlled silicon carbide semiconductor devices, for example, include insulated gate bipolar transistor (IGBTs) and the like. Further, in the embodiments described, while an instance in which silicon carbide is used as a wide band gap semiconductor is described as an example, a wide band gap semiconductor other than silicon carbide such as, for example, gallium nitride (GaN) is applicable. Further, in the embodiments, while the first conductivity type is assumed to be an n-type and the second conductivity type is assumed to be a p-type, the present invention is similarly implemented when the first conductivity type is a p-type and the second conductivity type is an n-type.

(65) According to the invention described above, the trench SBD (second trench) surrounds the trench gates (first trenches). As a result, portions in contact with the source electrode of the trench gates are inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when negative bias is applied to the drain side of the built-in SBD silicon carbide semiconductor device, bipolar operation of a parasitic pn diode is eliminated, enabling forward degradation to be suppressed as well as increases in turn-on loss to be suppressed.

(66) The semiconductor device according to the present invention achieves an effect in that forward voltage degradation and loss during turn-on may be reduced.

(67) As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power converting equipment, power source devices of various types of industrial machines, etc. and is particularly suitable for silicon carbide semiconductor devices having a trench gate structure.

REFERENCE CHARACTERS

(68) 1, 101 n.sup.-type drift layer 2, 102 n.sup.+-type silicon carbide substrate 3, 103 first p.sup.+-type region 4, 104 second p.sup.+-type region 5, 105 p.sup.+-type region 15, 115 n-type region 15a lower n-type region 15b upper n-type region 16, 116 p-type base layer 17, 117 n.sup.+-type source region 18, 118 p.sup.++-type contact region 19, 119 gate insulating film 20, 120 gate electrode 21, 121 interlayer insulating film 22, 122 source electrode 25 interlayer insulating film 26 gate contact region 27 gate runner 28 source electrode pad 29, 129 Schottky metal 31, 131 trench gate 32, 132 trench SBDs 40, 140 active region 41, 141 connecting region 42, 142 edge region 43 JTE region 50, 150 built-in SBD silicon carbide semiconductor device