FILTER CIRCUITRY AND CIRCUITRY COMPRISING THE SAME

Abstract

Polyphase filter circuitry including: an input node to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and a common-source amplifier circuit. The common-source amplifier circuit includes a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance R.sub.M1 at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PFF are define the frequency response of the common-source amplifier circuit so that, based on the input signal V.sub.IN, a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD and a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.

Claims

1. Polyphase filter circuitry, comprising: an input node configured to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and a common-source amplifier circuit, wherein: the common-source amplifier circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PFF are configured to define the frequency response of the common-source amplifier circuit so that, based on the input signal V.sub.IN, a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD and a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.

2. The polyphase filter circuitry of claim 1, further comprising a source-follower circuit, wherein: the source-follower circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PPF connected to its source terminal; for the source-follower circuit, the output resistance Rmi seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG; and the signal V.sub.LEAD of the common-source amplifier circuit and the signal V.sub.LAG of the source-follower circuit are output signals of the polyphase filter circuitry.

3. The polyphase filter circuitry of claim 1, wherein, for each common-source amplifier circuit or source-follower circuit: the capacitor C.sub.PPF is connected between, or substantially directly between, the source terminal of the transistor M1 and a supply voltage node; or the capacitor C.sub.PPF is implemented as a capacitor C.sub.PPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node and a capacitor C.sub.PPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node.

4. The polyphase filter circuitry of claim 1, wherein, for each common-source amplifier circuit or source-follower circuit: the capacitor C.sub.PPF, or each of the capacitors C.sub.PPF1 and C.sub.PPF2, is implemented as a MOS capacitor, optionally as a field-effect transistor configured as a MOS capacitor.

5. The polyphase filter circuitry of claim 1, wherein, for each common-source amplifier circuit, a resistor R.sub.DRAIN is connected between the drain terminal of the transistor M1 and a supply voltage node, wherein, for each common-source amplifier circuit, the resistor R.sub.DRAIN is implemented as a diode-connected field-effect transistor.

6. The polyphase filter circuitry of claim 1, wherein, for each common-source amplifier circuit or source-follower circuit, a current source or a resistor is connected between the source terminal of the transistor M1 and a supply voltage node, optionally wherein that current source or resistor is implemented as a field-effect transistor.

7. The polyphase filter circuitry of claim 1, wherein: for each common-source amplifier circuit or source-follower circuit, the field-effect transistors of the common-source amplifier circuit are of the same or similar type and/or of the same semiconductor fabrication process; and/or said field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process.

8. Multi-phase clock generation circuitry comprising: the polyphase filter circuitry of claim 1; and a source clock generation circuit configured to generate and provide to the polyphase filter circuitry the input signal V.sub.IN as a source clock signal, the output signals of the polyphase filter circuitry being output clock signals of the multi-phase clock generation circuitry having different relative phases from one another.

9. A source-follower circuit, comprising: an input node configured to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; a field-effect transistor M1 with its gate terminal connected to the input node; and a capacitor C.sub.PPF connected to the source terminal of the field-effect transistor M1, wherein: the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG; and the capacitor C.sub.PFF is substantially directly connected between the source terminal of the field-effect transistor and a supply voltage node and is implemented as a MOS capacitor.

10. The source-follower circuit of claim 9, wherein the capacitor C.sub.PPF is implemented as a field-effect transistor configured as the MOS capacitor.

11. The source-follower circuit of claim 9, wherein: the capacitor C.sub.PPF is implemented as a capacitor C.sub.PPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node, and a capacitor C.sub.PPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node; and the capacitor C.sub.PPF, or each of the capacitors C.sub.PPF1 and C.sub.PPF2, is implemented as a field-effect transistor configured as a MOS capacitor.

12. The source-follower circuit of claim 9, wherein: a current source or a resistor is connected between the source terminal of the transistor and a supply voltage node, optionally wherein that current source or resistor is implemented as a field-effect transistor.

13. The source-follower circuit of claim 9, wherein: the drain terminal of the transistor is connected directly to its supply voltage node.

14. The source-follower circuit of claim 9, wherein the field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process.

15. Integrated circuitry, such as an IC chip, comprising the polyphase filter circuitry of claim 1.

16. Integrated circuitry, such as an IC chip, comprising the multi-phase clock generation circuitry of claim 8.

17. Integrated circuitry, such as an IC chip, comprising the source-follower circuit of claim 9.

Description

[0022] Reference will now be made, by way of example, to the accompanying drawings, of which:

[0023] FIG. 1 is a schematic diagram of previously-considered PPF circuitry;

[0024] FIG. 2 is a schematic diagram of an equivalent circuit of the PPF circuitry of FIG. 1;

[0025] FIGS. 3 to 8 present schematic diagrams of PPF circuitry embodying the present invention;

[0026] FIGS. 9 and 10 are each schematic diagrams of clocked circuitry and multi-phase clock generation circuitry embodying the present invention;

[0027] FIG. 11 presents a graphical output of simulation results based on a simulation of multi-phase clock generation circuitry; and

[0028] FIG. 12 is a schematic diagram of integrated circuitry embodying the present invention.

[0029] In order to better appreciate problems with previously-considered filter circuitry, reference will be made to FIGS. 1 and 2.

[0030] FIG. 1 is a schematic diagram of previously-considered PPF circuitry 1. PPF circuitry 1 comprises a pair of RC filter circuits and an input node configured to receive an input (voltage) signal V.sub.IN having a dominant frequency (or peak frequency or tone frequency) f.sub.PPF. The input signal V.sub.IN may for example be a sinusoidal signal.

[0031] Both of the RC filter circuits are source-follower (SF) circuits as indicated. The left-hand SF circuit is configured as a low-pass filter and the right-hand SF circuit is configured as a high-pass filter circuit.

[0032] In detail, the left-hand SF circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node, with its drain terminal connected to a first supply voltage node (here, VDD or AVD) and with its source terminal connected to a second supply voltage node (here, VSS or AVS, effectively GND or ground) via a current source. The voltages at the first and second supply voltage nodes may be considered high and low voltages, or first and second different voltages, respectively. The transistor M1 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The source terminal of the field-effect transistor M1 is also connected to the second supply voltage node via a resistor R.sub.PPF and a capacitor C.sub.PPF connected in series in that order.

[0033] The right-hand SF circuit is configured in the same way as the left-hand SF circuit except that its resistor R.sub.PPF and capacitor C.sub.PPF are connected in series in the opposite order so as to enable a high-pass function rather than a low-pass function.

[0034] The SF arrangement supplies isolation between the PPF circuitry 1 and a driver circuit (not shown-providing the input signal V.sub.IN), for example a tuned LC-buffer, to avoid resistive/capacitive loading by the PPF circuitry 1 on the driver circuit. That is, the SF arrangement acts as a buffer to minimize or reduce loading on preceding stages.

[0035] As a running example, it will be assumed that the left-hand SF circuit is configured as an RC low-pass filter circuit with pole cut-off frequency equal to the frequency of operation f.sub.PPF to create a 45 lagging (voltage) signal V.sub.LAG at a node between the resistor R.sub.PPF and capacitor C.sub.PPF as indicated, with 0.707 (2) attenuation. Similarly, it will be assumed that the right-hand SF circuit is configured as an RC high-pass filter circuit with a zero at the origin and a pole at the frequency of operation f.sub.PPF to create a 45 leading (voltage) signal V.sub.LEAD at a node between the capacitor C.sub.PPF and resistor R.sub.PPF as indicated, also with 0.707 (2) attenuation.

[0036] The nodes at which the signals V.sub.LAG and V.sub.LEAD are generated may be considered output nodes of the PPF circuitry 1, and those signals may similarly be referred to as output signals of the PPF circuitry 1.

[0037] FIG. 2 is a schematic diagram of an equivalent circuit 2 of the PPF circuitry 1.

[0038] Equivalent circuit 2 comprise a pair of equivalent circuits or sub-circuits, one for each of the SF circuits of FIG. 1 as indicated. The left-hand equivalent circuit represents the low-pass filter and the right-hand equivalent circuit represents the high-pass filter.

[0039] In detail, looking at the left-hand equivalent circuit (corresponding to the left-hand SF circuit of FIG. 1), the SF has an equivalent output resistance of 1/g.sub.m,M1, where g.sub.m, M1 is the transconductance of the transistor M1, which appears as a series resistance at the input node where the input signal V.sub.IN is received. This equivalent output resistance 1/g.sub.m,M1 may be referred to as the output resistance R.sub.M1 seen at the source terminal of the transistor M1. This resistance R.sub.M1 is therefore shown in series with the resistor R.sub.PPF and capacitor C.sub.PPF in line with the left-hand SF circuit of FIG. 1.

[0040] The resistance R.sub.M1 has the effect of shifting the filter pole. For the resistance R.sub.M1 to have a negligible effect on pole location, 1/g.sub.m,M1 typically needs to be at least ten times smaller than the resistance of R.sub.PPF, or the presence of the resistance R.sub.M1 needs to be designed into the value of R.sub.PPF. The transconductance g.sub.m,M1 cannot be increased arbitrarily without loading the driver stage, which places a lower-limit on the resistance of R.sub.PPF. Consequently, the capacitance of the capacitor C.sub.PPF has an upper limit to keep the same pole location.

[0041] Similar analysis, taking into account 1/g.sub.m,M1, may be applied to the right-hand equivalent circuit (corresponding to the right-hand SF circuit of FIG. 1).

[0042] Looking at FIGS. 1 and 2, the PPF circuitry 1 has been found to suffer from large amplitude and/or phase variation across process corners. This variation may in part be due to non-linearities and PVT variations.

[0043] A process corner here may be taken as an example of a design-of-experiments technique, known in semiconductor manufacturing, that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit employing devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, or may not function at all (and be considered to have inadequate design margin).

[0044] Taking field-effect transistors as an example, one naming convention for process corners (adopted in FIG. 11 described later herein) is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS) corner. In this naming convention, three corners exist: typical (t), fast (f) and slow(s). Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. For example, a corner designated as fs denotes fast N-channel MOSFETs and slow P-channel MOSFETs. There are therefore five possible corners: typical-typical (tt), fast-fast (ff), slow-slow (ss), fast-slow (fs), and slow-fast (sf). Corners may also be defined in terms of temperature: low (I) and high (h).

[0045] The main reason for the large spread in amplitude and/or phase across process corners is the pole frequency location which depends heavily on the resistor R.sub.PPF and capacitor C.sub.PPF process corners, which are normally uncorrelated. The low value of the capacitance of the capacitor C.sub.PPF in the PPF circuit 1 as mentioned earlier also makes the PPF circuit 1 sensitive to loading capacitance of the succeeding stage, resulting in more spread across corners.

[0046] The arrangements disclosed herein seek to address such problems by configuring the PPF circuitry, and its constituent filter circuits, to reduce the number of different types of device (transistors, capacitors, resistors) required, as will become apparent. In some arrangements, both the capacitors and resistors are implemented using the same device type, which results in tracking across process deviation and much lower process deviation spread in comparison with the PPF circuitry 1. The arrangements disclosed herein significantly reduce the effect of process corner variation on PPF performance.

[0047] FIG. 3 is a schematic diagram of PPF circuitry 10 embodying the present invention.

[0048] PPF circuitry 10 comprises a pair of RC filter circuits (or circuits which may have RC filter circuits as equivalent circuits), shown in separate dashed boxes, and an input node configured to receive an input signal V.sub.IN having a dominant frequency (or peak frequency or tone frequency) f.sub.PPF. The terminology RC filter will be used herein for ease of explanation, understanding that the disclosed circuits function as RC filter circuits (in the sense of an RC circuit configured with discrete R and C components being an equivalent circuit), even when the R component of the RC filter function is not implemented by a discrete/passive resistor as such. The present disclosure will be understood accordingly.

[0049] One of the RC filter circuits is a source-follower (SF) circuit, as indicated, and the other of the RC filter circuits is a source-degenerated common-source amplifier (CSA) circuit, also as indicated. The left-hand SF circuit is configured as (or to act as) a low-pass filter and the right-hand CSA circuit is configured as (or to act as) a low-pass filter and/or a high-pass filter depending on where the output signal is taken from. The source-degenerated common-source amplifier circuit will be referred to herein as a common-source amplifier (CSA) circuit for simplicity.

[0050] The left-hand SF circuit is similar to the left-hand SF circuit in FIG. 1, except that the resistor R.sub.PPF has been omitted (the resistance of the RC filter function coming from the output resistance as seen at the source terminal of the transistor M1). In detail, the left-hand SF circuit in FIG. 3 comprises a field-effect transistor M1 with its gate terminal connected to the input node, with its drain terminal connected to a first supply voltage node (here, VDD or AVD as before) and with its source terminal connected to a second supply voltage node (here, VSS or AVS as before) via a current source. In some arrangements the current source may be replaced with a resistor. The source terminal of the field-effect transistor M1 is also connected (directly, i.e. without a series-connected discrete resistor) to the second supply voltage node via a capacitor C.sub.PPF. In practice, a (small) resistor may be connected in series with the capacitor C.sub.PPF as long as its effect on pole location is negligible for a given application.

[0051] The right-hand CSA circuit is configured in the same way as the left-hand SF circuit except that the drain terminal of the transistor M1 is connected to the first supply voltage node via a resistor R.sub.DRAIN, thus forming the CSA arrangement. In the arrangement shown, the drain terminal of the transistor M1 is connected to the first supply voltage node substantially directly via the resistor R.sub.DRAIN.

[0052] As before, the SF and CSA arrangements supply isolation between the PPF circuitry 10 and a driver circuit (not shown), i.e. minimizing or reducing loading on preceding stages.

[0053] Continuing the running example, it will be assumed that the left-hand SF circuit is configured as an RC low-pass filter with pole cut-off frequency equal to the frequency of operation f.sub.PPF to create a 45 lagging signal V.sub.LAG at the source terminal of the transistor M1 as indicated, with 0.707 (2) attenuation. Similarly, it will be assumed that the right-hand CSA circuit is configured to provide an RC high-pass filter function with a zero at the origin and a pole at the frequency of operation f.sub.PPF to create a 45 leading signal V.sub.LEAD at the drain terminal of the transistor M1 also as indicated, also with 0.707 (2) attenuation.

[0054] The arrangement of FIG. 3 relaxes the upper limit for C.sub.PPF.

[0055] To generate the V.sub.LAG signal, the left-hand SF circuit employs the source-follower output resistance R.sub.M1 to create the low-pass filter function along with the capacitor C.sub.PPF. The pole frequency-g.sub.m,M1/(2*TT*C.sub.PPF) is set to be equal to the operation frequency f.sub.PPF. Here, for simplicity, C.sub.PPF represents the capacitance of the capacitor C.sub.PPF, and similarly R.sub.DRAIN will be used to represent the resistance of the resistor R.sub.DRAIN.

[0056] To generate the V.sub.LEAD signal, the right-hand CSA circuit employs source degeneration to create a zero at DC (or very low frequency) and a pole at g.sub.m, M1/(2**C.sub.PPF).

[0057] As a result, the C.sub.PPF value can be much higher.

[0058] As also indicated in FIG. 3, the V.sub.LAG signal is also available at the source terminal of the transistor M1 of the right-hand CSA circuit, based on a low-pass filter function to that node. In situations where there is minimal or negligible capacitive loading at the drain terminal of the transistor M1 of the right-hand CSA circuit, or if the phase requirements are suitable, the V.sub.LEAD and V.sub.LAG signals may both be taken from the right-hand CSA circuit, and the left-hand SF circuit may then be omitted. If there is significant capacitive loading at the drain terminal of the transistor M1, it may be that only the V.sub.LEAD signal is used and the V.sub.LAG signal is unused (and hence it is shown in parentheses).

[0059] Thus, as indicated in FIG. 3, the V.sub.LAG and V.sub.LEAD signals from the left-hand SF circuit and right-hand CSA circuit of the PPF circuit 10, respectively, may form output signals of the PFF circuit 10 at corresponding output nodes. In another arrangement, the V.sub.LAG and V.sub.LEAD signals from the right-hand CSA circuit of the PPF circuit 10 may form output signals of the PFF circuit 10 (and the left-hand SF circuit may be omitted).

[0060] FIG. 4 is a schematic diagram of PPF circuitry 20 embodying the present invention, which may be considered a development of the PPF circuitry 10.

[0061] PPF circuitry 20, like the PPF circuitry 10, comprises a pair of RC filter circuits (here not shown in separate dashed boxes), one of which is a source-follower (SF) circuit as indicated and the other of which is a source-degenerated common-source amplifier (CSA) circuit as indicated, and an input node configured to receive the input signal V.sub.IN having a dominant frequency (or peak frequency or tone frequency) f.sub.PPF. It is recalled that these circuits are referred to as RC filter circuits in terms of their function, as here the R element of the RC filter is not implemented by a discrete/passive resistance. The circuits could be referred to simply as filter circuits, for example.

[0062] The left-hand SF circuit and the right-hand CSA circuit of FIG. 4 are the same as the left-hand SF circuit and the right-hand CSA circuit of FIG. 3, respectively, except that the capacitors C.sub.PPF are implemented as MOS capacitors, in this example as field-effect transistors configured as MOS capacitors.

[0063] The PPF circuitry 20 exploits the fact that the poles for the left-hand SF circuit and the right-hand CSA circuit are defined by the output resistance 1/g.sub.m,M1, or R.sub.M1, as mentioned earlier. In the PPF circuitry 20 each capacitor C.sub.PPF is implemented as an NMOS field-effect transistor configured as MOS capacitor. For fast process corners, the transconductance of M1, i.e. g.sub.m,M1, is higher, resulting into lower output resistance R.sub.M1 and higher C.sub.PPF active capacitance, and vice versa for slow process corners. Consequently, the pole frequency spread across process corners is reduced.

[0064] In the right-hand CSA circuit (common-source stage), the resistor R.sub.DRAIN is also implemented as a field-effect transistor, in this case as a diode-connected NMOS field-effect transistor M2. The diode-connected transistor M2 is connected in series (i.e. with its channel in series) between the drain terminal of the transistor M1 of the right-hand CSA circuit and the first supply voltage node (here, VDD), substantially directly.

[0065] In an example variation 20X shown in a dashed circle, the current sources may also be implemented as a field-effect transistor, in this case as an NMOS field-effect transistor M3 whose gate voltage is controlled by a reference voltage VREF to control the drain current Ip. Although only explicitly shown in respect of the left-hand SF circuit in FIG. 4, this applies equally to all of the current sources of the circuits described herein. The variation 20X is one example implementation of a current source using a field-effect transistor; other example implementations (not shown) may be employed such as a field-effect transistor in series with a resistor (which resistor could be implemented as a field-effect transistor, such as a diode-connected field-effect transistor). As another variation (not shown), the current sources may be replaced with resistors, which again could each be implemented as a field-effect transistor, such as a diode-connected field-effect transistor. The present disclosure will be understood accordingly.

[0066] In the implementation of FIG. 4, taking into account variation 20X, all of the discrete components are implemented with field-effect transistors, in this case NMOS field-effect transistors.

[0067] The gain of the signal V.sub.LEAD in the right-hand CSA circuit (common-source stage) is g.sub.m, M1/g.sub.m,M2, where g.sub.m,M2 is the transconductance of the transistor M2, which has low spread across corners if the M1 and M2 devices are of the same or similar type and/or of the same semiconductor fabrication process and/or have the same or similar fabrication parameters. For example, where devices M1 and M2 are of the same fabrication process, their fabrication parameters and masks may be the same as in mass production of a product. Of course, all fabrication processes have uncontrollable variations, which lead to circuit variation on different chips but much less variation of transistors/devices in close proximity.

[0068] FIG. 5 is a schematic diagram of PPF circuitry 30 embodying the present invention, which may be considered a development of the PPF circuitry 20.

[0069] PPF circuitry 30, like the PPF circuitry 10 and 20, comprises a pair of RC filter circuits (again, not shown in separate dashed boxes), one of which is a source-follower (SF) circuit as indicated and the other of which is a source-degenerated common-source amplifier (CSA) circuit as indicated, and an input node configured to receive the input signal V.sub.IN having a dominant frequency f.sub.PPF.

[0070] The left-hand SF circuit and the right-hand CSA circuit of FIG. 5 are the same as the left-hand SF circuit and the right-hand CSA circuit of FIG. 4, respectively, except that the capacitors C.sub.PPF are each implemented as a pair of MOS capacitors, C.sub.PPF1 and C.sub.PPF2.

[0071] The capacitors C.sub.PPF1 and C.sub.PPF2 are implemented as field-effect transistors, here NMOS transistors, configured as MOS capacitors. For each circuit, C.sub.PPF1 is connected between the source terminal of the transistor M1 and the first supply voltage node (here, VDD), substantially directly, and C.sub.PPF2 is connected between the source terminal of the transistor M1 and the second supply voltage node (here, VSS), again substantially directly.

[0072] The capacitors C.sub.PPF1 and C.sub.PPF2 may have substantially the same capacitance as one another, effectively dividing the capacitor C.sub.PPF into two halves. By dividing the capacitor C.sub.PPF into two halves, one connected to the first supply voltage node and the other connected to the second supply voltage node, performance is further improved. Using this technique, the C.sub.PPF MOS capacitor variation in capacitor versus the voltage swing which would be experienced in FIG. 4 is reduced in FIG. 5. By way of explanation, as V.sub.LAG increases, the C.sub.PPF1 capacitance decreases, whereas the C.sub.PPF2 capacitance increases, and vice versa for V.sub.LAG decrease.

[0073] As will be appreciated, various implementations of PPFs are envisaged which may output a plurality of output signals having different relative phases (e.g. V.sub.LAG, V.sub.LEAD) based on an input signal (e.g. V.sub.IN). FIGS. 6 and 7 present schematic views of PPF circuitry 40A, 40B, 40C, and 40D to give examples of such different arrangements of PPF circuitry.

[0074] PPF circuitry 40A may be understood to generate output signals V.sub.LAG and V.sub.LEAD based on the input signal V.sub.IN, and to comprise a SF circuit and a CSA circuit. PPF circuitry 40A may therefore be the same as any of PFF circuitry 10, 20 and 30, where the output signal V.sub.LAG is, or is derived from, the signal V.sub.LAG of the left-hand SF circuit, and where the output signal V.sub.LEAD is, or is derived from, the signal V.sub.LEAD of the right-hand CSA circuit.

[0075] PPF circuitry 40B may be understood to generate output signals V.sub.LAG and V.sub.LEAD based on the input signal V.sub.IN, and to comprise two CSA circuits. Each CSA circuit of the PPF circuitry 40B may therefore be the same as the CSA circuit of any of PFF circuitry 10, 20 and 30. That is, the CSA circuits of the PPF circuitry 40B may both be the same as the CSA circuit of the same PPF circuitry of PFF circuitry 10, 20 and 30, or may be the same as the CSA circuits from respective different PPF circuitry of PFF circuitry 10, 20 and 30. In the PPF circuitry 40B, the output signal V.sub.LAG is, or is derived from, the signal V.sub.LAG of the left-hand CSA circuit, and the output signal V.sub.LEAD is, or is derived from, the signal V.sub.LEAD of the right-hand CSA circuit.

[0076] PPF circuitry 40C may be understood to generate output signals V.sub.LAG and V.sub.LEAD based on the input signal V.sub.IN, and to comprise (only) one CSA circuit. The CSA circuit of the PPF circuitry 40C may be the same as the CSA circuit of any of PFF circuitry 10, 20 and 30. In the PPF circuitry 40C, the output signals V.sub.LAG and V.sub.LEAD are, or are derived from, the signals V.sub.LAG and V.sub.LEAD of the same CSA circuit. As mentioned earlier, this arrangement may be suitable where there is negligible capacitive loading.

[0077] PPF circuitry 40D may be understood to generate output signals V.sub.LAG1 and V.sub.LAG2 (which may be compared to output signals V.sub.LAG and V.sub.LEAD in that they have different relative phases) based on the input signal V.sub.IN, and to comprise two SF circuits. Each SF circuit of the PPF circuitry 40D may therefore be the same as the SF circuit of any of PFF circuitry 10, 20 and 30. That is, the SF circuits of the PPF circuitry 40D may both be the same as the SF circuit of the same PPF circuitry of PFF circuitry 10, 20 and 30, or may be the same as the SF circuits from respective different PPF circuitry of PFF circuitry 10, 20 and 30. In the PPF circuitry 40D, the output signal V.sub.LAG1 is, or is derived from, the signal V.sub.LAG of the left-hand SF circuit, and the output signal V.sub.LAG2 is, or is derived from, the signal V.sub.LAG of the right-hand SF circuit. In order to generate output signals V.sub.LAG1 and V.sub.LAG2 with different relative phases, the resistance R.sub.M1 and/or capacitance C.sub.PPF (or C.sub.PPF1 in combination with C.sub.PPF2) may be configured differently between the two SF circuits as would be understood by the skilled person. References to circuits generating output signals V.sub.LAG and V.sub.LEAD may therefore be considered to also apply to circuits generating output signals V.sub.LAG1 and V.sub.LAG2, where PPF circuitry 40D is involved, and the present disclosure will be understood accordingly.

[0078] The PFF circuitry considered above focuses on outputting a plurality of output signals having different relative phases (e.g. V.sub.LAG, V.sub.LEAD) based on a single input signal (e.g. V.sub.IN). For example, where the given phase shifts are 45 phase shifts as in the running example, the output signals V.sub.LAG, V.sub.LEAD may have relative phases 0 and 90 and be referred to as I and Q phases, respectively. Multiple sets of such PPF circuitry could however be provided to operate based on different such input signals.

[0079] FIG. 8 is a schematic diagram of PPF circuitry 50 embodying the present invention. PPF circuitry 50 comprises two sets of PPF circuitry 60 and 70.

[0080] The PPF circuitry 60 may be taken to be the same as any of the PPF circuitry 10, 20, 30, 40A, 40B, 40C, 40D described above, and thus comprises an input node configured to receive the input signal V.sub.IN and to output output signals V.sub.LAG and V.sub.LEAD.

[0081] The PPF circuitry 70 may also be taken to be the same as any of the PPF circuitry 10, 20, 30, 40A, 40B, 40C, 40D described above, except that it is connected to receive an input signal/V.sub.IN rather than the input signal V.sub.IN, wherein V.sub.IN and/V.sub.IN are complementary signals. The PPF circuitry 70 therefore outputs signals/V.sub.LAG and/V.sub.LEAD instead of signals V.sub.LAG and V.sub.LEAD, respectively, where signals/V.sub.LAG and/V.sub.LEAD may be considered complementary signals of signals V.sub.LAG and V.sub.LEAD, respectively.

[0082] Overall, therefore, the PPF circuitry 50 may be considered to have first and second input nodes for receiving input signals V.sub.IN and/V.sub.IN, respectively, and to output output signals V.sub.LAG, V.sub.LEAD, /V.sub.LAG and/V.sub.LEAD. Where V.sub.IN and/V.sub.IN are complementary signals (i.e. 180 out of phase), and where the phase shifts created in the PPF circuitry 60 and PPF circuitry 70 are all for example 45 as in the running example, the output signals V.sub.LAG, V.sub.LEAD, /V.sub.LAG and/V.sub.LEAD may constitute a set of quadrature output signals, which may have relative phases 0, 90, 180 and 270, respectively, and which may be referred to as I+, Q+, I and Q phases, respectively. In such a case, the PPF circuitry 50 may be, or be part of, quadrature oscillator circuitry.

[0083] FIG. 9 is a schematic diagram of clocked circuitry 80 embodying the present invention, comprising multi-phase clock generation circuitry 82 also embodying the present invention. Clock signals herein may be considered oscillator signals.

[0084] The multi-phase clock generation circuitry 82 may be considered to comprise any of the PPF circuitry 10, 20, 30, 40A, 40B, 40C, 40D described above, and a source clock generation circuit 84 configured to generate and provide to the polyphase filter circuitry the input signal V.sub.IN as a source clock signal. The output signals of the polyphase filter circuitry are then the output clock signals of the multi-phase clock generation circuitry 82 and have different relative phases from one another.

[0085] The clocked circuitry 80 comprises the multi-phase clock generation circuitry 82 and one or more clocked circuits 86 connected to receive the output clock signals of the polyphase filter circuitry and to operate based thereon. For ease of understanding, individual clocked circuits 86A and 86B operating based on the output signals V.sub.LAG and V.sub.LEAD, respectively, are shown. However, in general one or more clocked circuits 86 may be connected to receive the output clock signals.

[0086] FIG. 10 is a schematic diagram of clocked circuitry 90 embodying the present invention, comprising multi-phase clock generation circuitry 92 also embodying the present invention.

[0087] The multi-phase clock generation circuitry 92 may be considered to comprise the PPF circuitry 50 described above, and a source clock generation circuit 94 configured to generate and provide to the polyphase filter circuitry the input signals V.sub.IN and/V.sub.IN as source clock signals. The output signals of the polyphase filter circuitry 50 are then the output clock signals of the multi-phase clock generation circuitry 92 and have different relative phases from one another.

[0088] The clocked circuitry 90 comprises the multi-phase clock generation circuitry 92 and one or more clocked circuits 96 connected to receive the output clock signals of the polyphase filter circuitry 50 and to operate based thereon.

[0089] The clocked circuitry 80 or 90, or the multi-phase clock generation circuitry 82 or 92, may be or be part of quadrature oscillator circuitry, phase lock loop circuitry (PLL), an analogue-to-digital converter (ADC), a digital-to-analogue converter (DAC), Serializer/Deserializer circuits (SERDES), Clock Data Recovery circuits (CDRs), Wireless Transceivers, Processors, IQ phase generation circuitry or clocking circuitry.

[0090] FIG. 11 presents a graphical output of simulation results based on a simulation of the multi-phase clock generation circuitry 92 (see FIG. 10), where the PPF circuitry 60 and the PPF circuitry 70 of the PPF circuitry 50 (see FIG. 8) are each the same as the PPF circuitry 30 (see FIG. 5). Also, for each instance of the PPF circuitry 30, the output signal V.sub.LEAD (or/V.sub.LEAD) is generated by the CSA circuit and the output signal V.sub.LAG (or /V.sub.LAG) is generated by the SF circuit.

[0091] The graph shows the simulation of the output signals V.sub.LAG, V.sub.LEAD, /V.sub.LAG and/V.sub.LEAD across process corners (see the lefthand panel), in this case (for the transistors) typical-typical (tt), slow-slow (ss), and fast-fast (ff), as mentioned earlier. Temperature corners are also taken into account, giving traces for V.sub.LEAD in the order as in the left-hand panel for tt room temperature (tt*t), ss high temperature (ss*h), ss low temperature (ss*I), ff high temperature (ff*h) and ff low temperature (ff*I), where tt*t corresponds to trace ttttttt whose label starts with tt and ends with t (the intermediate letters being ignored for these purposes). These traces for V.sub.LEAD are labelled a to e, respectively, and are those whose peaks align with the label V.sub.LEAD above the graph. Corresponding traces are also provided for V.sub.LAG, /V.sub.LEAD and/V.sub.LAG but are not listed specifically in the lefthand panel. The labels M1, M2, M3 and M4 in FIG. 11 are markers marking four readings to indicate the spread, and do not correspond to the reference signs M1 and M2 for transistors in the earlier Figures.

[0092] As can be seen, the spread across process and temperature is relatively low, and is lower for V.sub.LAG and/V.sub.LAG than for V.sub.LEAD and/V.sub.LEAD. This is because the resistance R.sub.DRAIN (see FIG. 5) affects the gain of V.sub.LEAD and/V.sub.LEAD and the signals V.sub.LAG and/V.sub.LAG do not have this additional factor. The reason for the spread is the extra parasitic capacitance at the V.sub.LEAD node which creates an extra parasitic pole that can slightly shift the V.sub.LEAD signal. The extra pole is not present for the V.sub.LAG signal. Overall, the multi-phase clock generation circuitry 92 exhibits minimal spread across process and temperature.

[0093] It will be appreciated the circuitry disclosed herein enables implementation of PPF with reduced phase/amplitude spread across process corners to improve overall system performance. It will also be appreciated that the component RC filter circuits of the PPF circuitry disclosed herein contribute to the PPF performance. Accordingly, the present invention extends to the SF or CSA circuits individually (or combinations thereof) of PPF circuitry 10, 20 and 30.

[0094] For example, looking at FIGS. 5 to 7, there is provided a source-follower circuit, comprising: an input node configured to receive the input signal V.sub.IN having a dominant frequency f.sub.PPF; a field-effect transistor M1 with its gate terminal connected to the input node; and a capacitor C.sub.PPF connected to the source terminal of the field-effect transistor M1, wherein: the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG. The capacitor C.sub.PFF may be substantially directly connected between the source terminal of the field-effect transistor and a supply voltage node and be implemented as a MOS capacitor (e.g. as a field-effect transistor configured as the MOS capacitor). The capacitor C.sub.PFF may be implemented as a capacitor C.sub.PPF1 and a capacitor C.sub.PPF2 as described earlier. Similarly, there is provided a common-source amplifier circuit, comprising: the source-follower circuit, and a resistor R.sub.DRAIN (which may be a diode-connected field-effect transistor) connected between the drain terminal of the transistor and a supply voltage node. A signal V.sub.LEAD may be generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD. The field-effect transistors may be of the same or similar type and/or of the same semiconductor fabrication process.

[0095] Any of the circuitry disclosed herein may be implemented as integrated circuitry or as an integrated circuit, for example as (or as part of) and IC chip, such as a flip chip. FIG. 12 is a schematic diagram of integrated circuitry 100 embodying the present invention. The integrated circuitry 100 may comprise any of the PPF circuitry (such as PPF circuitry 10, 20, 30, 40A, 40B, 40C, 40D, 50), indicated as PPF circuitry 30 in FIG. 12 for simplicity, the SF or CSA circuits thereof (indicated as 30 (SF), 30 (CSA) in FIG. 12 for simplicity, or the multi-phase clock generation circuitry 82 or 92, or the clocked circuitry 80 or 90.

[0096] Integrated circuitry 100 may be representative of some or all of an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

[0097] The present invention may be embodied in many different ways in the light of the above disclosure, within the spirit and scope of the appended claims.

[0098] The present disclosure extends to the following statements:

[0099] A1. Polyphase filter circuitry, comprising: [0100] an input node configured to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and [0101] a common-source amplifier circuit, [0102] wherein: [0103] the common-source amplifier circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PFF connected to its source terminal; and [0104] for the common-source amplifier circuit, the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PFF are configured to define the frequency response of the common-source amplifier circuit so that, based on the input signal V.sub.IN, a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD and a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.

[0105] A2. The polyphase filter circuitry of statement A1, wherein the signals V.sub.LEAD and V.sub.LAG of the common-source amplifier circuit are output signals of the polyphase filter circuitry.

[0106] A3. The polyphase filter circuitry of statement A1, comprising first and second said common-source amplifier circuits, wherein the signal V.sub.LEAD of the first common-source amplifier circuit and the signal V.sub.LAG of the second common-source amplifier circuit are output signals of the polyphase filter circuitry.

[0107] A4. The polyphase filter circuitry of statement A1, further comprising a source-follower circuit, [0108] wherein: [0109] the source-follower circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PPF connected to its source terminal; and [0110] for the source-follower circuit, the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.

[0111] A5. The polyphase filter circuitry of statement A4, wherein the signal V.sub.LEAD of the common-source amplifier circuit and the signal V.sub.LAG of the source-follower circuit are output signals of the polyphase filter circuitry.

[0112] A6. The polyphase filter circuitry of statement A4 or A5, wherein, for the source-follower circuit, the drain terminal of the transistor M1 is connected to a supply voltage node, optionally directly to that supply voltage node.

[0113] A7. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit or source-follower circuit, the capacitor C.sub.PPF is substantially directly connected to the source terminal of the field-effect transistor M1.

[0114] A8. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit or source-follower circuit, the frequency response of that circuit is defined substantially (only) by the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF.

[0115] A9. The polyphase filter circuitry of any of the preceding statements, wherein: [0116] each common-source amplifier circuit or source-follower circuit is, or functions as, or is equivalent to an RC filter circuit, optionally substantially a first-order RC filter circuit or a single-pole RC filter circuit; and/or [0117] each common-source amplifier circuit is a source-degenerated common-source amplifier circuit.

[0118] A10. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit or source-follower circuit: [0119] the capacitor C.sub.PPF is connected between, or substantially directly between, the source terminal of the transistor M1 and a supply voltage node; or [0120] the capacitor C.sub.PPF is implemented as a capacitor C.sub.PPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node and a capacitor C.sub.PPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node.

[0121] A11. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit or source-follower circuit: [0122] the capacitor C.sub.PPF, or each of the capacitors C.sub.PPF1 and C.sub.PPF2, is implemented as a MOS capacitor, optionally as a field-effect transistor configured as a MOS capacitor.

[0123] A12. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit, a resistor R.sub.DRAIN is connected between the drain terminal of the transistor M1 and a supply voltage node.

[0124] A13. The polyphase filter circuitry of statement A12, wherein, for each common-source amplifier circuit, the resistor R.sub.DRAIN is implemented as a diode-connected field-effect transistor.

[0125] A14. The polyphase filter circuitry of statement A12 or A13, wherein, for each common-source amplifier circuit, a resistance of the resistor R.sub.DRAIN is configured to determine a gain applied by that common-source amplifier circuit in generating its signal V.sub.LEAD based on the input signal V.sub.IN.

[0126] A15. The polyphase filter circuitry of any of the preceding statements, wherein, for each common-source amplifier circuit or source-follower circuit, a current source or a resistor is connected between the source terminal of the transistor M1 and a supply voltage node, optionally wherein that current source or resistor is implemented as a field-effect transistor.

[0127] A16. The polyphase filter circuitry of any of the preceding statements, wherein: [0128] for each common-source amplifier circuit or source-follower circuit, the field-effect transistors of the common-source amplifier circuit are of the same or similar type and/or of the same semiconductor fabrication process; and/or [0129] said field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process.

[0130] A17. The polyphase filter circuitry of any of the preceding statements, wherein: [0131] the input node is a first input node; [0132] the common-source amplifier circuit, or a combination of the first and second said common-source amplifier circuits, or a combination of the common-source amplifier circuit and the source-follower circuit, is a first-node filter circuit; [0133] the polyphase filter circuitry comprises a second input node configured to receive an input signal/V.sub.IN, wherein V.sub.IN and/V.sub.IN are complementary signals; and [0134] the polyphase filter circuitry comprises a second-node filter circuit, substantially the same as the first-node filter circuit, whose gate terminals are connected to the second input node rather than to the first input node so that signals/V.sub.LAG and/V.sub.LEAD are generated instead of signals V.sub.LAG and V.sub.LEAD, respectively, wherein signals/V.sub.LAG and/V.sub.LEAD are complementary signals of signals V.sub.LAG and V.sub.LEAD, respectively.

[0135] A18. The polyphase filter circuitry of any of the preceding statements, wherein the given phase shifts for the output signals of the polyphase filter circuitry, or for at least two said output signals, are substantially the same as one another, and optionally are 45 phase shifts.

[0136] A19. Polyphase filter circuitry, comprising: [0137] an input node configured to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and [0138] first and second source-follower circuits, [0139] wherein: [0140] each source-follower circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PPF connected to its source terminal; [0141] for each source-follower circuit, the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG; [0142] the given phase shifts .sub.LAG for the first and second source-follower circuits are different from one another; and [0143] the signals V.sub.LAG of the first and second source-follower circuits are output signals of the polyphase filter circuitry.

[0144] A20. Multi-phase clock generation circuitry comprising: [0145] the polyphase filter circuitry of any of the preceding statements; and [0146] a source clock generation circuit configured to generate and provide to the polyphase filter circuitry the input signal V.sub.IN as a source clock signal, or the input signals V.sub.IN and/V.sub.IN as source clock signals, the output signals of the polyphase filter circuitry being output clock signals of the multi-phase clock generation circuitry having different relative phases from one another.

[0147] A21. Clocked circuitry, comprising: [0148] the multi-phase clock generation circuitry of statement A20; and [0149] one or more clocked circuits connected to receive the output clock signals and operate based thereon.

[0150] A22. The clocked circuitry of statement A21, being or comprising at least one of: [0151] quadrature oscillator circuitry; [0152] phase lock loop circuitry; [0153] clock data recovery circuitry; [0154] analogue-to-digital converter circuitry; [0155] digital-to-analogue converter circuitry; [0156] Serializer/Deserializer circuitry; [0157] a wireless transceiver; [0158] a processor; and [0159] IQ phase generation circuitry; and [0160] clocking circuitry.

[0161] A23. Integrated circuitry, such as an IC chip, comprising the polyphase filter circuitry of any of statements A1 to A19, or the multi-phase clock generation circuitry of statement A20, or the clocked circuitry of statement A21 or A22.

[0162] B1. A source-follower circuit, comprising: [0163] an input node configured to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; [0164] a field-effect transistor M1 with its gate terminal connected to the input node; and [0165] a capacitor C.sub.PPF connected to the source terminal of the field-effect transistor M1, [0166] wherein: [0167] the output resistance R.sub.M1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal V.sub.IN, a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG; [0168] the capacitor C.sub.PFF is substantially directly connected between the source terminal of the field-effect transistor and a supply voltage node and is implemented as a MOS capacitor.

[0169] B2. The source-follower circuit of statement B1, wherein the capacitor C.sub.PPF is implemented as a field-effect transistor configured as the MOS capacitor.

[0170] B3. The source-follower circuit of statement B1, wherein: [0171] the capacitor C.sub.PPF is implemented as a capacitor C.sub.PPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node, and a capacitor C.sub.PPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node; and [0172] the capacitor C.sub.PPF, or each of the capacitors C.sub.PPF1 and C.sub.PPF2, is implemented as a field-effect transistor configured as a MOS capacitor.

[0173] B4. The source-follower circuit of any of claims B1 to B3, wherein: [0174] a current source or a resistor is connected between the source terminal of the transistor and a supply voltage node, optionally wherein that current source or resistor is implemented as a field-effect transistor.

[0175] B5. The source-follower circuit of any of claims B1 to B4, wherein: [0176] the drain terminal of the transistor is connected directly to its supply voltage node.

[0177] B6. The source-follower circuit of any of claims B1 to B5, wherein the field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process.

[0178] B7. A common-source amplifier circuit, comprising: [0179] the source-follower circuit of any of claims X1 to X4; and [0180] a resistor R.sub.DRAIN connected between the drain terminal of the transistor and a supply voltage node, [0181] optionally wherein a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD.

[0182] B8. The common-source amplifier circuit of statement B7, wherein the resistor R.sub.DRAIN is implemented as a diode-connected field-effect transistor.

[0183] B9. The common-source amplifier circuit of statement B7 or B8, wherein the field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process.

[0184] C1. A source-follower circuit, comprising: [0185] an input node configured to receive an input signal V.sub.IN; [0186] a field-effect transistor M1 with its gate terminal connected to the input node; and [0187] a capacitor C.sub.PPF connected to the source terminal of the field-effect transistor M1, wherein: [0188] the capacitor C.sub.PFF is substantially directly connected between the source terminal of the field-effect transistor and a supply voltage node and is implemented as a MOS capacitor.

[0189] C2. A common-source amplifier circuit, comprising: [0190] the source-follower circuit of statement C1; and [0191] a resistor R.sub.DRAIN connected between the drain terminal of the transistor and a supply voltage node.