LOSSLESS EXCITING CURRENT SAMPLING CIRCUIT FOR ISOLATED CONVERTER

Abstract

A lossless exciting current sampling circuit for an isolated converter includes first and second voltage sampling circuits and a subtraction circuit formed by an operational amplifier. The two sampling circuits sample voltages of the primary winding of an isolation transformer, with outputs fed into the subtracter. The subtracter output is the circuit's output. RC low-pass filters with large time constants are used as primary voltage sampling circuits, realizing integration of voltage differences between the exciting inductance terminals, enabling lossless current sampling without resistors or transformers. The current sampling result is utilized for volt-second balance control, realized along with a hold circuit and comparator which compares the sampling hold result with the current sampling result to generate a control signal.

Claims

1. A lossless exciting current sampling circuit for an isolated converter, comprising: a first voltage sampling circuit connected to a current input terminal of a primary winding of an isolation transformer in an isolated converter and configured to perform sampling, filtering and integration on a voltage of the current input terminal of the primary winding of the isolation transformer to output a voltage sampling value of the current input terminal of the primary winding of the isolation transformer; a second voltage sampling circuit connected to a current output terminal of the primary winding of the isolation transformer in the isolated converter and configured to perform sampling, filtering and integration on a voltage of the current output terminal of the primary winding of the isolation transformer to output a voltage sampling value of the current output terminal of the primary winding of the isolation transformer; and a subtraction circuit having a forward input terminal connected to an output terminal of the first voltage sampling circuit and an inverted input terminal connected to an output terminal of the second voltage sampling circuit, and configured to output an exciting inductive current sampling signal.

2. The lossless exciting current sampling circuit for the isolated converter according to claim 1, wherein the first voltage sampling circuit and the second voltage sampling circuit are identical, and each of the first voltage sampling circuit and the second voltage sampling circuit is an RC filter with a large time constant.

3. The lossless exciting current sampling circuit for the isolated converter according to claim 1, wherein the first voltage sampling circuit and the second voltage sampling circuit are identical, and each of the first voltage sampling circuit and the second voltage sampling circuit is a high-pass filter cascaded integrating circuit with a large time constant.

4. The lossless exciting current sampling circuit for the isolated converter according to claim 2, wherein the RC filter comprises a first resistor, a voltage dividing resistor and a filter capacitor, wherein a first terminal of the first resistor is connected to one terminal of the primary winding of the isolation transformer, a connection point of a first terminal of the voltage dividing resistor and a second terminal of the first resistor is the output terminal of the voltage sampling circuit, a second terminal of the voltage dividing resistor is grounded, and the filter capacitor is connected in parallel between the first terminal and the second terminal of the voltage dividing resistor.

5. The lossless exciting current sampling circuit for the isolated converter according to claim 4, wherein parameters of the first resistor, the voltage dividing resistor and the filter capacitor are determined according the principle that a pole $\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}$ of the RC filter is between a zero $\frac{R_L}{L_m+L_r}$ and a zero $\frac{R_L}{L_r},$ wherein L.sub.m is an exciting inductance, R.sub.L is an equivalent loss resistance, and L.sub.r is a primary leakage inductance.

6. The lossless exciting current sampling circuit for the isolated converter according to claim 5, wherein the subtraction circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor and an operational amplifier, wherein a first terminal of the second resistor is connected to the output terminal of the first voltage sampling circuit, a second terminal of the second resistor and a first terminal of the third resistor are connected to a forward input terminal of the operational amplifier, a DC bias voltage for counteracting an offset of a difference between an output signal of the first voltage sampling circuit and an output signal of the second voltage sampling circuit is input to a second terminal of the third resistor, a first terminal of the fourth resistor is connected to the output terminal of the second voltage sampling circuit, a second terminal of the fourth resistor and a first terminal of the fifth resistor are connected to an inverted input terminal of the operational amplifier, and a second terminal of the fifth resistor is connected to an output terminal of the operational amplifier.

7. The lossless exciting current sampling circuit for the isolated converter according to claim 6, wherein the DC bias voltage satisfies a constraint: $V_{\mathrm{Bias}}>\left|\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_{m-}\mathrm{valley}}+{\mathrm{KV}}_{\mathrm{offset}}\right|,$ wherein V.sub.Bias is the DC bias voltage, K is an amplification factor, i.sub.L.sub.m.sub.valley is a valley of an exciting inductive current, and V.sub.offset is the offset of the difference between the output signal of the first voltage sampling circuit and the output signal of the second voltage sampling circuit.

8. The lossless exciting current sampling circuit for the isolated converter according to claim 7, wherein the exciting inductive current sampling signal output by the subtraction circuit is $V_{\mathrm{sen}}{V}_{\mathrm{Bias}}+\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_m}\left(t\right)+{\mathrm{KV}}_{\mathrm{offset}},$ wherein V.sub.sen is the exciting inductive current sampling signal, and i.sub.L.sub.m(t) is a time-domain signal of the exciting inductive current.

9. A control circuit for realizing volt-second balance of an exciting inductive current, comprising: a sampling hold circuit, wherein the exciting inductive current sampling signal output by the lossless exciting current sampling circuit according to claim 1 is input to an input terminal of the sampling hold circuit, and the sampling hold circuit outputs a sampling hold signal; and a comparison circuit, wherein the exciting inductive current sampling signal output by the lossless exciting current sampling circuit according to claim 1 is input to an inverted input terminal of the comparison circuit, the sampling hold signal output by the sampling hold circuit is input to a forward input terminal of the comparison circuit, and the comparison circuit outputs a control signal for turning off a power switch transistor in the primary circuit of the isolation transformer when the exciting inductive current sampling signal decreases to the sampling hold signal.

10. The control circuit for realizing volt-second balance of the exciting inductive current according to claim 9, wherein the sampling hold circuit comprises a switch, a voltage hold capacitor and a pull-up resistor, wherein a first terminal of the switch is used as an input terminal of the sampling hold circuit, a second terminal of the switch is connected to a positive plate of the voltage hold capacitor and a first terminal of the pull-up resistor and then is used as an output terminal of the sampling hold circuit, a single-pulse trigger signal is input to a control terminal of the switch, a negative plate of the voltage hold capacitor is grounded, and a second terminal of the pull-up resistor is connected to a DC voltage source.

11. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 9, wherein in the lossless exciting current sampling circuit, the first voltage sampling circuit and the second voltage sampling circuit are identical, and each of the first voltage sampling circuit and the second voltage sampling circuit is an RC filter with a large time constant.

12. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 9, wherein in the lossless exciting current sampling circuit, the first voltage sampling circuit and the second voltage sampling circuit are identical, and each of the first voltage sampling circuit and the second voltage sampling circuit is a high-pass filter cascaded integrating circuit with a large time constant.

13. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 11, wherein in the lossless exciting current sampling circuit, the RC filter comprises a first resistor, a voltage dividing resistor and a filter capacitor, wherein a first terminal of the first resistor is connected to one terminal of the primary winding of the isolation transformer, a connection point of a first terminal of the voltage dividing resistor and a second terminal of the first resistor is the output terminal of the voltage sampling circuit, a second terminal of the voltage dividing resistor is grounded, and the filter capacitor is connected in parallel between the first terminal and the second terminal of the voltage dividing resistor.

14. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 13, wherein in the lossless exciting current sampling circuit, parameters of the first resistor, the voltage dividing resistor and the filter capacitor are determined according the principle that a pole $\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}$ of the RC filter is between a zero $\frac{R_L}{L_m+L_r}$ and a zero $\frac{R_L}{L_r},$ wherein L.sub.m is an exciting inductance, R.sub.L is an equivalent loss resistance, and L.sub.r is a primary leakage inductance.

15. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 14, wherein in the lossless exciting current sampling circuit, the subtraction circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor and an operational amplifier, wherein a first terminal of the second resistor is connected to the output terminal of the first voltage sampling circuit, a second terminal of the second resistor and a first terminal of the third resistor are connected to a forward input terminal of the operational amplifier, a DC bias voltage for counteracting an offset of a difference between an output signal of the first voltage sampling circuit and an output signal of the second voltage sampling circuit is input to a second terminal of the third resistor, a first terminal of the fourth resistor is connected to the output terminal of the second voltage sampling circuit, a second terminal of the fourth resistor and a first terminal of the fifth resistor are connected to an inverted input terminal of the operational amplifier, and a second terminal of the fifth resistor is connected to an output terminal of the operational amplifier.

16. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 15, wherein in the lossless exciting current sampling circuit, the DC bias voltage satisfies a constraint: $V_{\mathrm{Bias}}>\left|\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_{m-}\mathrm{valley}}+{\mathrm{KV}}_{\mathrm{offset}}\right|,$ wherein V.sub.Bias is the DC bias voltage, K is an amplification factor, i.sub.L.sub.m.sub.valley is a valley of an exciting inductive current, and V.sub.offset is the offset of the difference between the output signal of the first voltage sampling circuit and the output signal of the second voltage sampling circuit.

17. The control circuit for realizing the volt-second balance of the exciting inductive current according to claim 16, wherein in the lossless exciting current sampling circuit, the exciting inductive current sampling signal output by the subtraction circuit is $V_{\mathrm{sen}}{V}_{\mathrm{Bias}}+\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_m}\left(t\right)+{\mathrm{KV}}_{\mathrm{offset}},$ wherein V.sub.sen is the exciting inductive current sampling signal, and i.sub.L.sub.m(t) is a time-domain signal of the exciting inductive current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a principle block diagram of a lossless exciting current sampling circuit for an isolated converter and volt-second balance control according to the invention.

[0017] FIG. 2 is a specific circuit diagram of the lossless exciting current sampling circuit for an isolated converter and volt-second balance control according to one embodiment of the invention.

[0018] FIG. 3 is an oscillogram of an exciting inductive current of a buck-boost converter sampled by the lossless exciting current sampling circuit in a discontinuous conduction mode (DCM) according to one embodiment of the invention.

[0019] FIG. 4 is an oscillogram of an exciting inductive current of a buck-boost converter sampled by the lossless exciting current sampling circuit in a critical conduction mode (CrCM) according to one embodiment of the invention.

[0020] FIG. 5 is an oscillogram of an exciting inductive current of a flyback converter sampled by the lossless exciting current sampling circuit in a discontinuous conduction mode (DCM) according to one embodiment of the invention.

[0021] FIG. 6 is an oscillogram of an exciting inductive current of the flyback converter sampled by the lossless exciting current sampling circuit in a critical conduction mode (CrCM) according to one embodiment of the invention;

REFERENCE SIGNS IN THE FIGURES

[0022] L.sub.r, primary leakage inductance; L.sub.m, exciting inductance; R.sub.L, equivalent loss resistance; R0, voltage dividing resistor; C0, filter capacitor; C.sub.VSB, voltage hold capacitor; R1-R5, first to fifth resistors; R.sub.up, pull-up resistor; OPA, operational amplifier; SW, switch; CMP, comparator.

Detailed Description of the Embodiments

[0023] The technical solution of the invention will be described in detail below in conjunction with accompanying drawings.

[0024] As shown in FIG. 1 which is a principle block diagram of a lossless exciting current sampling circuit and volt-second balance control according to the invention, an isolated converter includes an isolation transformer, wherein a primary winding of the isolation transformer is connected in parallel with a primary power conversion circuit, and a secondary winding of the isolation transformer is connected in parallel with a secondary circuit. The lossless exciting current sampling circuit performs voltage division, filtering and integration on voltages of two terminals of the primary winding of the isolation transformer to obtain sampling values of the voltages of the two terminals of the primary winding of the isolation transformer, and then amplifies and compensates for a difference between the sampling values of the voltages of the two terminals of the primary winding of the isolation transformer to obtain a voltage signal representing an exciting current. The lossless exciting current sampling circuit includes a first voltage sampling circuit, a second voltage sampling circuit and a subtraction circuit formed by an operational amplifier. The lossless exciting current sampling signal is applied to a volt-second balance control method, and a control signal is obtained by detecting the time when an increment in the cycle of the current sampling signal is 0. A circuit for realizing volt-second balance includes a sampling hold circuit and a comparison circuit. The isolated converter includes an isolation transformer, two terminals of a primary winding of the isolation transformer are marked as a terminal 1 and a terminal b respectively, voltages of the two terminals are V.sub.a and V.sub.b respectively, and the ratio of the number of turns of the primary winding of the isolation transformer to the number of turns of a secondary winding of the isolation transformer is

[00002]$N_{\mathrm{PS}}=\frac{N_P}{N_S}.$

A primary side of an equivalent circuit of the isolation transformer has an exciting inductance L.sub.m, a primary leakage inductance L.sub.r and an equivalent loss resistance R.sub.L, the exciting inductive current is denoted as i.sub.L.sub.m, and a secondary current is denoted as i.sub.sec, so the difference between the voltages of the two terminals of the primary winding of the isolation transformer satisfies the following frequency-domain model:

[00003]$V_a\left(s\right)-V_b\left(s\right)=i_{L_m}\left(s\right).Math.\left(R_L+s\left(L_m+L_r\right)\right)-\frac{i_{\sec }\left(s\right)}{N_{PS}}.Math.\left(R_L-s{L}_r\right)$

[0025] As shown in FIG. 2 which is a specific circuit diagram of the lossless exciting current sampling circuit in this embodiment, the lossless exciting current sampling circuit is connected to the primary side of the isolation transformer in the isolated converter, and includes a first voltage sampling circuit, a second voltage sampling circuit and a subtraction circuit. The first voltage sampling circuit is connected to the terminal a of the primary winding of the isolation transformer, and a sampling output terminal of the first voltage sampling circuit is connected to a forward input terminal of a subtracter. The second voltage sampling circuit is connected to the terminal b of the primary winding of the isolation transformer, and a sampling output terminal of the second voltage sampling circuit is connected to an inverted input terminal of the subtracter. An output terminal of the subtracter is an output terminal of the lossless exciting current sampling circuit.

[0026] The first voltage sampling circuit and the second voltage sampling circuit are both RC circuits with a large time constant to realize integration of detected voltages, wherein a first resistor R.sub.1 and a voltage dividing resistor R.sub.0 form a voltage dividing network to realize voltage division of the sampled voltage of the terminal a of the primary winding of the isolation transformer, and a filter capacitor C.sub.0, the first resistor R.sub.1 and the voltage dividing resistor R.sub.0 form a low-pass filter circuit to filter out high-frequency noise. The two voltage sampling circuits sample the voltages V.sub.a and V.sub.b of the two terminals a and b of the primary winding of the isolation transformer respectively, and a sampling output frequency-domain model of the first voltage sampling circuit and the second voltage sampling circuit is obtained:

[00004]$V_{\mathrm{aS}}\left(s\right)=V_a\left(s\right).Math.\frac{R_0}{R_0+R_1}.Math.\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_{0}s+1}$$V_{bS}\left(s\right)=V_b\left(s\right).Math.\frac{R_0}{R_0+R_1}.Math.\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_{0}s+1}$

[0027] The difference between output signals of the two voltage sampling circuits satisfies the following expression:

[00005]$V_{\mathrm{aS}}\left(s\right)-V_{bS}\left(s\right)=\left[i_{L_m}\left(s\right).Math.\left(R_L+s\left(L_m+L_r\right)\right)-\frac{i_{\sec }\left(s\right)}{N_{\mathrm{PS}}}.Math.\left(R_L+s{L}_r\right)\right].Math.\frac{R_0}{R_0+R_1}.Math.\frac{1}{\left(\frac{R_{0}R}{R_0+R_1}\right)C_{0}s+1}$

[0028] Parameters of the first resistor R.sub.1, the voltage dividing resistor R.sub.0 and the filter capacitor C.sub.0 are selected, and a pole of the RC filter is controlled between a zero

[00006]$\frac{R_L}{L_m+L_r}$

and a

[00007]$\frac{R_L}{L_r}.$

[0029] The frequency-domain model is transformed to a time domain to obtain:

[00008]$V_{\mathrm{aS}}\left(t\right)-V_{{\mathrm{bS}}^{}}\left(t\right)=\frac{R_0}{R_0+R_1}.Math.\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.\left\{\left[\left(L_m+L_r\right).Math.i_{L_m}\left(t\right)+\left(R_L-\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}\right).Math.i_{L_m}\left(t\right).Math.e^{\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}t}\right]-\left[L_r.Math.\frac{i_{\sec }\left(s\right)}{N_{\mathrm{PS}}}+\left(R_L-\frac{L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}\right).Math.\frac{i_{\sec }\left(s\right)}{N_{\mathrm{PS}}}.Math.e^{\frac{1}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}t}\right]\right\}\frac{R_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_m}\left(t\right)+V_{\mathrm{offset}}$

[0030] As can be known from the above expression, an offset V.sub.offset is introduced into the difference between the voltages output by the two sampling circuits, so in this embodiment, a DC bias voltage V.sub.Bias is superposed to the forward input terminal of the subtraction circuit to ensure that an output of the subtraction circuit is always a positive value. A forward input signal V.sub.+(t) of the subtraction circuit satisfies the following expression:

[00009]$V_{+}\left(t\right)=\frac{R_3}{R_2+R_3}.Math.V_{\mathrm{aS}}\left(t\right)+\frac{R_2}{R_2+R_3}.Math.V_{\mathrm{Bias}}$

[0031] The subtraction circuit is composed of a second resistor R.sub.2, a third resistor R.sub.3, a fourth resistor R.sub.4, a fifth resistor R.sub.5 and an operational amplifier OPA, and an output signal of the operational amplifier is calculated according to the characteristics of the operational amplifier:

[00010]$V_{\mathrm{sen}}=R_5.Math.\frac{R_2{R}_3}{R_2+R_3}.Math.\frac{R_4+R_5}{R_4{R}_5}.Math.\left(\frac{V_{\mathrm{Bias}}}{R_3}+\frac{V_{\mathrm{as}}}{R_2}\right)-\frac{R_5}{R_4}.Math.V_{\mathrm{bS}}$

[0032] In the above expression, the resistance of the second resistor R.sub.2, the third resistor R.sub.3, the fourth resistor R.sub.4, the fifth resistor R.sub.5 satisfies R.sub.3=R.sub.5=K*R.sub.2=K*R.sub.4, so:

[00011]$V_{\mathrm{sen}}=V_{\mathrm{Bias}}+K\left(V_{\mathrm{aS}}-V_{\mathrm{bS}}\right)V_{\mathrm{Bias}}+\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_m}\left(t\right)+{\mathrm{KV}}_{\mathrm{offset}}$

[0033] Where, K is used for amplifying an exciting current signal obtained by sampling, and the value of K should ensure that the detected signal V.sub.sen is easy to distinguish.

[0034] It can be known from the above expression that the output result of the lossless exciting current sampling circuit is an exciting inductive current signal superposed with a direct-current component, wherein the DC bias voltage V.sub.Bias satisfies the following condition:

[00012]$V_{\mathrm{Bias}}>\left|\frac{{\mathrm{KR}}_0}{R_0+R_1}.Math.\frac{L_m+L_r}{\left(\frac{R_0{R}_1}{R_0+R_1}\right)C_0}.Math.i_{L_{m-}\mathrm{valley}}+{\mathrm{KV}}_{\mathrm{offset}}\right|.$

[0035] The specific circuit diagram of the lossless exciting current sampling circuit used for realizing volt-second balance is shown in FIG. 2. A circuit for realizing volt-second balance includes the lossless exciting current sampling circuit, a sampling hold circuit and a comparison circuit, wherein the comparison circuit is a quick comparator. The output V.sub.sen of the lossless exciting current sampling circuit is input to an inverted input terminal of the comparator CMP, and is also input to a forward input terminal of the comparator CMP through the sampling hold circuit. The sampling hold circuit includes a switch SW, a voltage hold capacitor C.sub.VSB and a pull-up resistor R.sub.up. Wherein, the switch SW is triggered and controlled by a single pulse, and sampling hold is performed on the output V.sub.sen of the lossless exciting current sampling circuit by the voltage hold capacitor C.sub.VSB at the beginning of a cycle. According to a sampling hold signal V.sub.SH, the voltage hold capacitor C.sub.VSB is charged by the pull-up resistor R.sub.up to obtain a small positive slope signal used for controlling the state of a power transistor to change in advance to prevent system instabilities caused by delayed changing of the state, wherein the pull-up resistor R.sub.up is a maximum resistor of a megohm level.

[0036] The sampling hold signal V.sub.SH output by the sampling hold circuit is input to the forward input terminal of the comparator CMP. The comparator compares V.sub.sen and V.sub.SH; when V.sub.sen decreases to V.sub.SH, the comparator outputs a high level to control the power transistor to be turned off.

[0037] FIG. 3 and FIG. 4 are test diagrams of a four-switch buck-boost converter tested by the lossless exciting current sampling circuit in a discontinuous conduction mode (DCM) and a critical conduction mode (CrCM), where V.sub.sen is a voltage signal obtained by exciting current sampling, V.sub.SH is a voltage signal obtained by sampling hold, i.sub.L is an actual inductive current, and the falling edge of the signal Q3 is determined by the volt-second balance control circuit. It can be seen from FIG. 3 and FIG. 4 that the waveform of the exciting inductive current sampling signal V.sub.sen is accurate, and is consistent with the waveform of the actual exciting inductive current, and when the inductive current basically decreases to 0, the volt-second balance control circuit cuts off Q3, such that the deexciting process is ended.

[0038] FIG. 5 and FIG. 6 are test diagrams of a flyback converter tested by the lossless exciting current sampling circuit in a discontinuous conduction mode (DCM) and a critical conduction mode (CrCM), and it can be seen from FIG. 5 and FIG. 6 that the control signal (Q3) obtained by exciting current sampling is consistent with a secondary synchronous rectifying signal (Q5).

[0039] The above embodiments are merely used for explaining the invention by way of examples, and are not intended to limit the application. In addition, the invention may be implemented in other forms without departing from the spirit or basic features of the invention. The scope of the invention should be defined by the appended claims rather than the above description, and all changes obvious to those skilled in the art should fall within the scope of the appended claims.