INSTRUMENTATION AMPLIFIER CAPABLE OF COMPENSATING OFFSET VOLTAGE

Abstract

An instrumentation amplifier includes an input chopping circuit configured to convert differential input voltages into differential chopping input voltages according to a chopping signal; a compensation voltage input circuit configured to generate differential compensation voltages according to differential compensation signals; a compensation chopping circuit configured to generated signals by performing chopping operation on the differential compensation voltages according to the chopping signal and to provide the signals to the compensation voltage input circuit; an amplifier circuit configured to generate differential output voltages from the differential chopping input voltages and the differential compensation voltages; a modulation circuit configured to modulate the differential output voltages; an output chopping circuit configured to generate a bitstream signal by converting phase of an output of the modulation circuit according to the chopping signal; and a filter circuit configured to filter the bitstream signal.

Claims

1. An instrumentation amplifier comprising: an input chopping circuit configured to convert differential input voltages into differential chopping input voltages according to a chopping signal; a compensation voltage input circuit configured to generate differential compensation voltages according to differential compensation signals; a compensation chopping circuit configured to generated signals by performing chopping operation on the differential compensation voltages according to the chopping signal and to provide the signals to the compensation voltage input circuit; an amplifier circuit configured to generate differential output voltages from the differential chopping input voltages and the differential compensation voltages; a modulation circuit configured to modulate the differential output voltages; an output chopping circuit configured to generate a bitstream signal by converting phase of an output of the modulation circuit according to the chopping signal; and a filter circuit configured to filter the bitstream signal.

2. The instrumentation amplifier of claim 1, wherein the amplifier circuit includes: a first input amplifier configured to receive a positive input voltage among the differential chopping input voltages and a positive compensation voltage among the differential compensation voltages via two positive input terminals; a second input amplifier configured to receive a negative input voltage among the differential chopping input voltages and a negative compensation voltage among the differential compensation voltages via two positive input terminals; and an output amplifier configured to generate the differential output voltages.

3. The instrumentation amplifier of claim 2, wherein the amplifier circuit further includes: a resistor and a capacitor connected in parallel between a negative input terminal of the first input amplifier and an output terminal of the first input amplifier; a resistor and a capacitor connected in parallel between a negative input terminal of the second input amplifier and an output terminal of the second input amplifier; and a variable resistor connected between the negative input terminal of the first input amplifier and the negative input terminal of the second input amplifier.

4. The instrumentation amplifier of claim 2, wherein the amplifier circuit further includes: a resistor connected between an output terminal of the first input amplifier and a positive input terminal of the output amplifier; a resistor connected between an output terminal of the second input amplifier and a negative input terminal of the output amplifier; and a resistor connected between the positive input terminal of the output amplifier and a negative output terminal of the output amplifier; and a resistor connected between the negative input terminal of the output amplifier and a positive output terminal of the output amplifier.

5. The instrumentation amplifier of claim 1, wherein the filter circuit generates an average of a first value and a second value as an output thereof, and wherein the first value corresponds to an output of the filter circuit during a first operation performed when the chopping signal has a high level and the second value corresponds to an output of the filter circuit during a second operation performed when the chopping signal has a low level.

6. The instrumentation amplifier of claim 5, wherein the compensation voltage input circuit sets the differential compensation voltages at the same level when a first reset signal is enabled.

7. The instrumentation amplifier of claim 6, wherein the modulation circuit performs an initialization operation when a second reset signal is enabled.

8. The instrumentation amplifier of claim 7, wherein the first reset signal is enabled at the beginning of the first operation and the second reset signal is enabled at the beginning of the second operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments that include various features, and explain various principles and beneficial aspects of those embodiments.

[0018] FIG. 1 illustrates a conventional instrumentation amplifier.

[0019] FIG. 2 illustrates an instrumentation amplifier according to an embodiment of the present disclosure.

[0020] FIG. 3 is a timing diagram showing an operation of an instrumentation amplifier according to an embodiment of the present disclosure.

[0021] FIGS. 4A and 4B are graphs showing an effect of an instrumentation amplifier according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0022] Various embodiments will be described below with reference to the accompanying figures. Embodiments are provided for illustrative purposes and other embodiments that are not explicitly illustrated or described are possible. Further, modifications can be made to embodiments of the present disclosure that will be described below in detail.

[0023] FIG. 2 is a circuit diagram showing an instrumentation amplifier 100 according to an embodiment of the present disclosure.

[0024] The instrumentation amplifier 100 includes an amplifier circuit 110, an input chopping circuit 120, a first compensation voltage input circuit 131, a second compensation voltage input circuit 132, and a compensation input chopping circuit 140, a modulation circuit 150, an output chopping circuit 160, and a filter circuit 170.

[0025] The amplifier circuit 110 includes a first input amplifier 111, a second input amplifier 112, and an output amplifier 113, each of which is an operational amplifier.

[0026] The first input amplifier 111 and the second input amplifier 112 differ from conventional circuits in that a positive input terminal where an input compensation voltage is input is added, respectively.

[0027] In this embodiment, each of the first input amplifier 111 and the second input amplifier 112 may be implemented with a differential difference amplifier DDA. Since the DDA itself is a conventional technology, detailed description thereof will be omitted.

[0028] A positive chopping input voltage V.sub.INPC is applied to a first positive input terminal of the first input amplifier 111, and a positive compensation voltage V.sub.DACP is applied to a second positive input terminal of the first input amplifier 111.

[0029] A negative chopping input voltage V.sub.INNC is applied to a first positive input terminal of the second input amplifier 112, and a negative compensation voltage V.sub.DACN is applied to a second positive input terminal of the second input amplifier 112.

[0030] A resistor R.sub.1 and a capacitor C.sub.1 are connected in parallel between an output terminal of the first input amplifier 111, that is, a first node N1, and a negative input terminal of the first input amplifier 111, that is, a second node N2.

[0031] A resistor R.sub.1 and a capacitor C.sub.2 are connected in parallel between an output terminal of the second input amplifier 112, that is, a third node N3, and a negative input terminal of the second input amplifier 112, that is, a fourth node N4.

[0032] A variable resistor R.sub.G is connected between the second node N2 and the fourth node N4.

[0033] A resistor R.sub.2 is connected between the first node N1 and a positive input terminal of the output amplifier 113, that is, a fifth node N5, and a resistor R.sub.2 is connected between the third node N3 and a negative input terminal of the output amplifier 113, that is, a sixth node N6.

[0034] A resistor R.sub.3 is connected between the fifth node N5 and a negative output terminal of the output amplifier 113, and a resistor R.sub.3 is connected between the sixth node N6 and a positive output terminal of the output amplifier 113.

[0035] A gain Av of the amplifier circuit 100 is expressed as Equation 2 below. The gain Av can be adjusted by adjusting the variable resistor R.sub.G in the amplifier circuit 100.

[00002]$\begin{array}{cc}{A}_v=\left\{\frac{g_{m,\mathrm{in}}}{g_{m,\mathrm{in}}+g_{m,\mathrm{offset}}}\left(V_{\mathrm{INPC}}-V_{\mathrm{INNC}}\right)+\frac{g_{m,\mathrm{offset}}}{g_{m,\mathrm{in}}+g_{m,\mathrm{offset}}}\left(V_{\mathrm{DACP}}-V_{\mathrm{DACN}}\right)\right\}\left(1+\frac{R_1}{R_G}\right)\left(\frac{R_3}{R_2}\right)& \left[\mathrm{Equation}2\right]\end{array}$

[0036] In Equation 2, g.sub.m,in is a transconductance corresponding to the input voltage in the DDA circuit, and g.sub.m,offset is a transconductance corresponding to an offset voltage in the DDA circuit.

[0037] The input chopping circuit 120 performs a chopping operation according to a chopping signal F.sub.sys, receives input voltages V.sub.INP and V.sub.INN, and outputs chopping input voltages V.sub.INPC and V.sub.INNC.

[0038] For example, when the chopping signal F.sub.sys is at a high level, a positive input voltage V.sub.INP corresponds to the positive chopping input voltage V.sub.INPC and a negative input voltage V.sub.INN corresponds to the negative chopping input voltage V.sub.INNC. Conversely, when the chopping signal F.sub.sys is at a low level, the positive input voltage V.sub.INP corresponds to the negative chopping input voltage V.sub.INNC and the negative input voltage V.sub.INN corresponds to the positive chopping input voltage V.sub.INPC.

[0039] The first compensation voltage input circuit 131 generates the positive compensation voltage V.sub.DACP and the negative compensation voltage V.sub.DACN according to a positive compensation signal COMP.sub.INP and a negative compensation signal COMP.sub.INN. The second compensation voltage input circuit 132 generate the negative compensation voltage V.sub.DACN according to the positive compensation signal COMP.sub.INP and the negative compensation signal COMP.sub.INN.

[0040] In this embodiment, each of the positive compensation signal COMP.sub.INP and the negative compensation signal COMP.sub.INN is a 11-bit digital signal, and each of the first compensation voltage input circuit 131 and the second compensation voltage input circuit 132 includes a digital-to-analog converter.

[0041] The compensation input chopping circuit 140 provides the compensation signals COMP.sub.INP and COMP.sub.INN to the first compensation voltage input circuit 131 and the second compensation voltage input circuit 132 according to the chopping signal F.sub.sys.

[0042] For example, when the chopping signal F.sub.sys is at the high level, the positive compensation signal COMP.sub.INP is provided to the first compensation voltage input circuit 131, and the negative compensation signal COMP.sub.INN is provided to the second compensation voltage input circuit 132. Conversely, when the chopping signal F.sub.sys is at the low level, the positive compensation signal COMP.sub.INP is provided to the second compensation voltage input circuit 132, and the negative compensation signal COMP.sub.INN is provided to the first compensation voltage input circuit 131.

[0043] When the first reset signal RST.sub.IA is activated, the first compensation voltage input circuit 131 and the second compensation voltage input circuit 132 output voltages at the same level.

[0044] In this embodiment, the modulation circuit 150 is an incremental delta sigma modulator that modulates differential output voltages V.sub.OUTP and V.sub.OUTN output from the amplifier circuit 110. The incremental delta sigma modulator itself is well known, so detailed description thereof will be omitted.

[0045] The modulation circuit 150 performs a modulation operation according to the modulation signal F.sub.s and is initialized by the second reset signal RST.sub.DSM.

[0046] The output chopping circuit 160 generates a bit stream signal BS by changing phase of an output of the modulation circuit 150 according to the chopping signal F.sub.sys.

[0047] For example, if the chopping signal F.sub.sys is at the high level, the output of the modulation circuit 150 generates the bit stream signal BS as is. Conversely, when the chopping signal F.sub.sys is at the low level, the phase of the output of the modulation circuit 150 is changed by 180 degrees to generate the bit stream signal BS.

[0048] The filter circuit 170 filters the bit stream signal BS and generates a digital output signal D.sub.OUT.

[0049] In this embodiment, the filter circuit 170 performs digital decimation filtering and averages the two outputs resulting from the chopping operation to generate one digital output signal D.sub.OUT. Since the operation of the digital decimation filter itself is well known, detailed description thereof will be omitted.

[0050] FIG. 3 is a timing diagram showing an operation of the instrumentation amplifier 100 according to an embodiment of the present disclosure.

[0051] The modulation signal F.sub.s has a modulation period T.sub.S, and the modulation circuit 150 performs sampling and modulation operations accordingly.

[0052] The chopping signal F.sub.sys has a conversion period T.sub.conv and the chopping operation is performed accordingly. The modulation period T.sub.conv corresponds to 212 times the modulation period T.sub.S.

[0053] The first reset signal RST.sub.IA resets the amplifier circuit 110 in the high level section between T0 and T1, which is 12 times the modulation period T.sub.S, and at this time, as described above, the first compensation voltage input circuit 131 and the second compensation voltage input circuit 132 output voltages at the same level.

[0054] The second reset signal RST.sub.DSM resets the modulation circuit 150 in the high level section between T2 and T3, which is 28 times the modulation period T.sub.S. During this time, the output voltages V.sub.OUTP and V.sub.OUTN of the amplifier circuit 110 are sufficiently stabilized.

[0055] In FIG. 3, a section between T0 and T4 correspond to one modulation period T.sub.conv.

[0056] From T0 to T2, the modulation signal F.sub.sys is at the high level and the first operation is performed accordingly, and the filter circuit 170 generates a first data DATA1 accordingly.

[0057] From T2 to T4, the modulation signal F.sub.sys is at the low level and a second operation is performed accordingly, and the filter circuit 170 generates a second data DATA2 accordingly.

[0058] The filter circuit 170 averages the first data DATA1 and the second data DATA2 to generate a final digital output signal D.sub.OUT corresponding to the modulation period T.sub.CONV.

[0059] FIGS. 4A and 4B are graphs showing measured noise of the instrumentation amplifier 100 according to an embodiment of the present disclosure.

[0060] FIG. 4A corresponds to a case where the chopping operation is not performed, and FIG. 4B corresponds to a case where the chopping operation is performed.

[0061] In FIGS. 4A and 4B, the gain of the amplifier circuit 100 is 121, the number of data is 200, and the offset voltage is 24 mV.

[0062] In the graphs, the horizontal axis corresponds to the output voltage corresponding to the input voltage, and the vertical axis represents the number of cases corresponding to the range of the output voltage.

[0063] When the chopping operation is not performed as in FIG. 4A, the output is distributed around 24 mV, and in this case, the standard deviation and input referred noise is 6.08 V.sub.RMS. The input-referred noise corresponds to noise divided by the gain of the amplifier circuit 100.

[0064] When the chopping operation is performed as shown in FIG. 4B, the output is distributed around 0V, and in this case, the standard deviation and input reference noise is 2.39 V.sub.RMS.

[0065] It can be seen that by performing the chopping operation in this way, the influence of the offset voltage is reduced and the noise characteristics are improved.

[0066] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the disclosure as defined by the following claims.