FULLY METALLIC ATOMIC-SCALE TIN TRANSISTORS WITH ULTRALOW POWER DISSIPATION

Abstract

An atomic-scale tin transistor device with ultralow power dissipation and a method for producing the same and its use. An atomic-scale tin transistor device includes a source electrode, a drain electrode, and a gate electrode. The source, drain, and gate electrodes are spaced apart from one another and immersed in an aqueous electrolyte containing tin ions in an electrochemical cell. The source electrode and drain electrode are connected to each other in an on-state by a bistable atomic-scale tin point-contact which can be reversibly opened and closed by dissolution/deposition potentials applied to the gate electrode, respectively.

Claims

1. An atomic-scale tin transistor device comprising: a source electrode; a drain electrode; and a gate electrode, wherein the source, drain, and gate electrodes are spaced apart from one another and immersed in an aqueous electrolyte containing tin ions in an electrochemical cell, wherein the source electrode and drain electrode are connected to each other in an on-state by a bistable atomic-scale tin point-contact which can be reversibly opened and closed by dissolution/deposition potentials applied to the gate electrode, respectively, and wherein the atomic-scale tin point-contact consists in the on-state at its narrowest point of at least one tin atom up to a few hundreds of tin atoms formed by electrochemical deposition of tin.

2. The tin transistor device according to claim 1, wherein the source and drain electrodes contain at least one metal selected from the group consisting of copper (Cu), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and silver (Ag).

3. The tin transistor device according to claim 1, wherein the gate electrode consists of a tin wire or a metal film covered with a layer of tin.

4. The tin transistor device according to claim 1, wherein the electrolyte is an aqueous electrolyte comprising tin salts and acids such as SnS04+H2SO4, SnCh+HCl, Sn(NO.sub.3).sub.2+HNO.sub.3, and SnS0.sub.4+HBO.sub.3.

5. The tin transistor device according to claim 1, wherein the conductive channel length is 3 nm or less, preferably 1 nm or less.

6. The tin transistor device according to claim 1, wherein the only movable parts of which are the tin atoms, which connect the source and drain electrodes.

7. The tin transistor device according to claim 1, wherein the gate potential is less than 35 mV in magnitude.

8. The tin transistor device according to claim 1, wherein the tunneling current at an off-state is less than 10 nA.

9. A method of producing an atomic-scale tin transistor device according to claim 1, comprising: repeatedly applying potential cycles between the gate electrode and the source or drain electrode, respectively, for repeatedly depositing and dissolving tin atoms between the source electrode and drain electrode until the bistable atomic-scale tin point-contact has been formed, wherein the potential during the potential cycles is increased and subsequently lowered as long as due to the change of the potential at the gate electrode, the conductance value between the source electrode and the drain electrode is reproducibly switchable between two conductance values as a function of the potential of the gate electrode.

10. The method according to claim 9, wherein the bistable atomic-scale tin point-contact in the on-state at its narrowest point consists of only one tin atom or of a few tin atoms, and wherein by means of the tin transistor device an electrical circuit is opened or closed through conductive switching between on/off states within the atomic-scale tin point-contact with the bistable configuration by deposition/dissolution potentials in millivolts applied to the gate electrode.

11. The method according to claim 9, wherein the cycling process is carried out between two or more specified gate electrode potentials, and wherein the potential is varied in a rectangular, triangle, trapezoid, or sinusoidal waveform.

12. Use of the atomic-scale tin transistor device according to claim 1 as an atomic transistor or atomic relay.

13. The use according to claim 12 for logic switches and/or carrying out logic operations.

14. The use according to claim 12, wherein the transistor or relay is used in the range of ultra-high frequencies from the megahertz range over the gigahertz range to the terahertz range.

15. The use according to claim 12 as building blocks of atom-based electronics.

Description

[0036] In the following, embodiments of the present invention are described in detail with reference to the accompanying Figures which show:

[0037] FIG. 1: A schematic diagram of an atomic-scale tin transistor according to the present invention.

[0038] FIG. 2: A quantum conductance switching controlled via the feedback mechanism. The top (a) shows the ramping wave between 8 and 30 mV which expresses the potential change on the gate, the middle (b) shows a digital graph which presents the conductance variation (0-14 G.sub.0) following the gate potential, and the bottom (c) is a rectangular curve which shows the corresponding current from 0 to 14 A measured with U.sub.DS set to 12.9 mV.

[0039] FIG. 3: A function-generator-controlled quantum conductance switching between 0 and 7 G.sub.0. The upper (a) shows the rectangular wave between 5 and 15 mV which illustrates the potential applied to the gate by the virtual function generator, and the middle (b) digital signal exhibits quantum conductance switching between 0 and 7 G.sub.0 succeeding the gate potential with a delay at 0.1 s. At the same time, the lower (c) rectangular wave demonstrates the corresponsive current variation in a digital form between 0 and 7 A when U.sub.DS is set at 12.9 mV.

[0040] FIG. 4: Potential differences between the gate, source, and drain determined through U.sub.DS and the gate potential U.sub.G of an embodiment of the present invention.

[0041] FIG. 5: Demonstration of bistable conductive switching between 0 and different non-integer quantum conductance levels of an embodiment of the present invention.

[0042] FIG. 6: Demonstration of bistable conductive switching between 0 and different integer quantum conductance levels (from 2 G.sub.0 to 6 G.sub.0) of an embodiment of the present invention.

[0043] FIG. 7: Demonstration of bistable conductive switching between 0 and different integer quantum conductance levels (from 8 G.sub.0 to 12 G.sub.0) of an embodiment of the present invention.

[0044] FIG. 8: Demonstration of high quantum conductance (80 G.sub.0) and current switching controlled via the feedback mechanism in an atomic-scale tin transistor of an embodiment of the present invention.

[0045] FIG. 9: Cyclic voltammogram of tin performed in the electrolyte of SnSO.sub.4 (10 mM)+H.sub.2SO.sub.4 (40 mM) in bi-distilled water.

[0046] FIG. 10: Influence of the switching-on gate potential (U.sub.G) on the operation behaviors of an atomic-scale tin transistor of the present invention.

[0047] FIG. 11: Influence of the switching-off gate potential (U.sub.G) on the operation behaviors of a nano-scale tin transistor.

[0048] FIG. 12: Influence of the dc voltage applied across the drain and source electrodes (Ups) on the operation behaviors of an atomic-scale tin transistor of the present invention.

EXPLANATION OF THE PROCEDURE AND THE COMPONENTS ACCORDING TO THE PRESENT INVENTION

[0049] As illustrated in FIG. 1, the atomic-scale tin transistor is a modified electrolytic cell. In the electrolytic cell, electrical potential energy is converted to chemical potential energy. The electrolytic cell uses an electric current to force a particular chemical reaction to occur, which would otherwise not take place. A standard electrolytic cell consists of two electrodes and an electrolyte. One of two electrodes is the anode, where oxidation takes place. The cathode is the electrode where reduction takes place. In the atomic-scale tin transistor according to the present invention, the gate electrode (3) is taken as one electrode and the combination of source (1) and drain (2) as another. The source electrode is grounded. A dc voltage of a bias voltage (U.sub.DS or U.sub.Bias) is applied to the drain electrode. When the gate potential (U.sub.G) is larger than U.sub.DS (U.sub.G>U.sub.DS), the gate electrode is the anode, and the combination of source and drain is the cathode. Some tin atoms on the surface of the gate are oxidized and dissolved as ions into the electrolyte (4) according to Equation (2):

[00002]$\begin{array}{cc}\mathrm{Sn}\left(\mathrm{solid}\right).fwdarw.{\mathrm{Sn}}^{2+}\left(aq.\right)+2e^{-}& \left(2\right)\end{array}$

[0050] At the same time, an equal number of ions are reduced on the surface of the combination of the source and drain electrodes according to Equation (3):

[00003]$\begin{array}{cc}S{n}^{2+}\left(aq.\right)+2e^{-}.fwdarw.\mathrm{Sn}\left(\mathrm{solid}\right)& \left(3\right)\end{array}$

[0051] Some nano- or microcrystals grow on the surfaces of both source and drain electrodes. Once the crystals are large enough, they meet each other in the gap between the source and drain, and form a tin point-contact (6), which is the switching unit in the atomic-scale tin transistor of the present invention. The zoom-in of the tin point-contact (6) is shown in FIG. 1 with an on-state model. As the U.sub.G<U.sub.DS, the functions of the gate and the combination of source and drain electrodes are reversed. The oxidation reaction takes place on the combination and the reduction on the gate. The tin point-contact is dissolved because of oxidation. When the U.sub.DS is fixed, the tin point-contact can be built and dissolved reversibly by letting U.sub.G>U.sub.DS or U.sub.G<U.sub.DS.

[0052] The energy consumption in the atomic-scale tin transistor comes from electrochemically building and dissolving the tin point-contact between the source and drain. These building and dissolving procedures of the point-contact involve the material transfer of tin atoms amid the gate and the combination of source and drain. The minimal switching energy (E.sub.SW) is estimated by the product of the number (N.sub.contact) of tin atoms building the point-contact, two electrons needed by reducing Sn.sup.2+ ions, the potential difference between the gate and drain (U.sub.1 (on) or U.sub.2 (off) in volt), and one building and one dissolving procedure in a cycle. Therefore, the energy consumption of the atomic-scale tin transistor in one period is calculated as the sum of the dynamic and leakage parts according to Equation (4):

[00004]$\begin{array}{cc}{E}_{\mathrm{total}}{E}_{\mathrm{dynamic}}+E_{\mathrm{leakage}}={}_0^T{I}_G{U}_G\mathrm{dt}+{}_0^T{I}_T{U}_{\mathrm{DS}}d{N}_{\mathrm{contact}}.Math.2.Math.e.Math.U_1+N_{\mathrm{contact}}.Math.2.Math.e.Math.U_2+{}_0^T{I}_t{U}_{\mathrm{DS}}\mathrm{dt},& \left(4\right)\end{array}$

where T is period T=1/f, f operation frequency, U.sub.DS the dc voltage applied across the drain and source electrodes, IG is the electrochemical current between gate and drain-source, I.sub.t is the tunneling current between the drain and source. The gap between the drain and source electrodes at the off-state in the atomic-scale tin transistor is calculated with the formula applied in electrochemical scanning tunneling microscopy (EC-STM) according to Equation (5) (cf. D. Woo et al., Surface Science 601, 1554-1559 (2007):

[00005]$\begin{array}{cc}{I}_t\left(d\right)={\mathrm{AeU}}_{\mathrm{DS}}\exp \left(-4.Math.\frac{\sqrt{2m}}{h}.Math.d\right)={\mathrm{AeU}}_{\mathrm{DS}}\exp \left(-1.025\sqrt{}d\right)& \left(5\right)\end{array}$

where A represents a constant, e represents electron charge, q represents the tunnel barrier in the electrolyte in volt, U.sub.DS represents the voltage across the drain and source, and d represents the gap width in A. By considering the electrolyte concentration applied in the experiment, the tunnel barrier q is set at 1.6 V for further estimation. A tunneling regime with R.sub.T<10.sup.7 (2 was assigned approximately to a substrate-tip separation range <1 nm in an EC-STM. With Equation (5), it is estimated that when the gap width increases 5.33 , the tunneling current should decrease by 1000 times. The tunneling current at off-state in the atomic-scale tin transistor was measured to be 1.7 nA when U.sub.DS was set to 3.23 mV, and the quantum conductance at on-state measured to be 16 G.sub.0. The gap is calculated to be 0.85 nm. The number of atoms (N.sub.contact) in the point-contact in dimensions (length, 0.85 nm; diameter, 0.75 nm) with the conductance of 16 G.sub.0 is calculated theoretically to be 80 at least.

[0053] In the atomic-scale tin transistor according to the present invention, the information carriers are tin atoms. Tin atoms as information carriers are considerably different from electrons or spins due to their natural weight and size. They are physically heavier and more massive. The mass ratio of a tin atom to an electron is 2.1810.sup.5. The through-barrier-tunneling probability of the information carriers can be estimated using the Wentzel-Kramers-Brillouin (WKB) approximation according to Equation (6):

[00006]$\begin{array}{cc}{p}_{WKB}\exp \left(-\frac{4\sqrt{2m}}{h}.Math.L.Math.\sqrt{E_b}.\right),& \left(6\right)\end{array}$

where m denotes the carrier mass, L the barrier width, and E.sub.b the barrier height. Considering both the classic over-barrier transition and quantum through-barrier tunneling, using atoms as information carriers has apparent advantages for L<2.5 nm. It has been confirmed both experimentally and theoretically that the conductive channel of the atomic-scale tin transistor according to the present invention can have geometrical dimensions of a few in diameter and 1 nm in length.

[0054] Different from the CMOS devices, the bit value is presented by the conductance of the point-contact in the atomic-scale tin transistor. However, in this case, information is easily transferred back to the electrical domain, where nearly all information processing takes place today. Therefore, the atomic-scale tin transistor fulfills the requirements, pointed out by K. Galatsi et al., IEEE transactions on Nanotechnology 8, 66-75 (2008) on an electronic device as an alternative to a CMOS device. The conductance of the tin point-contact as a physical state variable can reside in two distinguishable on/off states, can be controlled between the on/off states (write) by the gate potential, read by an electrical current through the tin point-contact, transmitted from one physical location to another via the electrical current, and initialized in a defined state (erase) just by setting the gate potential. It has been demonstrated that the conductance of the tin point-contact as a state variable can compete with the thermal noise bath at room temperature. Furthermore, the inner resistance of metallic atomic-scale transistors is 12.9 k, much less than that of molecular electronic devices (in decades M).

Estimation of Energy Consumption in the Interconnects and Switching Process

[0055] The projected supply voltage (V.sub.DD) and gate length (LG) at the technology node of 0.7 eq in 2034 is 0.6 V and 12 nm, respectively. In charge-based CMOS logic circuits, the primary energy consumption source is electrical charging large capacitances in the interconnect wires. Indeed, transistor dynamic energy consumption constitutes 12% at the 10 nm technology node, and 88% of energy is dissipated in the interconnects. The atomic-scale tin transistors of the present invention as an alternative could offer benefits beyond charge-based CMOS. Because the dynamic energy consumption is proportional to V.sub.DD.sup.2, the energy consumption in the interconnect wires might be reduced by at least 400 times {[600 mV/abs (30 mV)].sup.2=400} or at maximum, 57600 times {[600 mV/abs (2.5 mV)].sup.2=57600} if the CMOS devices could be replaced with atomic-scale tin transistors. The potential values at 30 mV and 2.5 mV are the maximal applied voltages in absolute as illustrated in FIG. 2, FIG. 4a, and FIG. 4d.

[0056] In the atomic-scale tin transistor of the present invention with quantum conductance at 16 G.sub.0, the minimal switching-on energy estimated with the first term in Equation (4) is 0.34 eV (13.1 k.sub.BT at 300 K) when the reduction potential is 2.12 mV (0.5 mV-(1.62)). The minimal energy is about 18.9 times larger than the ultimate limit on the minimum energy per switching at k.sub.BTIn2 (Landauer's limit, approximately 310.sup.21 J at room temperature). The maximal energy is estimated to be 3.99 eV (154.2 k.sub.BT (at 300 K)) when the reduction potential of 24.91 mV (12 mV-(12.91)) is taken from the switching sequence shown in FIG. 4a. However, the projected switching energy of a transistor at the technology node of 0.7 eq is 193 k.sub.BT (T at 300 K). The switching energy is about 1.25 times (193 k.sub.BT/154.2 k.sub.BT, at maximum) or 14.7 times (193 k.sub.BT/13.1 k.sub.BT, at minimum) larger than the switching energy of the atomic-scale tin transistor with the tin point-contact with quantum conductance of 16 G.sub.0.

Estimating the Equivalency of Driving Current in CMOS Devices and Atomic-Scale Tin Transistors

[0057] Fifteen switching sequences with different non-integer and integer quantum conductance are presented in FIGS. 5, 6, and 7. The quantum conductance varies from 1.2 G.sub.0 to 12 G.sub.0. Since U.sub.DS was set at 12.91 mV, the corresponding on-state current (I.sub.DS) through the devices changes from 1.2 A to 12 A. The I.sub.DS presented in FIGS. 2, 3, 4a, and 8 were 14 A, 7 A, 16 A, and 80 A, respectively. In an RC circuit, the time constant is t=RC=V/I.Math.C. Therefore, the delay time (t.sub.d) of a single CMOS inverter is calculated as:

[00007]$\begin{array}{cc}{t}_d=\frac{C_s.Math.V_{\mathrm{DD}}}{I_{\mathrm{dsat}}}& \left(7\right)\end{array}$

where C.sub.s represents the total switching capacitance of a single inverter, I.sub.dsat represents the driving current, V.sub.DD represents the supply voltage. In the CMOS devices fabricated by Intel Company for its 10 nm technology node, I.sub.dsat is 176 A (NMOS) and 139 A (PMOS), and V.sub.DD 0.7 V, I.sub.off 1 nA. The U.sub.DS (12.91 mV) in absolute is 54 times smaller than V.sub.DD (0.7 V) in the 10 nm technology node. The I.sub.dsat divided by 54 should be 3.24 A (NMOS), 2.56 A (PMOS), respectively. The I.sub.DS from the atomic-scale tin transistor at 3 A is comparable with the driving current of CMOS devices in the 10 nm technology node. The corresponding quantum conductance of the atomic-scale tin transistor is 3 G.sub.0 when the U.sub.DS is set at 12.91 mV. For logic operations, one upstream binary switch controls/communicates with several downstream binary switches. The number of downstream devices that are driven by a given upstream device is called fan-out (FO). A typical fan-out in logic circuits is three (FO3). If the atomic-scale tin transistor could be used as one upstream binary switch, the atomic-scale tin transistor should have quantum conductance at 9 G.sub.0 and offer enough driving current at 9 A with U.sub.DS (12.91 mV).

[0058] With the formula mentioned above of the time delay (ta), the equivalence of driving current can be built between the high-performance CMOS devices at the 5 nm technology node [91.4 A/device (on) and 1 nA/device (off), and V.sub.DD=0.7 V] and the atomic-scale tin transistors (I.sub.DS=1.68 A and U.sub.DS=12.91 mV).

Fabricating and Training the Tin Point-Contact

[0059] FIG. 1 shows the schematic diagram of an atomic-scale tin transistor of the present invention. In the present embodiment, atomic-scale tin transistors are operated electrochemically in an electrochemical cell protected by an inert gas (Ar or N.sub.2) environment. The source and drain electrodes are made of one noble metal such as gold, silver, copper, and platinum, for instance. Commonly known lithography methods can be employed. The gap size is between a few micrometers such as 2 m to 10 m (photolithography), and decades of nanometers such as 60 to 160 nm (e-beam lithography). The distance between the drain and gate may be several decades of nanometers. The source and drain electrodes are insulated with a polymer except a small window crossing both electrodes for the electrochemical deposition of tin. The gate electrode consists of a piece of tin wire (diameter of 0.5 mm, Puratronic, 99.9985%) or a noble metal film covered with a layer of tin. For conductance measurements, a dc U.sub.DS is applied to the drain electrode. The source electrode is virtually grounded via a trans-impedance circuit. The potential of the gate is changed with respect to the ground. Therefore, the potential differences between the gate, drain, and source are determined through U.sub.DS and the gate potential. The source, drain, and gate are immersed in one kind of aqueous electrolytes containing tin salts and acids such as SnSO.sub.4+H.sub.2SO.sub.4, SnCl.sub.2+HCl, Sn(NO.sub.3).sub.2+HNO.sub.3, and SnSO.sub.4+HBO.sub.3.

[0060] To fabricate an initial tin point-contact in the gap between the source and drain, a potential at 30 mV is applied to the gate, and U.sub.DS is set at 12.9 mV. While tin islands are deposited in the polymer-free window on the source and drain, the conductance between the source and drain is monitored. When two of the tin islands on the source and drain meet each other in the gap, an atomic-scale tin point-contact is built. After the first junction forms between the source and drain, the deposition procedure continues for some time to stabilize the junction.

[0061] After the initial stage, the contact is opened just by setting the gate potential in the range between 18 mV and 30 mV. Then, the freshly opened junction is closed again by setting the gate potential between 2 mV and 12 mV. The cyclic deposition/dissolution procedure trains the freshly built atomic-scale tin transistor with the feedback mechanism, which is similar to the one previously described for the atomic-scale Ag transistors in WO 2006/026961 A2. After the cyclic training procedure, the atomic-scale tin point-contact forms bistable configurations and can perform bistable quantum conductive switching between the source and drain. The sign and the magnitude of the dc voltage (U.sub.DS) applied across these two electrodes directly influence the growth of the tin point-contact. Such a trained atomic-scale tin transistor can implement quantum conductance switching via both the feedback mechanism and a function generator. For comparison and consistency, the high conductance is indicated in the quantum conductance unit of G.sub.0.

[0062] Following the gate potential via the feedback mechanism, FIG. 2 presents a high conductance (0 to 14 G.sub.0) and current (0 to 14 A) switching in one embodiment. FIG. 3 displays a virtual function-generator-controlled quantum conductance switching between 0 and 7 G.sub.0 and current changing between 0 and 7 A in another embodiment. The quantum conductance and the corresponsive current switching follow the variation of the gate potential in a delay in 0.1 s.

[0063] In the atomic-scale tin transistor, the potential differences between the gate, source, and drain are determined through U.sub.DS applied between the drain and source and the gate potential U.sub.G. It is valuable to investigate possible on/off potential ranges on the gate to fabricate energy efficient atomic-scale tin transistors. In the embodiment described as follows, the fabrication procedure of atomic-scale tin transistors consists of three steps: building tin point-contact, training the point-contact, reducing the absolute value of Ups, and decreasing the difference between U.sub.G and U.sub.DS from both upper and lower sides of Ups. At the first stage, an atomic-scale tin point-contact was built electrochemically in the gap between the source and drain electrodes fabricated with the photo or e-beam lithography by setting U.sub.G at 30 mV and U.sub.DS at 12.9 mV. The point-contact was stabilized at 30 mV for a few minutes afterwards. At the second stage, the cyclic training process started just after the temporal stabilization and continued till a bistable configuration formed in the tin point-contact. At the third stage, the magnitude of U.sub.DS (12.9 mV) was reduced by half, quarter, and one-eighth. After U.sub.DS was set at a fixed value, the on/off potentials approached the U.sub.DS from both upper and lower sides step by step. FIG. 4 illustrates four bistable switching sequences (0 to 16 G.sub.0) achieved by setting Ups at 12.91 mV (a), 6.48 mV (b), 3.23 mV (c), 1.62 mV (d), individually. The corresponding on/off potentials (U.sub.G) were 12/30 mV (a), 2/10 mV (b), 0/4.5 mV (c), and 0.5/2.5 mV (d). In a general tendency, the switching period increases as the magnitudes of U.sub.DS and U.sub.G decrease. The absolute current values were reduced by half, quarter, and one eighth when the magnitude of U.sub.DS was decreased from 12.91 mV to 6.48 mV, 3.23 mV, and 1.62 mV, correspondingly. The values of current I.sub.DS were 16 A (a), 8 A (b), 4 A (c), and 2 A (d), respectively.

[0064] In the embodiment shown in FIG. 4d, the potential difference between the gate and drain is 2.12 mV (on)/0.88 mV (off), and the potential interval between the gate and source is 0.5 mV (on)/2.5 mV (off). These on/off potentials illustrated in FIG. 4d are consistent with the formal reduction potential (2.5 mV) roughly determined with the cyclic voltammetry displayed in FIG. 9.

[0065] The diversity of possible bistable atomic configurations in atomic-scale tin transistors has been confirmed in a series of embodiments under the investigation of the operation behavior of atomic-scale tin transistors via the feedback mechanism. The series of embodiments are presented in FIG. 5 (non-integer quantum conductance at on-states) and FIG. 6 (integer quantum conductance at on-states). In the ten embodiments shown in FIG. 5 and FIG. 6, U.sub.DS was set at 12.91 mV. Ten switching sequences with seven cycles were selected as examples and presented each of the two figures. Because of comparison and clear presentation, the conductance is plotted on the same scale in each figure, but the scales are not the same for the two figures. The scales are 0.25-3 (FIG. 5), 0.5-7 (FIG. 6). Time axes vary to meet the time length of individual switching sequences. In FIG. 5, five graphs demonstrate that the atomic-scale tin transistors can implement operation between an off-state and on-states with non-integer quantum conductance at (a) 1.2 G.sub.0, (b) 1.4 G.sub.0, (c) 1.75 G.sub.0, (d) 2.25 G.sub.0, and (e) 2.5 G.sub.0, respectively. The deposition/dissolution potentials for each switching sequence are 15/35 mV (1.2 G.sub.0), 15/35 mV (1.4 G.sub.0), 8/24 mV (1.75 G.sub.0), 10/30 mV (2.25 G.sub.0), and 10/30 mV (2.5 G.sub.0), separately. In FIG. 6, five digital wave plots illustrate the source-drain conductance switching between the non-conducting off-state and the conducting on-state with integer quantum conductance at (a) 2 G.sub.0, (b) 3 G.sub.0, (c) 4 G.sub.0, (d) 5 G.sub.0, and (e) 6 G.sub.0, individually. The on/off potentials for each switching sequence are 8/24 mV (2 G.sub.0), 8/24 mV (3 G.sub.0), 8/24 mV (4 G.sub.0), 8/24 mV (5 G.sub.0), and 8/24 mV (6 G.sub.0), correspondingly. In FIG. 7, five graphs in rectangular waveform observed in five embodiments demonstrate the conductance switching sequences with on-states at (a) 8 G.sub.0, (b) 9 G.sub.0, (c) 10 G.sub.0, (d) 11 G.sub.0, and (e) 12 G.sub.0, respectively. Since the plots utilize both line and empty circles (measured points), almost only direct transitions of closing edges were observed between these two states, and a few intermediate levels were found in the opening edges. This behavior is the same as that observed for the Pb atomic-scale transistors described previously. Thus, the results indicate that the switching transition of a tin point-contact is also due to a reproducible, bistable atomic-scale reconfiguration. The values of on/off switching potentials in each graph are 10/30 mV (8 G.sub.0), 10/30 mV (9 G.sub.0), 10/30 mV (10 G.sub.0), 8/30 mV (11 G.sub.0), and 8/30 mV (12 G.sub.0), correspondingly.

[0066] Following the gate potential via the feedback mechanism, FIG. 8 presents a high conductance (0 to 80 G.sub.0) and current (0 to 80 A) switching in one embodiment with U.sub.DS set at 12.9 mV. The absolute value of the current in this embodiment is directly comparable with the driving current in the high-performance CMOS devices at the 5 nm technology node [91.4 A/device (on) and 1 nA/device (off), and V.sub.DD=0.7 V]. The values of on/off switching potentials in FIG. 8a are 9/24 mV.

Using Cyclic Voltammetry to Determine the Formal Reduction Potential

[0067] Cyclic voltammetry was performed on one piece of gold wire in diameter of 0.25 mm as a working electrode and two pieces of tin wire in diameter of 0.5 mm as counter and quasi-reference electrodes. Within a sweeping range between-120 mV and 120 mV, the electrochemical potential was scanned reversibly at a rate of 4 mVs.sup.1 in the aqueous electrolytes of SnSO.sub.4 (10 mM)+H.sub.2SO.sub.4 (40 mM). The cyclic voltammogram is plotted in FIG. 9 in the International Union of Pure and Applied Chemistry (IUPAC) convention. From the cyclic voltammogram, the cathodic peak potential (E.sub.pc) is at 30 mV, and the anodic peak potential (E.sub.pa) is at 25 mV. According to cyclic voltammetry, the formal reduction potential (E) should be equal to (E.sub.pa+E.sub.pc)/2. Therefore, the formal reduction potential is determined with this cyclic voltammogram to be 2.5 mV. The electrochemical potential from the cyclic voltammogram can be translated into the potential applied to the gate electrode in the atomic-scale tin transistor, just multiplying the value by 1. The smallest reduction potential of tin is at 2.5 mV, which has been confirmed in FIG. 4d.

Demonstration of Atoms Instead of Electrons as Information Carriers

[0068] To confirm the influence of the gate potential (U.sub.G) and drain-source dc voltage (U.sub.DS) on the operation behaviors of atomic-scale tin transistors, the switching-on gate potential, the switching-off gate potential, and the drain-source dc voltage were changed in the step of 2 mV in three experiments, respectively. The experimental results are presented in FIG. 10 (via variation of the switching-on gate potential, 0-70 G.sub.0 switching), FIG. 11 (via variation of the switching-off gate potential, 0-166 G.sub.0 switching), and FIG. 12 (via variation of U.sub.DS, 0-197 G.sub.0 switching).

[0069] Graph (a) of FIG. 10 shows the switching-on gate potential increasing from 6 mV to 18 mV at the step of 2 mV. Graph (b) illustrates the conductance switching between 0 and 70 G.sub.0. Three arrows mark the change of switching period while the switching-on potential was kept constant. Graph (c) presents the switching periods as solid round points vs. the switching-on gate potential (U.sub.G). While the gate potential varied from 6 mV to 18 mV at the step of 2 mV, the conductance at on-state kept constant at 70 G.sub.0. The on-state electric current was 70 A as the U.sub.DS was set at 12.9 mV. The switching period decreased gradually when the switching-on potential increased from 6 mV to 12 mV and increased minorly when the potential varied from 12 mV to 16 mV. When the gate potential was set at 18 mV, the switching period jumped from low to higher level as marked with three arrows in Graph (b). Thus, although the conductance kept the same, the configuration of the tin point-contact changed during switching.

[0070] Graph (a) of FIG. 11 shows the switching-off gate potential increasing from 30 mV to 16 mV at the step of 2 mV. In the middle, Graph (b) illustrates the conductance switching between 0 and 166 G.sub.0. At the bottom, Graph (c) presents the switching periods as solid round points vs. the gate potential. The on-state electric current was 166 A as the U.sub.DS was set at 12.9 mV. The switching period decreased gradually when the switching-off gate potential increased from 30 mV to 20 mV at the step of 2 mV, and then raised minorly when the gate potential changed forward from 20 mV to 16 mV.

[0071] Graph (a) of FIG. 12 shows the gate potential switching between-28 mV (switching-off) and 10 mV (switching-on). Graph (b) illustrates the conductance switching between 0 and 197 G.sub.0. Graph (c) presents the switching current through the drain and source electrodes. The switching-on current in magnitude increases as the absolute value of U.sub.DS increases. Graph (d) displays the stepwise change of U.sub.DS from 13 mV to 25 mV at the step of 2 mV. Finally, graph (e) demonstrates the switching period as solid round points vs. the drain-source do voltage. Thus, the drain-source dc voltage influences the switching period.

[0072] Because the atomic-scale tin transistors perform bistable conductance switching, the conductance at on-states in these three figures keeps constant during variation of the gate potentials and the drain-source dc voltage. However, the variation of the gate potential and the drain-source dc voltage influences the switching period. The electric current at on-states does not depend on the gate potential during bistable conductance switching. Since the atomic-scale tin transistor has metallic point-contact at on-state, its I-V characteristic is Ohmic. The electric current at on-state is linearly proportional to the drain-source dc voltage as the graph of FIG. 12c indicates. The current changes (I.sub.DS) from 197 A to 376 A when U.sub.DS varies from 13 mV to 25 mV. The constant conductance at on-states in these three experiments demonstrates that the bistable configurations are robust. Therefore, atoms instead of electrons are information carriers in the atomic-scale tin transistors of the present invention.

[0073] The diversity of the bistable atomic configurations with different quantum conductance (from 1.2 G.sub.0 to 197 G.sub.0) in the atomic-scale tin point-contacts has been confirmed. The on-state current (I.sub.DS) through the devices changes from 1.2 A to 375 A. The on/off current ratio can reach 2.210.sup.4. With the formula of the time delay (ta) in a single CMOS inverter, the equivalence of driving current can be built between the CMOS devices at the 5 nm technology node and the atomic-scale tin transistors of the present invention. The I.sub.DS from the atomic-scale tin transistor at 1.68 A (U.sub.DS=12.91 mV) is comparable with the driving current [91.4 A/device (on) and V.sub.DD=0.7 V] of CMOS devices at the 5 nm technology node.