Abstract
A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.
Claims
1. A DAC cell circuit comprising: at least a DAC cell, comprising: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node; wherein the dead-band switch is open during a data transition.
2. The DAC cell circuit of claim 1, comprising: a plurality of DAC cells coupled in parallel; a voltage generating circuit coupled to the first current and the second current for generating a differential output voltage; and a reference voltage coupled to the source of the first MOSFET of each DAC cell.
3. The DAC cell circuit of claim 2, wherein the dead-band switches are controlled by a signal which is periodic with respect to a frequency which is equal to an input data rate of the plurality of DAC cells.
4. The DAC cell circuit of claim 3, further comprising: a common mode voltage; and a plurality of switches coupled between the common mode voltage and the drain of the first MOSFET of each DAC cell.
5. The DAC cell circuit of claim 4, wherein each DAC cell comprises a second MOSFET coupled in cascode above the first MOSFET, and the DAC cell circuit further comprises a cascode voltage coupled to the gate of the second cascode MOSFET of each DAC cell.
6. The DAC cell circuit of claim 4, wherein each DAC cell comprises a second MOSFET coupled in cascode below the first MOSFET, and the DAC cell circuit further comprises a second bias voltage coupled to a gate of the second cascode MOSFET of each DAC cell.
7. The DAC cell circuit of claim 6, wherein each DAC cell further comprises a second dead-band switch coupled between the second bias voltage and the gate of the second MOSFET.
8. The DAC cell circuit of claim 4, wherein each DAC cell comprises a resistor coupled between the source of the first MOSFET and the reference voltage.
9. A complementary DAC cell circuit comprising two DAC cell circuits of claim 4, coupled together in a mirrored architecture.
10. The complementary DAC cell circuit of claim 9, further comprising differential dead-band switches coupled between the differential output voltage and the common mode voltages.
11. The DAC cell circuit of claim 1, wherein the MOSFET is a PMOS.
12. The DAC cell circuit of claim 1, wherein the transistor is an NMOS.
13. The DAC cell circuit of claim 1, wherein the MOSFET is an NPN transistor.
14. The DAC cell circuit of claim 1, wherein the MOSFET is a PNP transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a diagram of a DAC cell according to the related art.
[0024] FIG. 2A is a diagram of a DAC cell undergoing a data transition according to the related art.
[0025] FIG. 2B is a diagram of a DAC cell undergoing a data transition according to the related art.
[0026] FIG. 2C is a diagram of a DAC cell undergoing a data transition according to the related art.
[0027] FIG. 3A is a diagram of a DAC cell circuit according to the related art.
[0028] FIG. 3B is a diagram of a DAC cell circuit according to the related art.
[0029] FIG. 3C is a diagram of a DAC cell circuit according to the related art.
[0030] FIG. 4 is a diagram of a tri-state DAC cell circuit according to the related art.
[0031] FIG. 5 is a diagram of a DAC cell according to an embodiment of the present invention.
[0032] FIG. 6A is a diagram of a DAC cell undergoing a data transition according to an embodiment of the present invention.
[0033] FIG. 6B is a diagram of a DAC cell undergoing a data transition according to an embodiment of the present invention.
[0034] FIG. 6C is a diagram of a DAC cell undergoing a data transition according to another embodiment of the present invention.
[0035] FIG. 6D is a diagram of a DAC cell undergoing a data transition according to another embodiment of the present invention.
[0036] FIG. 6E is a diagram of a DAC cell undergoing a data transition according to another embodiment of the present invention.
[0037] FIG. 7 is a diagram of a tri-state DAC cell according to an embodiment of the present invention.
[0038] FIG. 8 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0039] FIG. 9 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0040] FIG. 10 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0041] FIG. 11 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0042] FIG. 12 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0043] FIG. 13 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0044] FIG. 14 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
[0045] FIG. 15 is a diagram of a DAC cell circuit according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION
[0046] Refer to FIG. 5, which is a schematic diagram of a DAC cell 500 according to an exemplary embodiment of the present invention. As in the DAC cell 100 illustrated in FIG. 1, the DAC cell 500 comprises a first switch P.sub.(i), a second switch N.sub.(i), a capacitor, and a transistor/MOSFET Mn.sub.(i), wherein the capacitor and MOSFET are coupled to a bias line at a common bias node which receives a bias voltage V.sub.NBias. Different from the DAC cell 100, however, the DAC cell 500 further comprises a dead band switch (DB) which is coupled between the common bias node, the capacitor and the gate of the MOSFET. The dead band switch can be controlled by a periodic signal, and can work to isolate the MOSFET from the bias node during data transitions. This will be illustrated in the following.
[0047] Refer to FIG. 6A6E, which illustrate the DAC cell 500 undergoing a data transition from +1 to 1, wherein switch P.sub.(i) goes from state 1 to 0 (i.e. closed to open), and switch N.sub.(i) goes from state 0 to 1 (i.e. open to closed). As shown in FIG. 6A, switch P.sub.(i) is closed, switch N.sub.(i) is open, and the DB switch is closed. In FIG. 6B, the DB switch is open before any data transition to isolate any transitions occurring on the bias node. The effect of the DB switch opening will appear as a slight transition on the bias node. In FIG. 6C, switch P.sub.(i) will open, while switch N.sub.(i) and the DB switch also remain open. The transition because of the charge transfer to the capacitor will appear at the output of the MOSFET but this transition will not appear on the bias node.
[0048] In FIG. 6D, switch P.sub.(i) and the DB switch remain open. Switch N.sub.(i) is closed so that the capacitor will be discharged. At this point, the transition on the output node will go back to the original level. In FIG. 6E, the DB switch will close again. At this point, only a small transition will occur on the bias node, such that the amplitude of any odd-order harmonics at the output of the DAC cell 500 will be minimized. The time between closing the switch N.sub.(i) and closing the DB switch will depend on the size of the capacitor.
[0049] FIG. 7 illustrates a 17-level tri-state DAC applying the dead band switch architecture illustrated in FIG. 5. As shown in the diagram, there is a DB switch on the bias node in each of the DAC cells, and the DB switches are operated according to a periodic signal which has a frequency equal to the input data rate, wherein the DB switch is always open during a data transition. The isolation of the bias node via the DB switch means that the bias nodes exhibit reduced data-dependent transitions, meaning that there will be reduced even-order harmonics on the bias nodes. This means that the output of the DAC will exhibit reduced odd-order harmonics.
[0050] The proposed DAC cell structure incorporating a DB switch can be applied to a number of different circuit architectures, which will be detailed in the following.
[0051] Refer to FIG. 8, which illustrates a plurality of DAC cells coupled in parallel, wherein each DAC cell comprises a DB switch coupled between the bias node and the gate of the MOSFET. Note that the capacitors in each DAC cell are not illustrated for simplicity, and that, as long as the DB switch structure controlled by a periodic signal is maintained, one skilled in the art may implement each DAC cell with a different architecture.
[0052] The differential output of the DAC cells is input to a processing circuit which receives the generated currents I.sub.1 and I.sub.2 and generates a differential V.sub.out signal. The DB switches are coupled to the bias node V.sub.Bias and the sources of the MOSFETs of each DAC cell are coupled to a reference voltage V.sub.Ref.
[0053] FIG. 9 illustrates a DAC circuit according to another embodiment. In this embodiment, each DAC cell further comprises a third switch T.sub.(k) coupled between the drain of the MOSFETs of each DAC cell and a common mode voltage V.sub.CM, such that the DAC cell circuit in FIG. 9 is a tri-state circuit. The third switches are controlled by inputs T.sub.(k), for k=0, 1, . . . , L1.
[0054] FIG. 10 illustrates a tri-state DAC circuit according to another embodiment. In this diagram, each DAC cell comprises two MOSFETs coupled in cascode, as well as a cascode voltage V.sub.Casc coupled to the gates of the first cascode MOSFET of each DAC cell. In this embodiment, the DB switches are respectively coupled between the gates of the second cascode MOSFETs of each DAC cell and the bias voltage.
[0055] FIG. 11 also illustrates a DAC circuit comprising cascode MOSFETs according to another embodiment of the present invention. In this embodiment, the DB switches are coupled between the gates of the first cascode MOSFET of each DAC cell and the bias voltage, and the circuit comprises a second bias voltage V.sub.B1 which is coupled to the gates of the second cascode MOSFET of each DAC cell. This embodiment isolates a different cascode transistor.
[0056] FIG. 12 illustrates another embodiment of a DAC circuit comprising cascode MOSFETs. In this embodiment, both cascode MOSFETs have a DB switch coupled to their respective gates, wherein the DB switches coupled to the second cascode MOSFETs are further coupled to a second bias voltage V.sub.B1. The extra DB switch prevents transitions on the gates of both transistors.
[0057] FIG. 13 illustrates a DAC circuit according to yet another embodiment of the present invention. This embodiment is a similar circuit to that illustrated in FIG. 9 but each DAC cell further comprises a resistor coupled between the source of each MOSFET and the reference voltage V.sub.Ref.
[0058] FIG. 14 illustrates a DAC circuit which is a complementary DAC circuit comprising a mirrored DAC circuit of the circuit illustrated in FIG. 9.
[0059] FIG. 15 is a modification of the DAC circuit illustrated in FIG. 14 and further comprises DB switches coupled between the processing circuit and differential common mode voltages V.sub.CM1, V.sub.CM2. In this embodiment, the DB periodic signals will be differential, wherein a first signal is the inverse of the second signal. These extra dead-band switches are used when coupling from inputs of the processing circuit (differential voltage generation circuit) to gates of the tail transistors is significant.
[0060] In all the circuits illustrated above, the transistors in each DAC cell may be implemented by NMOS, PMOS, NPN or PNP transistors. Note that cascode architecture in the above circuits is illustrated as comprising two cascode transistors, but any number of transistors may be coupled in cascode, wherein the number may be determined according to specific requirements. As long as a tail transistor of the cascode transistors is coupled to a common node reference voltage and at least one transistor of the cascode transistors has its gate coupled to a dead-band switch, different cascode architectures of a DAC cell will fall within the scope of the present invention. Also, note that the switches T (i) are optional, wherein the presence of the switches makes the DAC cells tri-state and their absence makes them binary.
[0061] By providing dead band switches coupled to gates of transistors within a DAC cell, the bias node of a DAC cell can be isolated during data transitions. Further, inter-cell interference between DAC cells within a DAC cell circuit can be reduced. Extra dead-band switches coupled between bias nodes and the DAC outputs can further reduce coupling. The proposed DAC cell structure and DAC cell circuits of the present invention can thereby reduce odd-order harmonics present at an output of a DAC cell.
[0062] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
