SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING THE SAME

Abstract

A semiconductor device comprising a wafer with a preferably single-piece semiconductor substrate, in particular silicon substrate, and at least one integrated electronic component extending in and/or on the semiconductor substrate, the wafer having a front-end-of-line and a back-end-of-line lying there above, the front-end-of-line comprising the integrated electronic component or at least one of the integrated electronic components, and a photonic platform fabricated on the side of the wafer facing away from the front-end-of-line, which photonic platform comprises at least one waveguide and at least one electro-optical device, in particular at least one photodetector and/or at least one electro-optical modulator, wherein the electro-optical device or at least one of the electro-optical devices of the photonic platform is connected to the integrated electronic component or at least one of the integrated electronic components of the wafer.

Claims

1. Semiconductor device comprising a wafer (1) with a preferably single-piece semiconductor substrate (2), in particular silicon substrate, and at least one integrated electronic component (3) extending in and/or on the semiconductor substrate (2), the wafer (1) having a front-end-of-line (5) and a back-end-of-line (6) lying there above, the front-end-of-line (5) comprising the integrated electronic component or at least one of the integrated electronic components (3), and a photonic platform (8) fabricated on the side (9) of the wafer (1) facing away from the front-end-of-line (5), which photonic platform (8) comprises at least one waveguide (12) and at least one electro-optical device (15), in particular at least one photodetector and/or at least one electro-optical modulator, wherein the electro-optical device (15) or at least one of the electro-optical devices (15) of the photonic platform (8) is connected to the integrated electronic component (3) or at least one of the integrated electronic components (3) of the wafer (1).

2. Semiconductor device according to claim 1, wherein the back-end-of-line (6) of the wafer (1) and the photonic platform (8) comprise interconnection elements (7) through which the integrated electronic component (3) or at least one of the integrated electronic components (3) of the wafer (1) is connected to the electro-optical device (15) or at least one of the electro-optical devices (15) of the photonic platform (8).

3. Semiconductor device according to claim 1, wherein the photonic platform (8) comprises material deposited on the side (9) of the wafer (1) facing away from the front-end-of-line (5).

4. Semiconductor device according to claim 1, wherein the photonic platform (8) comprises a planarization coat (10) of a dielectric material fabricated in particular on the side (9) of the wafer (1) facing away from the front-end-of-line (5), and preferably the waveguide or at least one of the waveguides is fabricated on the side (11) of the planarization coat (12) facing away from the wafer (1).

5. Semiconductor device according to claim 3, wherein the planarization coat (10) is a coat formed by deposition, in particular chemical vapor deposition, preferably low-pressure chemical vapor deposition and/or plasma-assisted chemical vapor deposition, and/or by physical vapor deposition and/or atomic layer deposition of at least one coating material on the side (9) of the wafer (1) facing away from the front-end-of-line (5) and preferably subsequent processing of the deposited material on the side (11) facing away from the wafer (1) by means of chemical-mechanical polishing and/or by means of resist planarization, and/or wherein the planarization coat (10) is characterized on its side (11) facing away from the wafer (1) by a roughness of less than 2.0 nm RMS, preferably less than 1.0 nm RMS, particularly preferably less than 0.3 nm RMS, and/or wherein the planarization coat (10) comprises or consists of spin-on-glass and/or at least one polymer and/or at least one oxide, in particular silicon dioxide, and/or at least one nitride.

6. Semiconductor device according to claim 3, wherein the photonic platform (8) comprises at least one further planarization coat (13), the further planarization coat (13) or at least one of the further planarization coats (13) preferably being made of the same material as the planarization coat (10).

7. Semiconductor device according to claim 6, wherein the further planarization coat (13) or at least one of the further planarization coats (13) is formed by deposition, in particular chemical vapor deposition, preferably low-pressure chemical vapor deposition and/or plasma-assisted chemical vapor deposition, and/or by physical vapor deposition and/or atomic layer deposition of at least one coating material on the side (9) of the wafer (1) facing away from the front-end-of-line (5) and preferably subsequent processing of the deposited material on the side (14) facing away from the wafer (1) by means of chemical-mechanical polishing and/or by means of resist planarization, and/or wherein the further planarization coat (13) or at least one of the further planarization coats (13) is characterized on its side (14) facing away from the wafer (1) by a roughness of less than 2.0 nm RMS, preferably less than 1.0 nm RMS, particularly preferably less than 0.3 nm RMS, and/or wherein the further planarization coat (13) or at least one of the further planarization coats (13) comprises or consists of spin-on-glass and/or at least one polymer and/or at least one oxide, in particular silicon dioxide, and/or at least one nitride.

8. Semiconductor device according to claim 1, wherein the at least one waveguide (12) comprises or consists of titanium dioxide and/or aluminium nitride and/or tantalum pentoxide and/or silicon nitride and/or aluminium oxide and/or silicon oxynitride and/or lithium niobate and/or silicon, in particular polysilicon, and/or indium phosphite and/or gallium arsenide and/or indium gallium arsenide and/or aluminium gallium arsenide and/or at least one dichalcogenide, in particular two-dimensional transition metal dichalcogenide, and/or chalcogenide glass and/or resin or resin-containing materials, in particular SU8, and/or polymers or polymer-containing materials, in particular OrmoComp.

9. Semiconductor device according to claim 1, wherein the photonic platform (8) comprises a plurality of waveguides (12), preferably at least two waveguides (12) extending at least in sections one above the other.

10. Semiconductor device according to claim 1, wherein the semiconductor device, in particular the photonic platform (8) comprises at least one coupling device (20) associated with at least one of the waveguides (12), the at least one coupling device (32) preferably serving to couple electromagnetic radiation into the at least one associated waveguide (12), and/or to couple electromagnetic radiation out of the at least one associated waveguide (12).

11. Semiconductor device according to claim 1, wherein the electro-optical device (15) or at least one of the electro-optical devices (15) comprises at least one active element (16, 16a, 16b) comprising or consisting of at least one material, which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption and/or whose refractive index changes as a function of a voltage and/or the presence of a charge and/or an electric field.

12. Semiconductor device according to claim 11, wherein the electro-optical device (15) or at least one of the electro-optical devices is provided by a modulator (15) comprising an active element (16a) having or consisting of at least one material, whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, in particular graphene and/or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or lithium niobate and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor, and a further active element (16b) comprising or consisting of at least one material, whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, in particular graphene and/or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or lithium niobate and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor, or an electrode, wherein the two active elements (16a, 16b) or the active element and the electrode are preferably spaced apart from one another and/or are arranged offset from one another in such a way that they lie one above the other in sections.

13. Semiconductor device according to claim 1, wherein the electro-optical device (15) or at least one of the electro-optical devices is given by a photodetector (15) comprising one, preferably exactly one active element (16) consisting of or comprising at least one material which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption, in particular graphene and/or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor.

14. Semiconductor device according to claim 11, wherein, on or above the active element or at least one of the active elements (16, 16a, 16b), at least one plasmonic structure (29) consisting of or comprising a plasmonically active material, preferably gold and/or silver and/or aluminium and/or copper, is provided, the plasmonic structure (29) preferably comprising at least one pair of plasmonic elements (30) arranged next to one another and consisting of or comprising the plasmonically active material, which plasmonic elements (30) are preferably characterized by a section tapering in the direction of the respective other plasmonic element (30).

15. Semiconductor device according to claim 13, wherein on at least one side of the active element or at least one active element (16, 16a, 16b) a waveguide (12) is provided with an end section (31) tapering in the direction of the active element and preferably ending in a tip, wherein the tapering end section (31) preferably extends up to the active element or the at least one active element (16, 16a, 16b), and/or wherein a contact element (19) is provided on each of two sides of the tapering section (31), which contact element (19) is connected to the active element or the at least one active element (16, 16a, 16b) and which contact element (19) has a section (19a) tapering in the opposite direction and lying next to the ta-pering end section (31) of the waveguide (12).

16. Semiconductor device according to claim 15, wherein a wave-guide (12) having an end section (31) tapering in the direction of the active element or the at least one active element (16, 16a, 16b) and preferably ending in a tip is provided on two sides of the active element or the at least one active element (16, 16a, 16b) in each case, wherein the respective tapering end section (31) preferably extends as far as the active element or the at least one active element (16, 16a, 16b), and/or wherein a contact element (19) is provided on each of two sides of the respective tapering section (31), which contact element (19) is connected to the active element or the at least one active element (16, 16a, 16b) and which contact element (19) has a section (19a) tapering in the opposite direction and lying next to the tapering end section (31) of the respective waveguide (12).

17. Method of manufacturing a semiconductor device, comprising the steps: a wafer (1) having a preferably single-piece semiconductor substrate (2), in particular silicon substrate, and at least one integrated electronic component (3) extending in and/or on the semiconductor substrate (2) is provided, the wafer (1) having a front-end-of-line (5) and a back-end-of-line (6) lying there above, wherein the front-end-of-line (5) comprises the integrated electronic component (3) or at least one of the integrated electronic components (3), a photonic platform (8) is fabricated on the side (9) of the wafer (1) facing away from the front-end-of-line (5), the photonic platform (8) comprising at least one waveguide (12) and at least one electro-optical device (15), in particular at least one photodetector and/or at least one electro-optical modulator.

18. Method according to claim 17, wherein the back-end-of-line (6) of the provided wafer (1) comprises interconnection elements (7) connected to the integrated electronic component (3) or at least one of the integrated electronic components (3) of the front-end-of-line (5) and, in the photonic platform (8), inter-connection elements (7) are fabricated which are connected, on the one hand, to the interconnection elements (7) of the back-end-of-line (6) and, on the other hand, to the electro-optical device (15) or at least one of the electro-optical devices (15).

19. Method according to claim 17, wherein the fabrication of the photonic platform (8) includes depositing material on the side (9) of the wafer (1) facing away from the front-end-of-line (5).

20. Method according to claim 17, wherein the fabrication of the photonic platform (8) includes fabricating a planarization coat (10) of a dielectric material in particular on the side (9) of the wafer (1) facing away from the front-end-of-line (5), and preferably the or at least one of the waveguides (12) is fabricated on the side (11) of the planarization coat (10) facing away from the wafer (1).

21. Method according to claim 20, wherein the fabrication of the planarization coat (10) includes that a coating material is applied, in particular deposited, to the side (9) of the wafer (1) and the coating material is at least on its side (11) facing away from the wafer (1) subsequently subjected to a planarization treatment, in particular chemically-mechanically polishing and/or resist-planarization, preferably in such a way that a roughness of the side of less than 2.0 nm, preferably less than 1.0 nm RMS, particularly preferably less than 0.3 nm RMS is obtained.

22. Method according to claim 20, wherein at least one further planarization coat (13) is preferably fabricated following the fabrication of the at least one waveguide (12), the fabrication of the further planarization coat (13) preferably including that a coating material is applied, in particular deposited, to the side (11) of the planarization coat (10) facing away from the wafer (1) and/or of the at least one waveguide (12) and the coating material is then, at least on its side (14) facing away from the wafer (1), subjected to a planarization treatment, in particular chemical-mechanical polishing and/or resist planarization, preferably in such a way that a roughness of the side of less than 2.0 nm, preferably less than 1.0 nm RMS, particularly preferably less than 0.3 nm RMS is obtained.

23. Method according to claim 20, wherein the fabrication of the planarization coat (10) and/or the further planarization coat (13) includes applying a further coating material to the treated side following the planarization treatment.

24. Method according to claim 20, wherein the fabrication of the at least one waveguide (12) includes applying a waveguide material in particular to the side (11) of the planarization coat (10) facing away from the wafer (5), preferably depositing or spinning or transferring it thereon, and then preferably carrying out a structuring of the applied waveguide material in particular by means of lithography and/or reactive ion etching.

25. Method according to claim 17, wherein the or at least one waveguide (12) at least one coupling device (32) is manufactured, which serves for coupling electromagnetic radiation into the at least one waveguide (12) and/or for coupling electromagnetic radiation out of the at least one waveguide (12).

26. Method of manufacturing at least one semiconductor apparatus (38), wherein a semiconductor device according to claim 1 is provided and fragmented.

27. A semiconductor apparatus (38) obtained by fragmenting a semiconductor device according to claim 1.

Description

[0158] In the Drawing Shows:

[0159] FIG. 1 a top view of an embodiment of a semiconductor device according to the invention in purely schematic representation;

[0160] FIG. 2 a partial section through the semiconductor device of FIG. 1 in purely schematic representation;

[0161] FIG. 3 a top view of the photodetector from FIGS. 2, 4 and 5 in purely schematic representation;

[0162] FIG. 4 a partial section through a second embodiment of a semiconductor device according to the invention in purely schematic representation;

[0163] FIG. 5 a partial section through a third embodiment of a semiconductor device according to the invention in purely schematic representation;

[0164] FIG. 6 a partial section through a fourth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0165] FIG. 7 a partial section through a fifth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0166] FIG. 8 a partial section through a sixth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0167] FIG. 9 a top view on the modulator from FIG. 8 in purely schematic representation;

[0168] FIG. 10 a partial section through a seventh embodiment of a semiconductor device according to the invention in purely schematic representation;

[0169] FIG. 11 a partial section through an eighth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0170] FIGS. 12 to 16 five examples of possible contacting of the active elements of the electro-optical devices of the semiconductor devices in purely schematic representation;

[0171] FIG. 17 a partial section through a ninth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0172] FIG. 18 a partial section through a tenth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0173] FIG. 19 a partial section through an eleventh embodiment of a semiconductor device according to the invention in purely schematic representation;

[0174] FIG. 20 a partial section through a twelfth embodiment of a semiconductor device according to the invention in purely schematic representation;

[0175] FIG. 21 a top view of a first embodiment of a photodetector with plasmonic coupling in purely schematic representation;

[0176] FIG. 22 a top view of a second embodiment of a photodetector with plasmonic coupling in purely schematic representation;

[0177] FIG. 23 a top view of an embodiment of a modulator with plasmonic coupling in purely schematic representation;

[0178] FIG. 24 a top view of an example of a side coupling device in purely schematic representation;

[0179] FIG. 25 the side coupling device of FIG. 24 in schematic sectional representation;

[0180] FIG. 26 a top view of an example of a grating coupling device in purely schematic representation;

[0181] FIG. 27 the grating coupling device shown in FIG. 26 in schematic sectional representation;

[0182] FIG. 28 the steps of the method for manufacturing the device according to FIG. 1;

[0183] FIG. 29 a top view of three semiconductor devices according to the invention in purely schematic representation; and

[0184] FIG. 30 a purely schematic sectional representation through a semiconductor device according to the invention of FIG. 29.

[0185] In the figures, the same components or elements are marked with the same reference signs.

[0186] FIG. 1 shows in a purely schematic, highly simplified representation a top view of a semiconductor device according to the invention. This comprises a wafer 1, which can also be seen in sections in the partial sectional view according to FIG. 2, and which comprises a single-piece silicon substrate 2 and a plurality of integrated electronic components 3, which in the example shown extend in the semiconductor substrate 2. The integrated electronic components 3, which may in particular be transistors and/or resistors and/or capacitors, are indicated in the schematic FIG. 2 only in a simplified manner by a line with hatching provided with the reference sign 3. In a corresponding position in the substrate 2, a large number of integrated electronic components 3 are found in a sufficiently known manner. These can also be components of processors, such as CPUs and/or GPUs, or form such components in a likewise known manner.

[0187] The wafer 1 is a component or device from which a plurality of chips can be obtained in a manner sufficiently known from the prior art by (wafer) dicing, which is also referred to in German as “Wafer-Zerkleinern”. The dicing or fragmenting can be performed, for example, by (laser) cutting or sawing or scribing or breaking the wafer 1. Accordingly, a wafer comprises a plurality of regions, each of which forms a chip following dicing. These regions are referred to as chip regions 4.

[0188] In FIG. 1 these are indicated purely schematically with a thin line. Each chip region 4 of the wafer 1 comprises a section or partial region of the single-piece semiconductor substrate 2 and usually at least one, preferably several, integrated electronic components 3. Depending on the design of the wafer 1, which depends on the specific case of application, up to ten or even several tens, several hundreds or several thousands of integrated electronic components 3 can be provided in each chip region 4, for example. These can be arranged next to each other and/or one above the other.

[0189] The wafer 1 has a front-end-of-line (for short FEOL) 5, in which the plurality of integrated electronic components 3 are arranged, and an overlying back-end-of-line (for short BEOL) 6, in which or via which the integrated electronic components 3 of the front-end-of-line 5 are interconnected by means of different metal planes. The integrated electronic components 3 in the FEOL 5 and the associated interconnection in the BEOL 6 form integrated circuits of the wafer 1 in a sufficiently pre-known manner. A FEOL 5 is also sometimes referred to as a transistor front-end and a BEOL as a metal back-end. The metal planes comprise a plurality of interconnection elements 7, which are given in the present case by so-called VIAs, which is the abbreviation for Vertical Interconnect Access. The VIAs 7 are made of metal, for example copper, aluminium or tungsten.

[0190] The depicted semiconductor device 1 further comprises a photonic platform 8 which, as can clearly be seen in the sectional view according to FIG. 2, is located above the wafer 1 and, according to the invention, has been fabricated on its back-end-of-line 6, specifically built directly thereon. It should be noted that the chip regions 4 in FIG. 1 are indicated with a thin line, as these are located below the photonic platform 8 in the top view.

[0191] The wafer 1 is characterized by a diameter of 200 mm in the illustrated embodiment. This is also the diameter of the photonic platform 8 and the semiconductor device as a whole (cf. FIG. 1), which comprises the wafer 1 and, above the wafer 1, the photonic platform 8 fabricated thereon. The partial section according to FIG. 2 shows in the vertical direction the entire device according to FIG. 1 with the superimposed components or coats or elements thereof, but in the horizontal direction only a very small part of the device, specifically only a small part or section of one of the chip regions 4, which in turn is small in comparison to the overall extent of the device in the horizontal direction. This applies equally to the other partial sections. In the present case, the chip regions 4 are characterized in plan view by a rectangular shape in each case with an edge length of 2 mm in one direction and 3 mm in the other direction. It should be noted that these are indicated as squares in the purely schematic FIG. 1 merely for reasons of simplification.

[0192] As can be seen from FIG. 2, the photonic platform 8 provided according to the invention comprises a planarization coat 10, which has been fabricated on the side 9 of the wafer 1 facing away from the front end of line 5 and is made of a dielectric material. In the present case, the planarization coat 10 consists of silicon dioxide (SiO.sub.2), although this is to be understood as exemplary and other materials may also be used.

[0193] In the embodiment shown, the planarization coat 10 is a coat obtained by deposition of the corresponding coating material, here SiO.sub.2, on the side 9 of the wafer 1 facing away from the front-end-of-line 5 and subsequent planarization processing of the deposited material on the side 11 facing away from the wafer 1. The planarization coat 10 is characterized by a roughness of 0.2 nm RMS due to the processing on its side 11 facing away from the wafer 1, whereby this is to be understood as an example.

[0194] In the example shown, the planarization coat 10 extends over the entire side 9 of the wafer 1 facing away from the front-end-of-line 5. The material of the planarization coat 10 has been deposited over the entire surface of the side 9 of the wafer 1 facing away from the front-end-of-line 5. This is characterized by a diameter which at least substantially corresponds to that of the wafer 1.

[0195] The photonic platform 8 further comprises a plurality of waveguides 12 fabricated on the side 11 of the planarization coat 10 facing away from the wafer 1. Dielectrics, preferably titanium dioxide, which was also used in the illustrated embodiment, are particularly suitable as waveguide materials. Alternatively or additionally, waveguides 12 made of aluminium nitride and/or tantalum pentoxide and/or silicon nitride and/or aluminium oxide and/or silicon oxynitride and/or lithium niobate or also of semiconductors such as silicon, indium phosphide, gallium arsenide, indium gallium arsenide, aluminium gallium arsenide or dichalcogenides or chalcogenide glass or polymers such as SU8 or OrmoComp can be provided.

[0196] Typical dimensions of the waveguides 12 are a thickness in the range of 150 nm and 10 μm and in lateral extension, parallel to the wafer surface, widths between 100 nm and 10 μm. Purely by way of example, a thickness of 300 nm and a width of 1.1 μm may be mentioned. The specific dimensions of the waveguides 12 can vary. In particular, they vary in width depending on the function they perform.

[0197] In the present case, the photonic platform 8 also comprises a further planarization coat 13, which consists of the same material as the planarization coat 10, i.e. in the present case also of SiO.sub.2. The further planarization coat 13 is characterized on its side 14 facing away from the wafer 1 by a roughness corresponding to that of the planarization coat 10. It should be emphasized that the planarization coat 10 and the further planarization coat 13—as in the present case—can be characterized by the same material, the same extent and the same roughness on their sides 11 and 14, respectively, facing away from the wafer 1, but this is not necessary and is therefore not to be understood as restrictive.

[0198] The photonic platform 8 also comprises a plurality of electro-optical devices 15, which may in particular be photodetectors and/or modulators. In the illustrated embodiment, the photonic platform 8 comprises both a plurality of photodetectors 15 and a plurality of modulators 15.

[0199] FIG. 2 shows an example of one of the electro-optical devices, specifically a photodetector 15, schematically. FIG. 3 shows—again only schematically—a top view of a section of the device of FIG. 1, specifically of the photodetector 15 of FIG. 2.

[0200] FIGS. 4 and 5 show exemplary partial sections through further embodiments of semiconductor devices according to the invention, which may correspond in plan view to that of FIG. 1, and in which in each case photodetector 15 and underlying waveguide 12 can be seen, whereby in each case the photodetector 15 and/or the waveguide 12 is embodied alternatively to that of FIG. 2. It should be noted that the schematic representation from FIG. 3 also corresponds to the detectors 15 from FIGS. 4 and 5, with the proviso that only the upper, narrow part of the waveguides with a T-shaped cross-section (cf. FIGS. 4 and 5) is shown.

[0201] FIGS. 6 and 7 show partial sections through further embodiments of semiconductor devices according to the invention. Here, photodetectors 15 are also provided as electro-optical devices, differing in structure from those of FIGS. 2, 4 and 5.

[0202] FIGS. 8, 10 and 11 show partial sections through further embodiments of semiconductor devices according to the invention, in each of which an electro-optical device embodied as a modulator 15 can be seen. FIG. 9 shows a top view of the modulator 15 of FIG. 8.

[0203] The photodetectors 15 according to FIGS. 2 and 4 to 7 each comprise an active element 16 made of a material that absorbs electromagnetic radiation of at least one wavelength, preferably of at least one wavelength range, and generates an electrical photosignal as a result of the absorption. In the examples of FIGS. 2 and 4 to 7, the active elements 16 of the photodetectors 15 are each given by a graphene film 16. Graphene may also change its refractive index (refractivity and/or absorption) as a function of a voltage and/or charge and/or an electric field. It is also possible that the active elements 16 are given by films comprising or consisting of at least one other material, for example films comprising or consisting of a dichalcogenide-graphene heterostructure consisting of at least one layer of graphene and at least one layer of a dichalcogenide, or films comprising at least one layer of boron nitride and at least one layer of graphene. There are different chalcogenides, here transition metal dichalcogenides as two-dimensional materials such as MoS2, or WSe2 are particularly suitable.

[0204] As a comparison shows, the arrangements shown in FIGS. 2 and 4 differ solely in the shape of the waveguide 12. Whereas FIG. 2 shows a strip waveguide 12 with a rectangular cross-section, FIG. 4—just like FIG. 5—shows a ridge waveguide 12 with a T-shaped cross-section with a first, upper waveguide segment 12a with a narrower rectangular cross-section and a second, lower waveguide segment 12b with a significantly wider rectangular cross-section. The example of FIG. 5 differs from that of FIG. 4 only in that no further planarization coat 13 is provided here. It should be noted that the waveguide 12 in the embodiment according to FIG. 2 could alternatively be embodied, for example, as a so-called slot waveguide with two waveguide segments spaced apart from each other to form a slot or gap.

[0205] If a waveguide 12 comprises more than one segment 12a, 12b, it can apply that all segments are made of the same material, as is the case here. However, this need not necessarily apply; the segments may also comprise different materials or consist of different materials.

[0206] In the examples shown in FIGS. 2, 4 and 5, the graphene film 16 of the respective electro-optical device 15 extends above a longitudinal section of the waveguide 12 visible in the figures in each case. This can also be readily seen from the top view shown in FIG. 3. In the examples according to FIGS. 2 and 4, the graphene film or one graphene film 16, 16a is in each case fabricated on or provided on the side 14 of the further planarization coat 13 facing away from the wafer 1. As can be seen, the graphene film 16 extends here in each case in the region of the trapezoidal section of the further planarization coat 13 on the latter, in particular due to the resist planarization. In the example shown in FIG. 5, the graphene film 16 is located directly on the waveguide 12.

[0207] FIGS. 6 and 7 show examples in which, in deviation from FIGS. 2, 4 and 5, the graphene film 16 extends not above but inside (FIG. 6) or below (FIG. 7) the respective waveguide 12. As far as the shape of the waveguides 12 is concerned, these are again formed as ridge waveguides 12 with a T-shaped cross-section.

[0208] Thereby, the waveguide 12 of the example of FIG. 6 comprises a first, upper waveguide segment 12a, a middle 12b and lower waveguide segment 12c. All of the waveguide segments 12a, 12b, 12c have a rectangular cross-section, with the middle and lower segments 12b, 12c being noticeably wider. The middle waveguide segment 12b is provided on the graphene film 16 and serves both as a passivation coat for it and as the waveguide segment 12b (may also be referred to as a waveguide slab). In the present case, the segment 12b also serving as a passivation coat is made of aluminium oxide. Alternatively or additionally, it may also comprise or consist of dichalcogenides and/or dichalcogenide heterostructures and/or SiO.sub.2 and/or boron nitride. The two further segments 12a, 12c can, for example, also consist of or comprise aluminium oxide or also titanium dioxide.

[0209] The example in FIG. 7 differs from that in FIG. 6 in that there is no lower waveguide segment 12c. The graphene film 16 is arranged here directly on the side 11 of the planarization coat 10 facing away from the wafer 5.

[0210] In particular in the case of an electro-optical device embodied as a photodetector 15, two gate electrodes can also be assigned to the active element 16. These are then preferably embodied and arranged in such a way that the charge carrier concentration in the active element, in this case graphene film 16, can be adjusted via them and thus, for example, a pn-junction can be obtained. The gate electrodes can, for example, be arranged above the graphene film 16 and electrically insulated from it via a dielectric coat.

[0211] The modulators 15 according to FIGS. 8, 10 and 11 each comprise two active elements, specifically a lower 16a and an upper 16b, which are each provided by a film 16 of graphene. It is true for the modulators 15 as well that the active elements can also be embodied differently, for example as films comprising or consisting of at least one other material. The two graphene films 16a, 16b extend at a distance from each other and are not in electrical contact with each other. Rather, they are electrically insulated from each other by an intermediate coat 17 of a dielectric material, preferably an oxide or nitride, presently aluminium oxide. The dielectric coat 17 also serves as a passivation and as an etching protection or stop. As comparison of FIGS. 2 and 6 shows, the arrangements are identical except that the modulator 15 of FIG. 8 comprises a second active element 16b and that the additional dielectric coat 17 is provided.

[0212] The two graphene films 16a, 16b are arranged offset from each other such that they overlie or overlap (without touching) each other in sections. In the overlapping region, it further applies that the two graphene films 16a, 16b or the corresponding section thereof extend at least substantially parallel to each other. It should be noted that, alternatively to the modulator 15 comprising two active elements 16a, 16b, an electrode made of an electrically conductive material, for example copper or aluminium, may be provided instead of one of the active elements.

[0213] In the example shown in FIG. 8, the lower graphene film 16a—just like the single graphene film 16 of the detector of FIGS. 2 and 4—is provided on the side 14 of the further planarization coat 13, again in the region of the trapezoidal section above the waveguide 12. The second, upper graphene film extends on the side 18 of the dielectric coat 17 facing away from the wafer 5.

[0214] In analogy to the various examples from FIGS. 2, 4 and 5, the examples from FIGS. 8, 10 and 11 also differ essentially in that the waveguide 12 is characterized by a different shape and there is no second planarization coat 13, here neither in FIG. 10 nor in FIG. 11. While the example of FIG. 8 comprises a strip waveguide 12, those according to FIGS. 10 and 11 each comprise a ridge waveguide 12 having a T-shaped cross-section or profile. The waveguide in FIG. 10 comprises four waveguide segments 12a, 12b, 12c, 12d, when viewed in cross-section, and the waveguide in FIG. 11 comprises three segments 12a, 12b, 12c. All segments 12a to 12d have a rectangular cross-section, although, as can be seen from the figures, the upper segment 12a—in analogy to FIGS. 4 and 5—has a significantly smaller width than the underlying segments 12b, 12c and, in the case of FIG. 11, 12d. The two or three lower segments 12a, 12b, 12c are each characterized by the same width in the examples shown. Segment 12d of waveguide 12 of FIG. 10 may also be considered and referred to as the waveguide base.

[0215] In the example of FIG. 11, the lower graphene film 16a extends between the single planarization coat 10 here and the segment 12c of the ridge waveguide 12 lying there above, and the upper graphene film 16b extends between the segments 12b and 12c. The upper graphene film 16b thus extends within the waveguide 12. The lower graphene film 16a was fabricated on or provided on the side 11 of the planarization coat facing away from the wafer 5, and the upper graphene film 16b was fabricated on the segment 12c.

[0216] Each of the active elements 16, 16a, 16b of all detectors 15 and modulators 15 of the photonic platform 8 are arranged relative to the respective waveguide 12 identifiable in the figures and associated with them in such a way that they are exposed, at least in sections, to the evanescent field of electromagnetic radiation guided by the respective waveguide 12. Preferably, at least a section of the respective active element 16, 16a, 16b extends at a distance less than or equal to 50 nm, preferably less than or equal to 30 nm from the respective waveguide 12. As can be seen, for example, in FIG. 2, the further planarization coat 13 between the waveguide 12 and the graphene film 16 is correspondingly thin or “thinned out” with respect to its thickness in the remaining region.

[0217] Each of the electro-optical devices, specifically both each photodetector 15 and each modulator 15, in the illustrated embodiments is further electrically conductively connected to at least one of the integrated electronic components 3 of the front-end-of-line 5 of the respective wafer 1. As can be seen in the schematic sectional representations according to FIGS. 2 to 4 as well as 8, 10 and 11, the connection is realized via the VIAs 7 of the back-end-of-line 6 of the wafer 1 as well as further VIAs 7 extending through the planarization coat 10 and possibly further coats or elements.

[0218] Specifically, in the detectors 15, the respective graphene film 16 is electrically conductively connected at opposite end regions via contacts or contact elements 19 to the upper end of VIAs 7, which extend through the planarization coat 10 and possibly further coats or elements to the back-end-of-line 6 of the wafer 1. In the top view from FIG. 3, the VIAs 7 connected to the contact elements 19, which lie below the former, are indicated with a thin line.

[0219] In the modulators 15, each of the two graphene films 16a, 16b is connected to a contact element 19 at one end region and to a VIA 7 thereabove.

[0220] The contacting of an active element, presently graphene film 16, 16a, 16b of an electro-optical device 15 with a contact element 19 can in principle be designed in different ways. FIGS. 12 to 16 show five different possibilities by way of example.

[0221] According to the option shown in FIG. 12, an end region of the graphene film 16, 16a, 16b is in contact with a section of the underside of the contact element 19. Here, the contact element 19 is expediently made of a metal optimized for graphene, for example nickel and/or titanium and/or aluminium and/or copper and/or chromium and/or palladium and/or platinum and/or gold and/or silver.

[0222] The example shown in FIG. 13 differs from the arrangement according to FIG. 10 only in that the contact element 19 comprises not only one, but two metal layers 19a, 19b, whereby a better performance for a further connection can be achieved, since the upper layer 19b can consist of a metal optimized for a further connection. The lower layer 19a, which is in contact with the graphene film 16, 16a, 16b, expediently again consists of a metal optimized for graphene. Preferably, layer 19a consists of nickel and layer 19b consists of aluminium, or layer 19a consists of titanium and layer 19b consists of aluminium. Other combinations of nickel and/or titanium and/or aluminium and/or copper and/or chromium and/or palladium and/or platinum and/or gold and/or silver are also possible, both for active elements comprising or consisting of graphene and comprising or consisting of other electro-optically active materials.

[0223] In the example shown in FIG. 14, the contact element 19 also comprises a third, lower metal layer 19c which serves as a bonding agent. This layer 19c may, for example, consist of titanium or chromium or aluminium oxide. The layer 19a consists of, for example, nickel and/or titanium and/or aluminium and/or copper and/or chromium and/or palladium and/or platinum and/or gold and/or silver. The layer 19b may also consist of one of these metals or a combination thereof.

[0224] In the embodiments according to FIGS. 15 and 16, an end region of the active element, in this case graphene film 16, 16a, 16b, extends between a first, lower metal layer 19a optimized for graphene and a second, upper metal layer 19d of the contact element 19, which is also optimized for graphene. For this purpose, the end region of the active element 16 is characterized by an S-shaped cross section. The two layers 19a and 19d preferably consist of palladium or nickel or gold or platinum or a combination of nickel and/or titanium and/or aluminium and/or copper and/or chromium and/or palladium and/or platinum and/or gold and/or silver.

[0225] The example of FIG. 16 differs from that of FIG. 15 only in that, by analogy with FIG. 14, the contact element 19 comprises a third metal layer 19b which is optimized for further connection and, for example, like the layer 19b of FIG. 13, may consist of aluminium.

[0226] For all contacting examples, the graphene film 16 can be covered by the contact element 19 or a layer 19a to 19d thereof, so that the current passes in a vertical transition from the contact element 19 or a layer thereof into the graphene (top contact), or the graphene film 16 can also end at the edge of the contact element 19 or a layer 19a-19d thereof, so that the current passes laterally into the graphene film 16 (side contact). For example, the arrangement according to FIG. 13 can also be embodied as a top contact.

[0227] A passivation coat 25 is preferably provided above each active element, i.e. preferably above each of the graphene films 16. This can only be seen in FIGS. 12 to 16, which each show a section of a graphene film 16, 16a, 16b in an enlarged view.

[0228] In the present case, the passivation coat 25 is made of aluminium oxide. Alternatively or in addition thereto, such passivation coat 25 may also comprise or consist of dichalcogenides and/or dichalcogenide heterostructures and/or SiO.sub.2 and/or boron nitride. The passivation coat 25 passivates the active elements, in this case the graphene films, and at the same time serves as an etch stop layer, so that selective etching of the contact elements 19 for connection to the VIAs 7 is possible.

[0229] It should be noted that in the case of a modulator 15, the dielectric coat 17 provided between the two active elements 16a, 16b (cf. FIG. 8) can already serve to passivate the lower element 16b. In this case, a passivation coat 25 does not have to be assigned to it as well.

[0230] Furthermore, it should be noted that even if in the examples according to FIGS. 12 to 16 the active elements 16, 16a, 16b are given by graphene films, the embodiments shown are by no means limited to this material. Also for active elements 16 comprising or consisting of one or more other materials, the contacting can be designed accordingly.

[0231] Embodiments of photodetectors 15 or modulators 15 with active elements without graphene are shown in FIGS. 17 to 20.

[0232] In this regard, the embodiment of FIG. 17 comprises an active element 16 formed by a coat of polycrystalline silicon which also forms the waveguide 12. As can be seen, the silicon coat 16 has the shape of a ridge waveguide with a T-shaped cross-section. In the present case, the silicon coat forming the active element 16 and the waveguide 12 has two doped regions, namely a p-doped region 16p and an n-doped region 16n. It should be noted that, alternatively, a pin-transition could also be present, i.e. an undoped region could also lie between the p-doped and the n-doped regions. The silicon coat 6, like the active elements 16 of the examples of FIGS. 2 and 4 to 7, is connected to two contact elements 19. Depending on the polarity of an applied voltage, the charge carrier concentration in the barrier coat changes and thus also the absorption and the refractive index of the waveguide 12. It can also be said that the waveguide 12 is designed as a diode here in order to obtain a modulator.

[0233] FIG. 18 shows another example of a silicon modulator, also known as SISCAP (see also the publication “An efficient MOS-capacitor based silicon modulator and CMOS drivers for optical transmitters,” by M. Webster et el, 11th International Conference on Group IV Photonics (GFP), Paris, 2014, pp. 1-2. doi: 10.1109/Group4.2014.6961998). Here, two active elements 16a, 16b are provided, each formed by a silicon coat, preferably of crystalline silicon or polysilicon or amorphous silicon. Here, the active element 16a is p-doped and the element 16b is n-doped. The active elements 16a, 16b are further arranged offset from one another in such a way that they lie above one another in an overlapping region, this in analogy with the active elements 16 of the examples from FIGS. 8, 10 and 11. The overlapping region here forms the waveguide 12. The charge carrier concentration can be adjusted in this region and thus the optical properties of the waveguide 12.

[0234] FIG. 19 shows another example of a silicon modulator 15, which also comprises two active elements 16a, 16b formed by silicon coats that are p- and n-doped, respectively. These are adjacent to each other in a plane, and an element of electro-optical polymer 26 is provided between them. The two active elements 16a, 16b and the element 29 of an electro-optical polymer form a ridge waveguide 12 with a gap—formed by the element 26. In other words, the sidewalls of the gap serve here as electrodes of a capacitance. The electric field in the gap affects the optical properties of the polymer and enables modulation of an optical signal.

[0235] FIG. 20 shows an example of a modulator with a diode 27 made of compound semiconductors. The diode 27 consists of coats 27a to 27d of different composition, for example InGaAsP, in order to create a pn-junction and two contact regions. The contact regions are connected to the contact elements 19 and thus to integrated electronic components 4 by means of electrodes 28.

[0236] The electro-optical device or at least one electro-optical device—both in the case of a modulator 15 and in the case of a detector 15—may further be designed or fabricated as such with plasmonic coupling.

[0237] Corresponding examples can be found—in each case in purely schematic view—in FIGS. 21 to 23.

[0238] In this regard, FIG. 21 shows an example of a photodetector 15 in which a plasmonic structure 29 consisting of or comprising a plasmonically active material is provided, in concrete terms on the active element 16. In the example, the plasmonic structure 29 comprises three pairs of plasmonic elements 30 arranged next to one another and consisting of or comprising the plasmonically active material. Presently, the plasmonic elements consist of gold. Other suitable examples of materials include silver and/or aluminium and/or copper. The plasmonic elements 30 form quasi antennas on the waveguide 12 to increase absorption (see also Ma et al., “Plasmonically Enhanced Graphene Photodetector Featuring 100 Gbit/s Data Reception, High Responsivity, and Compact Size,” ACS Photonics 2019, 6, pages 154 to 161 (2018)). Such a plasmonic structure may be or become provided, for example, on the active element 16 of an arrangement according to FIG. 2, 4, or 5.

[0239] FIG. 22 shows an example of a photodetector 15 in which no waveguide 12 or section of such a waveguide is provided below or above the active element 16, but in which a waveguide 12 is preferably provided in a plane with the active element 16 and laterally thereto, which waveguide 12 has a section 31 tapering in a V-shape in the direction of the active element 16. The section 31 tapers to a point which extends to the left side of the active element 16, for example graphene film, in FIG. 22. As can be seen, the contact elements 19 here comprise sections 19e which taper in the opposite direction, that is in the direction away from the active element 16. In a manner of speaking, the contact elements 19 follow the tapering end section 31 of the waveguide 12 in sections, which enables plasmonic coupling.

[0240] FIG. 23 shows an analog modulator 15 with plasmonic coupling. As can be seen, waveguide sections 31 tapering in a V-shape in the direction of the active element 16 are provided on two opposite sides of the active element 16, e.g. graphene film, and sections 19e of the contact elements 19 tapering in the opposite direction are provided for both associated waveguide sections 31 and 19e. Thus, coupling of an optical mode to a plasmonic mode and back to an optical mode is possible here. In particular, in this embodiment, it may further be provided that the active element comprises or consists of at least one electro-optical polymer (see also the publication “Silicon-Organic Hybrid (SOH) and Plasmonic-Organic Hybrid (POH) Integration”, by Koos et al, Journal of Lightwave Technology, Vol. 34, No. 2, 2016).

[0241] The photonic platform 8 fabricated on the wafer 1 of a semiconductor device according to the invention will generally comprise a very large number of electro-optical devices 15, which may be given in particular by photodetectors and/or modulators. This is also the case in the illustrated embodiment. In particular, each section of the photonic platform 8 extending above a chip region 4 of the wafer 1 will already comprise a plurality of electro-optical devices 15 and a plurality of waveguides 12. For example, tens, hundreds, or even thousands of electro-optical devices 15 and/or waveguides 12 may be provided on each section of the photonic platform 8 extending above a chip region 4. The number can be selected in each case for the specific application.

[0242] In the illustrated embodiments of semiconductor devices according to the invention, all electro-optical devices 15 and waveguides 12 of the photonic platform 8 are structurally identical. In this respect, the conformity enables a particularly simple, rapid fabrication. It should be emphasized, however, that it is of course also possible for a semiconductor device according to the invention to comprise different ones of the examples shown in FIGS. 2, 4 to 8, 10, 11, and/or 17 to 23, for example both detectors 15 with underlying waveguides 12 according to FIG. 2 and modulators 15 and waveguides 12 according to FIG. 8. There may also be more than two different ones of the examples according to FIGS. 2, 4 to 8, 10, 11, and/or 17 to 23, for example also all of them one or more times, respectively.

[0243] In order to be able to realize arrangements with a further planarization coat 13 (cf. e.g. FIGS. 2, 4 and 8) as well as arrangements without such a coat (cf. e.g. FIGS. 5, 10 and 11) in a photonic platform 8, it can be provided that after the preferably two-dimensional fabrication of the further planarization coat 13, this coat is removed again in sections, e.g. by lithography and subsequent etching, wherever an arrangement without a further planarization coat is desired. For other coats, which are only desired in some places but not everywhere, a completely analogous procedure can be or has been used.

[0244] The active element(s) 16, 16a, 16b of each electro-optical device may be electrically conductively connected to one or, in the case of the detectors, two contact elements 19 in any of the ways shown in FIGS. 12 to 16. It is possible that all active elements 16, 16a, 16b of a semiconductor device according to the invention are contacted with contact elements 19 in the same way. Alternatively, it is of course also possible that different active elements 16 of a device are contacted in different ways.

[0245] In FIGS. 3 and 9, in addition to the active element(s) 16, 16a, 16b, the waveguides 12 and contact elements 19, coupling devices 32 of the photonic platform 8 are schematically indicated, which serve to couple light into or out of the waveguide 12. One of the coupling devices 32 is arranged here at each of the opposite ends of the respective waveguide 12. In the present case, the coupling devices 32 are each designed as side or grating coupling devices. FIGS. 24 to 27 show purely schematic representations of examples of such. FIGS. 24 and 25 show a side coupling device 32 in plan view and in section, and FIGS. 26 and 27 show a grating coupling device 32 in plan view and in section.

[0246] It may be that a coupling device 32 is or two coupling devices 32 are associated with several, possibly also to each of the waveguides 12 of the photonic platform 8. In particular, two coupling devices 32 have been or are associated with a waveguide 12 in the case where light is to be coupled in and out. However, it is also possible that only a possibly initial coupling is desired. Then one coupling device 32 can be sufficient.

[0247] The example of the side coupling device 32 shown in FIGS. 24 and 25 comprises a side coupling element 33 consisting preferably of resins or resin-containing materials, in particular SU8, or/and silicon nitride, or/and silicon oxynitride or dielectrics, whose refractive index lies between that of the waveguide 12 (in particular n=2.4) and that of the element 33 (SU8 n=1.56) serving as a mode field converter, such as aluminium oxide (n=1.68). As can be seen, the latter is characterized by a width b as well as a height h which exceeds the extension of the waveguide 12 in corresponding directions, in the present case corresponding to a multiple thereof in each case. The side coupling device 32 further comprises an end section 34 of the waveguide 12 extending into the side coupling element, which, as can be readily seen in FIG. 24, tapers conically towards its end. It should be noted that in FIG. 24, the outer contour of the tapered section 34 is indicated with a thin line, as it is obscured in plan view by a section of the element 33. The element 33 causes the mode field to be matched from the diameter of an optical fiber (for example, 5 μm to 15 μm in diameter) to the size of the waveguide 12 (for example, 300 nm in height, 1.1 μm in width). The tapered tip 34 of the waveguide 12 causes an adiabatic adjustment of the effective refractive index in the region of the mode field, so that the optical mode is increasingly transferred from the coupling structure into the waveguide 12.

[0248] As can be seen from the top view in FIG. 26, the grating coupling device 32 is formed by an end section 35 of the waveguide 12 which widens conically towards the end and, as it is also well shown in the sectional view in FIG. 27, has a grating structure 36 on its side facing away from the wafer 5. This widening adapts the dimension of the waveguide 12 (e.g. 300 nm height, 1.1 μm width) to the diameter of the mode field in an optical fiber (e.g. 5 μm to 15 μm) and thus increases the coupling efficiency. In the top view according to FIG. 26, the grating structure 36 is only simplified by several parallel lines. The incident light is diffracted by the grating-like arrangement of refractive index steps. The dimensions of the grating are conveniently calculated so that at a given angle of incidence the first diffraction order is located in the waveguide 12 and thus the light is coupled into the waveguide 12.

[0249] The coupling devices 32 lie in one plane with the respective waveguide 12, i.e. they are located on the side 11 of the planarization coat 10 facing away from the wafer 5.

[0250] The waveguides 12, which are shown only in sections in FIGS. 21 to 23 comprising partial views, can also be provided with a coupling device 32 at their ends which cannot be seen.

[0251] In addition to the electro-optical devices 15, the photonic platform 8 may also include one or more optical devices. These may be, for example, one or more interferometers, such as Mach-Zehnder interferometers, and/or MMIs and/or directional couplers and/or ring resonators and/or polarization converters and/or splitters. The optical devices are typically formed by multiple sections of waveguides 12, which are then arranged accordingly. In particular, they constitute passive structures of waveguides 12 or of longitudinal waveguide sections. A section, in particular a section in the longitudinal direction, i.e. a longitudinal section of a waveguide 12, for example the waveguides 12 to be seen in FIGS. 2, 4 to 11, can in each case be a component of such an optical device, specifically a section which lies in front of or behind the electro-optical device 15 in the direction oriented perpendicularly to the drawing plane.

[0252] It is also possible for the photonic platform 8 to include one or more thermo-optical devices. For example, one such device includes a heating element and a longitudinal section of a waveguide 12, the heating element being arranged relative to the waveguide section such that it can heat the waveguide section. Heating the waveguide 12 by means of the heating element can change the refractive index of the waveguide 12 in the longitudinal section. This effect can be used, for example, for phase matching. A thermo-optical device may also be associated with or form part of an interferometer of the photonic platform. For example, a longitudinal section of the waveguide 12 seen in FIGS. 2, 4 to 11 can each be part of a thermo-optical device, again a section that lies in front of or behind the electro-optical device 15 in a direction oriented perpendicularly to the drawing plane.

[0253] The photonic platform 8 further comprises a passivation coat 37 which extends above the electro-optical devices 15 and preferably forms the upper finish of the photonic platform 8 and the semiconductor device (cf. FIG. 1). The passivation 37 simultaneously constitutes a cladding. It should be noted that the passivation coat 37 is not shown in the views according to FIGS. 3 and 9, but only the underlying devices 15.

[0254] To obtain the semiconductor device shown in FIG. 1, in a first step S1 (cf. FIG. 28) the wafer 1 is provided with the integrated circuits comprising the integrated electronic components 3 and the metallization including the VIAs 7. The wafer 1 may be any wafer 1 of conventional type obtained by a previously known manufacturing process.

[0255] Then, the photonic platform 8 is fabricated on the BEOL 6 of the wafer 1.

[0256] Specifically, in a second step S2, the planarization coat 10 is fabricated on the back-end-of-line 6 of the wafer 1. For this purpose, a coating material, in this case silicon dioxide (SiO.sub.2), is applied, which can be done for example by chemical vapor deposition, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition or also by spin-coating with spin-on-glass. In the present case, PECVD is used. After the coating material has been deposited, the side of the coating facing away from wafer 5 is subjected to a planarization treatment (step S3), in this case a resist planarization, whereby a side 11 facing away from wafer 5 is obtained with a roughness of 0.2 nm RMS.

[0257] Resist planarization includes a single or repeated spin-on-glass deposition and subsequent etching, in this case reactive ion etching (RIE). The spin-on-glass coat partially compensates for height differences, i.e. valleys of the topology have a higher coat thickness after spin-on-glass coating than adjacent elevations. If the entire spin-on-glass coat is etched after spin-on-glass coating, for example by RIE, the height difference has been reduced due to the planarizing effect of the spin-on-glass coat. By repetition, the height difference can be further reduced until the desired roughness is obtained.

[0258] It should be noted that a side 11 of the planarization coat 10 facing away from the wafer 5 of a corresponding low roughness can alternatively be obtained, for example, via chemical mechanical polishing (CMP).

[0259] In the next step S4, the waveguides are fabricated. For this purpose, waveguide material, in this case titanium dioxide (TiO.sub.2), is deposited, in particular over the entire surface 11 of the resulting planarization coat 10. As with the planarization coat, the material can be deposited by PVD or CVD, in particular PECVD or LPCVD, or by spin-coating. An atomic layer deposition (ALD) can also be carried out or a transfer print process. In analogy to the planarization coat 10, LPCVD is used. Lithography and structuring, in particular by means of reactive ion etching (RIE), are carried out to obtain the individual waveguides 12.

[0260] To obtain the strip waveguides 12 (see, for example, FIGS. 3 and 8), the waveguide material is completely removed wherever no strip waveguide 12 is to remain, in other words etched down to the underlying coat 10.

[0261] The coupling devices 32 including their waveguide ends 34, 35 belong (cf. FIGS. 3, 9 and 24 to 27) are fabricated in the present case together with the ridge or strip waveguides 12, wherein for the case of ridge waveguides 12 the lateral extension of the waveguide 12 in the region of the coupling point can be removed dry-chemically in a separate etching step. Waveguides 12 consisting of superimposed coats can be structured with the uppermost coat 12a after completion of the coat structure, and for the case of ridge waveguides 12, the lateral extension of the waveguide in the region of the coupling point can be removed dry-chemically in a separate etching step. In all cases, mode converters can be defined between ridge and strip waveguides 12, and sections of the ridge waveguides 12 can be formed as strip waveguides 12 using lithography and RIE.

[0262] Grating couplers 32 with grating structures 36 can be lithographically defined and dry chemically structured.

[0263] For side coupling elements (mode converters) 33, dielectrics and/or semiconductors and/or resins and/or polymers are deposited in one or more layers and structured by means of lithography or/and RIE.

[0264] In a next step S5, the further planarization coat 13 is fabricated on the waveguides 12 and the side 11 of the planarization coat 10. In the present case, this is obtained in a completely analogous manner to the planarization coat 10 by deposition using PECVD and resist planarization. As a result of the resist planarization, the cross-section of the further planarization coat 13 above the waveguide 12 is trapezoidal (see FIG. 2).

[0265] Also with regard to the further planarization coat 13, it applies that alternatively to LPCVD and CMP, other of the above-mentioned processes can be used and another planarization treatment, such as CMP, and/or further planarization is possible, as described above for the planarization coat 10. If CMP is used, a flat surface is generally obtained, i.e., there is then no trapezoidal section above the waveguide 12 as seen in FIG. 2 (and also FIGS. 4 and 9, for example).

[0266] The planarization coat 10 and further planarization coat 13 can comprise one or more cover layers which are preferably provided on the surface subjected to the planarization treatment and which can be, for example, dichalcogenide layers or dichalcogenide heterostructures or also boron nitride layers. These materials are preferably deposited or transferred without the need for further chemical-mechanical polishing or further resist planarization, although it is not excluded that this is repeated again.

[0267] For the sake of completeness, it should be noted that in the event that a semiconductor device according to the invention is also to have regions without a further planarization coat 13, for example also regions in which the structure corresponds to that according to FIG. 5, 10 or 11, the further planarization coat 13 (and any coats located thereon) is subsequently partially removed again, in particular by lithography and etching.

[0268] In step S6, the VIAs 7 are fabricated through the planarization coat 10 and the further planarization coat 13. In principle, this can be done in any way known from the prior art. In particular, the regions in which these are to extend are first defined preferably by lithography and dry-chemically etched by means of RIE. Then metallization is carried out and the metallized surface is structured, for example by means of CMP (Damascene process) or by means of lithography and RIE. It is possible both that the VIAs 7 are fabricated after completion of the further planarization coat 13 through both planarization coats 10, 13 or also that after completion of the first coat 10 sections of the VIAs 7 are fabricated through the first planarization coat 10 and after completion of the second planarization coat 13 sections of the VIAs 7 are fabricated through the second coat 13.

[0269] Subsequently, the electro-optical devices 15 are fabricated.

[0270] For this purpose, in step S7 the respective active elements of the detectors given by the graphene film 16 are provided on the side 14 of the further planarization coat 13 facing away from the wafer 5, for example deposited on the side 14, and then in step S8 the contact elements 19 (single or multilayer) are obtained.

[0271] The deposition of the graphene films 16 can, for example, be carried out via a transfer process as described in more detail above. Then, in particular, a graphene film fabricated on a separate substrate or a separate metal foil or a separate germanium wafer is transferred to the further planarization coat 13 in each case. It is also possible that the graphene films are fabricated directly on the further planarization coat 13. This may include, for example, material deposition.

[0272] If a transfer process is used, it is possible that the passivation coat 25 is already provided on the side of the respective graphene film 16 facing away from the wafer 5, that this layer has been deposited thereon, for example, and is then transferred with it. Alternatively, the passivation coat 25 can also be deposited after transferring or fabricating the graphene film(s) 16.

[0273] It is also possible that first a full-area graphene film and/or a full-area passivation coat is fabricated on the further planarization coat 13, which extend over the entire surface of the further planarization coat 13. In this case, further structuring is then carried out, in particular by lithography and RIE, in order to obtain the individual graphene films 16 as active elements of a plurality of electro-optical devices 16.

[0274] The contact elements 19 or their layers 19a to 19d are then fabricated, preferably by depositing one (FIG. 12) or more layers (FIGS. 13 to 16) of metal over the entire surface and then structuring by means of lithography and RIE.

[0275] In the manner described with the manufacturing sequence of first the graphene films 16 and then contact elements 19, contacting can be achieved as schematically shown in FIGS. 12 to 14.

[0276] For the contacting variants shown in FIGS. 15 and 16, only the lower metal layer 19c or 19a of the contact elements 19 is fabricated first, followed by the graphene films 16 and then the further layer 19b, 19d or the two further layers 19a, 19b or 19d, 19b. This can also be done via full-area deposition of an appropriate metal and subsequent structuring by lithography and RIE.

[0277] In a second to last step S9, the upper passivation 37 is deposited, preferably of Al.sub.2O.sub.3 and SiO.sub.2. In this passivation, openings, in particular to contact elements, are then suitably fabricated by means of lithography and RIE (step S10). Preferably, openings to contact elements, which serve to connect the photonics and/or electronics to the outside, are fabricated.

[0278] By the steps described above, a semiconductor device comprising strip waveguides 12 and electro-optical devices 15 as shown in FIG. 2 can be obtained.

[0279] If a semiconductor device is to be obtained which exclusively—or also additionally—has regions which are constructed as shown in FIG. 4, i.e. which comprise ridge waveguides 12, only step S4 must be varied to the effect that the segments 12a are etched laterally only to a lesser depth so that waveguide material still remains laterally of the segments 12a and the segments 12b, 12c are obtained which the strip waveguides do not have.

[0280] To obtain the structure according to FIG. 5, only the further planarization coat 13 must be removed again in sections before the ridge waveguides 12 are fabricated. If a semiconductor device is to be obtained which does not have a further planarization coat 13 at any point, its fabrication can of course also be dispensed completely.

[0281] To obtain the example shown in FIG. 6, the lower waveguide segment 12c is first fabricated on the side of the planarization coat 10 facing away from the wafer, using the methods described above, e.g. PECVD. Then the active element, in this case the graphene film 16, and the contact elements 19 are fabricated, the order again depending on which of the contacting schemes shown in FIGS. 12 to 16 is chosen. Then the passivation coat 25 is fabricated on the graphene film 16 (shown only in FIGS. 12 to 16) and then the two segments 12b and 12a and the coat 37.

[0282] To obtain the arrangement shown in FIG. 7, a substantially analogous procedure can be followed, omitting only the step of fabricating the waveguide segment 12c and providing the graphene film 16 on the side 11 of the planarization coat 10 facing away from the wafer 5.

[0283] Also for fabricating a semiconductor device according to the invention, which comprises one or more modulators 15 as electro-optical devices, the procedure is partly different from that described above in connection with FIG. 2.

[0284] For the example according to FIG. 8, for example, up to the fabrication of the further planarization coat 13 and the VIAs 7 by the planarization coat 10 and this 13, the procedure can in principle be the same, i.e. steps S1 to S6 can be identical.

[0285] However, the fabrication of the respective modulator(s) 15 then comprises first providing the one, lower graphene film 16a as one of the two active elements on the further planarization coat 13 and producing only one contact element 19 at its one end region pointing to the left in FIG. 8. The fabrication can be carried out in the same way as described above in connection with FIG. 2 for the one graphene film 16 and the two contact elements 19.

[0286] Subsequently, the dielectric coat 17 is provided, for example by deposition preferably of aluminium oxide. It is also possible that the dielectric coat 17 is provided by a transfer process.

[0287] The second, upper graphene film 16b is then fabricated, and the second contact element 19 is fabricated at its end region pointing to the right in FIG. 6. The production can again be carried out in the same way as described above in connection with FIG. 2 for the one graphene film 16 and the two contact elements 19.

[0288] Then, steps S8 and S9 described above can follow to obtain the upper passivation 37 and the openings therein.

[0289] For the structure according to FIG. 10, steps S1 to S6 can also be carried out identically and then the further planarization coat 13 can be partially removed again. Alternatively, their production, i.e. step S5, can be omitted and only VIAs can be fabricated through the planarization coat 10 in step S6.

[0290] Then, on the side 11 of the planarization coat 10 facing away from the wafer 5, the segment 12d, i.e. the waveguide base, is fabricated by depositing an optically transparent, preferably dielectric coat or semiconductor and structuring it by means of lithography and RIE. In the present case, TiO.sub.2 is deposited.

[0291] On the side of the waveguide base 12d facing away from the wafer 5, the lower graphene film 16a and then the contact element 19 belonging to it are fabricated, on top of this the waveguide segment 12c, above this the upper graphene film 16b with associated contact element 19, on top of this the waveguide segment 12b and on top of this the waveguide segment 12a, which is characterized by a significantly smaller width than the other segments 12b, 12c, 12d. The material for the waveguide segment 12b can be fabricated, for example, by means of ALD or by a chalcogenide coat obtained by CVD or transfer and ALD, and/or by a coat of dielectric or semiconducting material fabricated by means of PVD and structured by lithography and RIE. Subsequently, segment 12a is provided, wherein, by means of ALD and/or PVD and/or PECVD and/or LPCVD, a dielectric or semiconducting material and/or a dichalcogenide coat obtained by CVD or transfer is provided and structured using lithography and RIE.

[0292] The graphene films 16a, 16b and contact elements 19 can be fabricated in the same manner as described above in connection with FIG. 2.

[0293] In this example, the upper graphene film 16 extends within the waveguide 12.

[0294] Finally, steps S9 and S10 can be performed, again to obtain the passivation coat 37 and openings therein.

[0295] In order to obtain the arrangement according to FIG. 11, it is possible to proceed mostly in the same way as described above in connection with FIG. 10, with the only difference that the fabrication of the lowest waveguide segment 12d in FIG. 10 is omitted and the lower graphene film 16a is fabricated directly on the side 11 of the planarization coat 10.

[0296] To obtain the arrangement according to FIG. 17, the same procedure can be followed again until the completion of the planarization coat 10 (steps S1 to S3). On its side 11 facing away from the wafer 5, the silicon coat 16 is then fabricated as an active element. This may again include material deposition, such as via one of the aforementioned processes, for example a CVD or PVD process or spin-coating, and subsequent structuring (e.g. lithography and RIE) to obtain the T-shape. The obtained ridge waveguide is p-doped on its one side and n-doped on its other side to obtain the 16p and 16n regions. In this way, the pn-junction is obtained. Then the contact elements 19 can be fabricated.

[0297] For the modulator 15 shown in FIG. 18, which is designed as a so-called SISCAP, the steps S1 to S3 can again be identical and then the two silicon coats 16a and 16b, each forming an active element, are fabricated, which can also include a material deposition, for example via one of the aforementioned processes, for example a CVD or PVD process or spin-coating, and a subsequent structuring (e.g. lithography and RIE), and the associated contact elements 19 are fabricated.

[0298] For FIG. 19, it is possible to proceed in principle as for FIG. 17, with the addition of the element 26 made of an electro-optical polymer between the two elements 16a and 16b.

[0299] To obtain the modulator 15 according to FIG. 20, the steps S1 to S5 can be identical as described above in connection with FIG. 2. On the side 14 of the further planarization coat 13 facing away from the wafer 5, the first electrode 28 with associated contact element 19 can then be fabricated, then the diode 27 with coats 27a to 27d and then the second electrode 28 with associated contact element 19, whereby this can in each case include material deposition and subsequent structuring.

[0300] Finally, in all of the examples of FIGS. 17 through 20, the coat 37 may be prepared in a manner analogous to the remaining examples.

[0301] As can be seen from the above, the photonic platform 8 is fabricated directly on the BEOL 6 of the wafer 1. It can also be said to be monolithically fabricated on wafer 1, or to be a monolithic platform 8. In particular, the coats 10, 13, 37 and the waveguides 12 are fabricated directly on the wafer 1 by respectively depositing appropriate material on the BEOL 6 of the wafer 1, or on coats already fabricated thereon. There is no separate fabrication of the coats 10, 13, 37 or waveguides 12 and subsequent connection by bonding.

[0302] It should be noted that the above-described methods for manufacturing semiconductor devices according to the invention are embodiments of the method according to the invention.

[0303] After completion of a semiconductor device according to the invention, a plurality of chips with integrated photonics can be obtained from it in a simple and fast way, specifically by mere dicing, in other words fragmenting.

[0304] In the semiconductor device shown in FIG. 1, dicing can be performed, which includes, for example, (laser) cutting and/or sawing and/or breaking along the shown lines defining the chip regions 4. In principle, dicing can be performed in any manner known from the prior art, in particular as in the prior art for conventional wafers 1.

[0305] FIG. 29 shows, by way of example and purely schematically, three chips with integrated photonics obtained by such dicing in plan view. These represent embodiments of semiconductor apparatuses 38 according to the invention. Each of these semiconductor apparatuses 38 comprises a chip 39, the extent of which corresponds to a chip region 4 of the wafer 1, and a section 40 of the photonic platform 8 lying above it, the lateral extent of which due to the dicing coincides at least substantially with the lateral extent of the chip 39 lying below. The chip 39 and the above lying section 40 of the photonic platform 8 can be taken from the purely schematic sectional view shown in FIG. 30.

[0306] It should be noted that in this highly simplified illustration, only the two superimposed regions defined by the chip 39 and photonics 40 are indicated, but not coats and components thereof.

[0307] The chip 39 comprises, inter alia, a plurality of integrated electronic components 3, such as transistors and/or capacitors and/or resistors, which may be, for example, parts of a processor of the chip 39, and the section 40 of the photonic platform 8 comprises, inter alia, a plurality of electro-optical devices 15, such as may be taken in particular from FIGS. 2 to 11, and 17 to 23.

[0308] The semiconductor apparatuses 38 obtained by dicing a semiconductor device according to the invention, each of which represents a bare chip with monolithically integrated photonics, can then be inserted into packages, as is known from conventional bare chips, and used for further applications.

[0309] The photonic platform section 40 may be used, for example, to convert electrical signals from the integrated electrical components of the chip 39 into optical signals so that, for example, communication with other chips and/or other integrated electronic components 4 of the apparatus 38 may be accomplished by optical means. For this purpose, for example, light may be modulated by a modulator 15 coupled to an integrated electronic component, such as transistor 4, and the modulated light signal may be received, for example, by a photodetector 15 coupled to another integrated electronic component, such as transistor 4 of the same or a different chip.