METHOD FOR MANUFACTURING AN ELECTRO-OPTICAL DEVICE AND ELECTRO-OPTICAL DEVICE

Abstract

The present application relates to a method for manufacturing an electro-optical device, wherein a waveguide (3) is provided (S1), a planarization coat (7) overlapping at least a section of the waveguide (3) is fabricated (S2), the planarization coat (7) is provided with a spin-on-glass coating (9) (S3), at least in the region of the spin-on-glass coating (9), a preferably dry chemical etching treatment is carried out (S4), optionally, the steps of providing the planarization coat (7) with a spin-on-glass coating (9) and the etching treatment are repeated at least once (S5, S6), and an active element (10) is provided (S7) on or above the planarization coat (7) and above the waveguide (3).

Claims

1. Method for manufacturing an electro-optical device, in particular a photodetector (6) or electro-optical modulator (6), wherein a waveguide (3) is provided (S1), a planarization coat (7) overlapping at least a section of the waveguide (3) is fabricated (S2), preferably by applying, in particular depositing, a coating material, the planarization coat (7) is provided with a spin-on-glass coating (9) (S3), at least in the region of the spin-on-glass coating (9), a preferably dry chemical etching treatment is carried out (S4), in the course of which etching is preferably carried out down to the planarization coat (7) and preferably the spin-on-glass coating (9) and part of the planarization coat (7) are removed, optionally, the steps of providing the planarization coat (7) with a spin-on-glass coating (9) and the etching treatment are repeated at least once (S5, S6), and an active element (10) is provided (S7) on or above the planarization coat (7) and above the waveguide (3), which active element (10) comprises or consists of at least one material, which absorbs electromagnetic radiation of at least one wavelength and generates an electric photosignal as a result of the absorption and/or whose refractive index changes as a function of a voltage and/or the presence of charge(s) and/or an electric field.

2. Method according to claim 1, wherein obtaining an electro-optical modulator (6) as the electro-optical device, the following steps are further performed: a dielectric coat (17) is fabricated on the active element (10), preferably a dielectric coat (17) comprising or consisting of at least one oxide and/or nitride, particularly preferably comprising or consisting of aluminium oxide and/or silicon nitride and/or hafnium oxide, and on the upper side of the dielectric coat (17) facing away from the active element (10) a further active element (10) is provided, the further active element (10) preferably being arranged offset with respect to the active element (10) in such a way that the active element (10) and the further active element (10) lie one above the other in sections.

3. Method according to claim 1, wherein the active element (10) is provided on or above the upper side of the planarization coat (7) by applying, in particular depositing, at least one suitable material, or in that the active element (10) is provided on the upper side of the planarization coat (7) by means of a transfer process.

4. Method according to claim 1, wherein a film is provided as active element (10), and/or in that wherein as the at least one material of the active element (10), which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption and/or whose refractive index changes as a function of a voltage and/or the presence of charge(s) and/or an electric field, graphene and/or at least one dichalcogenide, in particular two-dimensional transition metal dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or lithium niobate and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor, is used.

5. Method according to claim 1, wherein the planarization coat (7) is fabricated by applying, in particular depositing, coating material at least on or above a section of the waveguide (3) and on regions laterally of the waveguide (3).

6. Method according to claim 1, wherein the planarization coat (7) is fabricated by depositing coating material by means of chemical vapor deposition, preferably low-pressure chemical vapor deposition, and/or by means of plasma-assisted chemical vapor deposition, and/or by means of physical vapor deposition.

7. Method according to claim 1, wherein a planarization coat (7) comprising or consisting of at least one oxide, in particular silicon dioxide, and/or comprising or consisting of at least one nitride and/or com-prising or consisting of at least one polymer is fabricated.

8. Method according to claim 1, wherein the etching treatment is carried out in such a way that the etching rate for the material of the planarization coat (7) is greater or smaller than the etching rate for the spin-on-glass by a maximum of 50%, preferably a maximum of 30%, particularly preferably a maximum of 10%.

9. Method according to claim 1, wherein the electro-optical device (6) is fabricated on or above a wafer (4) or on or above a chip, and preferably the provided waveguide (3) is arranged on or above the wafer or chip, wherein the wafer (4) or chip particularly preferably comprises integrated circuits with integrated electronic components (13).

10. Electro-optical device (6) obtained by the method according to claim 1.

11. Semiconductor apparatus comprising a chip and at least one, preferably a plurality of electro-optical devices (6) according to claim 10.

12. Semiconductor device comprising a wafer (4) and at least one, preferably a plurality of electro-optical devices (6) according to claim 10.

13. Method according to claim 2, wherein the active element (10) is provided on or above the upper side of the planarization coat (7) by applying, in particular depositing, at least one suitable material, or in that the active element (10) is provided on the upper side of the planarization coat (7) by means of a transfer process.

14. Method according to claim 2, wherein a film is provided as active element (10), and/or wherein as the at least one material of the active element (10), which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption and/or whose refractive index changes as a function of a voltage and/or the presence of charge(s) and/or an electric field, graphene and/or at least one dichalcogenide, in particular two-dimensional transition metal dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or lithium niobate and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor, is used.

15. Method according to claim 2, wherein the planarization coat (7) is fabricated by applying, in particular depositing, coating material at least on or above a section of the waveguide (3) and on regions laterally of the waveguide (3).

16. Method according to claim 3, wherein the planarization coat (7) is fabricated by applying, in particular depositing, coating material at least on or above a section of the waveguide (3) and on regions laterally of the waveguide (3).

17. Method according to claim 4, wherein the planarization coat (7) is fabricated by applying, in particular depositing, coating material at least on or above a section of the waveguide (3) and on regions laterally of the waveguide (3).

Description

[0094] With respect to embodiments of the invention, reference is also made to the subclaims and to the following description of several embodiments with reference to the accompanying drawing.

[0095] In the drawing shows:

[0096] FIG. 1 a waveguide arranged on a wafer in purely schematic sectional representation;

[0097] FIG. 2 the waveguide from FIG. 1 with the planarization coat fabricated thereon;

[0098] FIG. 3 the waveguide from FIG. 1 with a planarization coat and a spin-on-glass coating on the planarization coat;

[0099] FIG. 4 the arrangement of FIG. 3 after a RIE etching treatment;

[0100] FIG. 5 the arrangement from FIG. 4 with a further spin-on glass coating fabricated after the etching process on the planarization coat;

[0101] FIG. 6 the arrangement of FIG. 5 after another RIE etching;

[0102] FIG. 7 a SEM image of an arrangement corresponding to FIG. 2;

[0103] FIG. 8 a SEM image of the arrangement in FIG. 7 after a single resist planarization treatment;

[0104] FIG. 9 a SEM image of the arrangement shown in FIG. 8 after a second resist planarization treatment;

[0105] FIG. 10 a SEM image of the arrangement in FIG. 9 after a third resist planarization treatment;

[0106] FIG. 11 the arrangement of FIG. 6 with a graphene film provided on the planarization coat;

[0107] FIG. 12 the arrangement of FIG. 11 with contact and interconnection elements;

[0108] FIG. 13 a top view of the graphene film, the contact elements and the waveguide from FIG. 12;

[0109] FIG. 14 an arrangement corresponding in large parts to the arrangement in FIG. 12 with an electro-optical device according to the invention in the form of a modulator comprising two graphene films;

[0110] FIG. 15 another arrangement corresponding to the arrangement in FIG. 4, in which a ridge waveguide is provided instead of a strip waveguide; and

[0111] FIG. 16 a block diagram showing the steps of an embodiment of the method according to the invention.

[0112] All figures show purely schematic representations. In the figures, the same components or elements are marked with the same reference signs.

[0113] FIG. 1 shows a partial sectional view through a coat of SiO.sub.2 1, on the upper side 2 of which, pointing upwards in the figure, a waveguide 3 is arranged. The SiO.sub.2 layer is located on a wafer 4 which is not visible in FIG. 1 but is shown in FIG. 12.

[0114] In the embodiment shown, a plurality of waveguides 3 are arranged on the upper side 2 of the coat 1 for which one waveguide 3 is shown as an example in FIG. 1. In particular, dielectrics, preferably titanium dioxide, which was also used in the illustrated embodiment, are suitable as waveguide materials, although this is to be understood as exemplary. As far as the dimensions of the waveguide(s) 3 are concerned, it is preferred that their thickness is in the range from 150 nanometers to 10 micrometers and their width and length are in the range from 100 nanometers to 10 micrometers. The exemplary waveguide 3 shown in FIG. 1 is 300 nm thick, has a width of 400 nm and is characterized by a length—oriented perpendicular to the drawing plane—of 5 micrometers.

[0115] The coat 1 consisting of SiO.sub.2 is also to be understood purely exemplary. A coat of another material could also be provided on the wafer 4, for example. The waveguides 3 could also be arranged directly on the upper side 5 of the wafer 4, which faces upwards in FIG. 12.

[0116] Electro-optical devices 6, specifically photodetectors or modulators, are to be fabricated for several of the waveguides 3, which is possible by carrying out the embodiment of the method according to the invention described below. The fabrication of the electro-optical devices 6 is described in part by way of example using the one waveguide 3 shown in FIG. 1.

[0117] After providing the wafer 4 with the waveguides 3 (step S1), a planarization coat 7 is fabricated in a second step S2, which planarization coat 7 extends at least over a section of the respective waveguide 3 and on two opposite sides beyond the respective waveguide 3. In the example described here, a planarization coat 7 extending over the entire upper surface 2 of the coat 1 provided on the wafer 4 is fabricated. This extends correspondingly over and between all waveguides 3 arranged on the upper side 2, so that this requirement is fulfilled. As can be seen in FIG. 2, which shows the arrangement obtained following the fabrication of the planarization coat 7—in the same partial section as in FIG. 1—exemplarily for the one waveguide 3, there is material of the planarization coat 7 both on and to both lateral sides of the waveguide 3.

[0118] To obtain the planarization coat 7, a coating material, in this case silicon dioxide (SiO.sub.2), is applied, which can be done, for example, by chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition or also atomic layer deposition (ALD) or sputtering. In the present case, PECVD is used. FIG. 7 shows a scanning electron microscope (SEM) image of an arrangement as shown in purely schematic sectional view in FIG. 2. The SEM image shows the thickness of the planarization coat 7, which—with slight variation in the lateral direction—is about 1.1 μm, both in the region above the waveguide 3 and on both lateral sides of it.

[0119] After the coating material is deposited, the upper side of the obtained planarization coat 7 is subjected to a planarization treatment.

[0120] For planarization, the planarization coat 7 is first provided with a spin-on-glass coating 9 on its upper side facing away from the waveguide 2 (step S3). For this purpose, a suitable material, in this case hydrogen silsesquioxane (HSQ), is spun onto the planarization coat 7 in the liquid state and then heated. During annealing, the material vitrifies, hence it is called spin-on-glass.

[0121] Due to the kinetics of liquid materials at height differences, a planarization effect results. The HSQ coat thickness is lower on an elevation on the surface, in this case the waveguides 3, than next to them. This effect can be seen well in FIG. 3, which shows the arrangement from FIG. 2 with the spin-on-glass coating 9 fabricated. The thickness of the coating above the waveguide 3 is less than laterally of the waveguide 3.

[0122] In a next step S4, an etching treatment is carried out, specifically a CHF3-based dry chemical etching, in this case RIE. In this step, etching is performed down to the planarization coat 7 and the spin-on-glass coating 9 is completely removed and the planarization coat 7 is partially removed.

[0123] In a preferred embodiment, the etching treatment is carried out in such a way that the etching rate for the spin-on-glass coating 9 is greater than or less than the etching rate for the planarization coat by a maximum of 50%, in particular by a maximum of 30%, preferably by a maximum of 10%. Exemplary values for etch rates are about 45 nm/min for HSQ and 33 nm/min for SiO.sub.2. Suitable parameters for setting the etching process are, as it is known to the skilled person, for example pressure and/or the composition of the gas mixture and/or the power for exciting the plasma and/or DC voltage as well as temperature of the electrode.

[0124] The removing depth above the waveguide 3 coincides with or is similar to the removing depth in regions adjacent to the waveguide 3. Since the coat thickness of the spin-on-glass coating 9 was thinner above the respective waveguide 3 than next to it (cf. FIG. 3), more of the underlying planarization coat 7 is being removed above the respective waveguide 3 than next to it as a result. In other words, the uneven distribution of the spin-on-glass is specifically used to reduce the thickness of the planarization coat 7 on the waveguide 3 more than next to it. Since in the example shown, due to the kinematics in the liquid state, a spin-on-glass coating 9 with a lower thickness compared to regions lying next to the respective waveguide 3 results, it applies to all waveguides 3.

[0125] The result, in particular the lower coat thickness above the waveguide 3, can be seen—purely schematically—in FIG. 4, which shows the arrangement from FIG. 3 after the etching treatment. The spin-on-glass coating 9 has been completely removed and the planarization coat 7 only partially. FIG. 8 shows an SEM image of the arrangement in FIG. 7 after a corresponding etching treatment. As can be seen, in this example the remaining coat thickness of the planarization coat 7 above the waveguide 3 is only 581.2 nm compared to a larger coat thickness of 742.9 nm next to it.

[0126] If necessary, the steps of providing the planarization coat 7 with a spin-on-glass coating 9 and etching treatment can be repeated one or more times to obtain an even flatter topology.

[0127] Thus, in a step S5, a further spin-on-glass coating 9 can be provided on the planarization coat 7, in particular in the same way as the first spin-on-glass coating 9. FIG. 5 shows the arrangement of FIG. 4 with a renewed spin-on-glass coating 9 fabricated following the (first) etching process.

[0128] A new etching (step S6), preferably with the same parameters as in step S4, leads to the arrangement shown in FIG. 6 as a result. As can be seen, the thickness of the planarization coat 7 on the waveguide 3 is less than in FIG. 4.

[0129] FIGS. 9 and 10 show SEM images of the arrangement of FIG. 8 after a second and third pass of the steps of providing the planarization coat 7 with a spin-on-glass coating 9 and subsequent etching. The coat thickness of the planarization coat 7 on the waveguide 3 continues to decrease, in FIG. 9 it is still 97.40 nm and in FIG. 10 it is almost zero or zero.

[0130] After the above described planarization treatment with only one or also two or more passes of spin-on-glass coating 9 and subsequent etching, in a next step (presently step S7 after a repetition) an active element 10 is provided on the planarization coat 7 and above the waveguide 3, which active element 10 comprises or consists of at least one material which absorbs electromagnetic radiation of at least one wavelength and generates an electric photosignal as a result of the absorption and/or whose refractive index changes as a function of a voltage and/or the presence of charge(s) and/or an electric field.

[0131] In the described embodiment, a graphene film 10 is deposited as an active element on the planarization coat 7 and above the respective waveguide 3, presently by means of a transfer process as described in more detail above. In this case, in particular, a graphene film 10 fabricated on a separate substrate or a separate metal foil or a separate germanium wafer is transferred to the further planarization coat 13 above the (respective) waveguide 3. It is also possible that one or more graphene films 10 are fabricated directly on the further planarization coat 13, each above a waveguide. This may include, for example, material deposition and, if necessary, subsequent structuring.

[0132] Typical dimensions for active elements are in the range from 5 to 500 μm length on the waveguide along the propagation direction of the light (orthogonal to the drawing plane of FIGS. 1 to 12, 14 and 15) and 1 to 50 μm width across the propagation direction.

[0133] The respective graphene film 10 is arranged relative to the respective waveguide 3 such that it is exposed, at least in sections, to the evanescent field of electromagnetic radiation that is or may be guided by the respective waveguide 3.

[0134] It is expedient to subsequently fabricate contact elements 11 for the respective graphene film 10 (step S8), via which a connection to interconnection elements, specifically VIAs (Vertical Interconnect Access) 12, is achieved, which extend through the planarization coat 7, the SiO.sub.2 coat 1 and sections of the wafer 4. The contact elements 11 can also be seen in the top view in FIG. 13. The contact elements 11 are fabricated in the present case by depositing at least one metal over the entire surface and then structuring by means of lithography and RIE. Exemplary metals for the contact elements 11 are nickel and/or titanium and/or aluminium and/or copper and/or chromium and/or palladium and/or platinum and/or gold and/or silver. Within the scope of the structuring, contact elements 11 can be fabricated for a plurality of graphene films 10.

[0135] It should be noted that it is also possible in principle for the contact elements 11 to be fabricated first, possibly only partially, such as at least a first layer or first layers of such, and then the or the respective graphene film 10 to be provided.

[0136] Via the contact elements 11 and the VIAs 12, an electrical connection of the graphene film 10 with integrated electronic components 13 of the wafer 4 can be realized. The VIAs 12 are shown only in FIG. 12, in which the wafer with the integrated electronic components 13 can also be seen. The components 13, which preferably comprise transistors and/or capacitors and/or resistors, are indicated in the purely schematic FIG. 12 only in simplified form by a line with hatching provided with the reference sign 13. The components 13 are located in a front-end-of-line (FEOL) 14 of the wafer 4 in a sufficiently known manner. Above this is the back-end-of-line (BEOL) 15, in which or via which the integrated electronic components 13 are interconnected by means of various metal planes. The integrated electronic components 13 in the FEOL 14 and the associated interconnection including the VIAs 12 in the BEOL 15 form integrated circuits of the wafer 4. The integrated circuits extend in a semiconductor substrate, in this case a silicon substrate 16, of the wafer 4.

[0137] It should be noted that the VIAs 7 or sections thereof extending through the wafer 4 and the SiO.sub.2 coat 1 thereon were already present in the wafer 4 and the SiO.sub.2 coat 1 when they were provided in the first step. The VIAs 12 or sections thereof extending through planarization coat 7 are or were conveniently fabricated together with planarization coat 7. The fabrication may be carried out in any manner known in the prior art. In particular, regions in which they are to extend can preferably be defined by lithography and dry-chemically etched by means of RIE. Subsequently, metallization can be carried out and the metallized surface can be structured, for example by means of CMP (Damascene process) or by means of lithography and RIE.

[0138] As a result, one or more electro-optical devices—in the case of the example according to FIG. 11 with a graphene film 10—a photodetector is obtained which, in addition to the graphene film 10, comprises the underlying longitudinal section of the waveguide 3. The graphene film 10 and underlying waveguide 3 can also be taken from the purely schematic top view shown in FIG. 13. As can be seen, the longitudinal extent of waveguide 3 here is significantly greater than the longitudinal extent of graphene film 10.

[0139] Optionally, it is possible that an electro-optical device 6 is provided which is characterized by a plasmonic coupling or realizes such a coupling. Then, expediently, at least one plasmonic structure 17 consisting of or comprising a plasmonically active material, preferably gold and/or silver and/or aluminium and/or copper, is provided on or above the or at least one active element 10. The plasmonic structure 17 may then comprise one or more pairs of plasmonic elements 18 arranged next to one another and consisting of or comprising the plasmonically active material. The plasmonic elements may be characterized by a section tapering in the direction of the other plasmonic element, as can be seen—purely by way of example—in FIG. 13. The plasmonic elements 18, of which six pieces 8 (three pairs) are provided here, have a triangular shape. Resonant density fluctuations in the plasmonic structure 17 are excited by the optical mode in the waveguide 3. This collective motion of electron distribution is referred to as plasmon and propagates in the plasmonic structure 17. Characteristics include a higher electric field strength compared to the optical mode. This results in a stronger absorption in graphene 10 or generally in an absorbing material.

[0140] A passivation coat 19 can be provided above the electro-optical device(s). This can be used to protect the arrangement or circuit from environmental influences, in particular water. It should be noted that the passivation 19 is not shown in the top view according to FIG. 13, but only the underlying arrangement.

[0141] In particular, in order to obtain a modulator, two active elements 10 or one active element 10 and one electrode can also be provided on the respective waveguide 3. The first variant is exemplarily shown in the purely schematic FIG. 14.

[0142] For a modulator, the above steps S1 to S7 can be identical, in which case the active element provided in step S7, preferably also a graphene film 10, represents the lower film 10 in FIG. 14.

[0143] Then, in step S8, only one contact element 11 is fabricated for the lower graphene film 10.

[0144] In a step S9, a dielectric coat 18 is fabricated on the lower graphene film 10, preferably comprising or consisting of at least one oxide and/or nitride, particularly preferably aluminium oxide and/or silicon nitride and/or hafnium oxide. In the present case, a dielectric coat 18 is fabricated of aluminium oxide. This can be done—in analogy to planarization coat 7—by deposition, for example by means of one of the deposition processes mentioned for the latter. It is possible that the dielectric coat 18 is fabricated over the entire wafer 4.

[0145] In a step S10, the or—in the case that a modulator 6 is fabricated for several of the waveguides 3—the respective further active element, in this case the (respective) further graphene film 10, can then be provided on the dielectric coat above the (respective) waveguide 3. The further graphene film 10 is thereby arranged offset to the first, lower graphene 10 in such a way that the lower graphene film 10 and the further, upper graphene film 10 lie in sections one above the other, in other words overlap in sections. As can be seen from FIG. 14, the overlapping region is located above the waveguide 3 and is similar in width to the waveguide 3. The second graphene film 10 may have the same extension as the first one.

[0146] In FIG. 16, all steps S1 to S10 are shown schematically. This shows both the steps for obtaining a photodetector (ending with step S8) and the steps for obtaining a modulator (all steps S1 to S10).

[0147] Finally, the contact element 11 for the further, upper graphene film 10 can be fabricated, preferably in the same way as the one for the lower film 10.

[0148] The wafer 4 with the electro-optical devices 6 fabricated thereon is an embodiment of a semiconductor device according to the invention.

[0149] It should be noted that one or more of the waveguides 3, alternatively to being formed as a strip waveguide 3 with a rectangular cross-section as shown in FIGS. 1 to 14, can also be formed, for example, as a ridge waveguide 3 with a T-shaped cross-section comprising a first, upper section 3 with a narrower rectangular cross-section and a second, lower section 3b with a significantly wider rectangular cross-section. FIG. 14 shows—purely schematically and by way of example—an arrangement corresponding to FIG. 6 with a ridge waveguide 3.

[0150] It is possible that the wafer 4 on which a plurality of electro-optical devices 6 have been fabricated in the manner described above is subsequently diced. In this way, a plurality of chips with integrated circuits can be obtained, each comprising at least one, preferably a plurality of electro-optical devices, in particular photodetectors 6 and/or modulator 6, which have been fabricated in the manner according to the invention.

[0151] The “bare chips” with electro-optical devices obtained by dicing can then be inserted into packages and put to further use, as it is already known from conventional bare chips.

[0152] A chip with electro-optical devices obtained by dicing the semiconductor device with the wafer 4 and the electro-optical devices 6 is an embodiment of a semiconductor apparatus according to the invention.

[0153] It should be noted that all partial sectional views show only a comparatively very small section, specifically a section showing only a small part of a chip region 4 or a chip obtained after dicing. All partial sections thus represent sections through both an embodiment example of a semiconductor apparatus according to the invention and an embodiment example of a semiconductor device according to the invention. Furthermore, it should be noted that a plurality of electro-optical devices 6 can already be provided above a single chip region 4 or chip, for example several tens, several hundreds or even several thousands, depending on the case of application.