Drain extended CMOS with counter-doped drain extension

Abstract

An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Claims

1. A method of fabricating an integrated circuit, comprising the step of: forming a drift region between a gate and a drain of a DEMOS transistor; wherein at least 10 percent of a length of said drift region between said gate and said drain consists of a concentration of a first dopant type plus a concentration of scattering centers; and wherein said concentration of said scattering centers is greater than said concentration of said first dopant type divided by 5.

2. The method of claim 1, wherein said concentration of said scattering centers is a dopant of a second dopant type.

3. The method of claim 2, wherein said concentration of said first dopant type is an n-type dopant in the range of 1E15/cm.sup.3 to 1E18/cm.sup.3 and wherein said second dopant type is a p-type dopant with a concentration between 0.2 and 0.9 of said first dopant type concentration.

4. The method of claim 3, wherein said concentration of said n-type dopant is about 5E16/cm.sup.3 and wherein said concentration of said second dopant type is about 3E16/cm.sup.3.

5. The method of claim 1, wherein said concentration of said scattering centers is silicon, germanium, or carbon.

6. The method of claim 5, wherein said concentration of said first dopant is between 1E15/cm.sup.3 to 1E18/cm.sup.3 and wherein said concentration of said scattering centers is between 1E15/cm.sup.3 to 1E18/cm.sup.3.

7. The method of claim 6, wherein said concentration of said first dopant is about 2E16/cm.sup.3 and wherein said concentration of said scattering centers is about 6E16/cm.sup.3.

8. The method of claim 1, wherein a first portion of said concentration of said scattering centers are a second dopant type, wherein a concentration of said second dopant type is between 0.2 and 0.9 times the said concentration, and wherein a second portion of said scattering centers are at least one of silicon, germanium, and carbon.

9. A method of fabricating an integrated circuit, comprising the step of: forming a gate of a DEMOS transistor over a substrate; forming a source and drain of the DEMOS transistor in the substrate; forming a drift region the DEMOS transistor between the gate and drain by: implanting a first dopant type into a region of the substrate; and adding a concentration of scattering centers by counterdoping the region with a second dopant type, wherein at least 10 percent of a length of said drift region between said gate and said drain consists of a concentration of a first dopant type plus a concentration of scattering centers; and wherein said concentration of said scattering centers is greater than said concentration of said first dopant type divided by 5.

10. The method of claim 9, wherein said concentration of said first dopant type is an n-type dopant in the range of 1E15/cm.sup.3 to 1E18/cm.sup.3 and wherein said second dopant type is a p-type dopant with a concentration between 0.2 and 0.9 of said first dopant type concentration.

11. The method of claim 9, wherein said concentration of said n-type dopant is about 5E16/cm.sup.3 and wherein said concentration of said second dopant type is about 3E16/cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a cross-sectional view of a diode according to an embodiment of the invention.

(2) FIG. 2 shows a dopant profile of a conventional diode.

(3) FIG. 3 shows a dopant profile of a diode according to an embodiment of the invention.

(4) FIG. 4 shows a cross-sectional view of DEMOS transistor according to an embodiment of the invention.

(5) FIG. 5 is a graph of carrier mobility vs dopant density.

(6) FIG. 6 is a graph of resistivity of a semiconductor vs the breakdown voltage for several doping and counterdoping concentrations.

(7) FIG. 7 shows a dopant profile of a conventional DENMOS.

(8) FIG. 8 shows a dopant profile of a DENMOS according to an embodiment of the invention.

(9) FIG. 9 is a cross-sectional view of a vertical DEMOS transistor according to an embodiment of the invention.

(10) FIG. 10 is a flowchart illustrating a method for designing a counterdoped DEMOS transistor according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

(11) The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.

(12) This invention involves adding scattering centers into the depletion region of a diode where the peak electric field forms to reduce the mean free path of the carriers and raise the breakdown voltage, Vb, of the diode. This enables a higher voltage to be applied to the diode or enables the diffusion doping to be increased thus reducing the resistance.

(13) The term scattering centers refers to atoms within a semiconductor that reduce the mean free path of carriers within the semiconductor. These may include interstitial and non interstitial atoms. For example, interstitial silicon, germanium, arsenic, and indium atoms may reduce the mean free path of carriers in a silicon semiconductor.

(14) An example diode 1000 is shown in FIG. 1. A reverse biased pn diode with a positive voltage applied n-doped diffusion is used for illustration, but a reverse biased pn diode with a negative voltage applied to the p-doped diffusion may be used as well. The pn diode may be formed on a p-type substrate 1006 by implanting an n-type dopant such as phosphorus or arsenic to form n-doped regions 1014 and 1018 on top of the p-doped substrate 1006. N-doped region 1014 may be a lightly doped region with approximately 1E+16/cm.sup.3 donor (n-type) dopants and highly doped region 1018 may have approximately 2E+20/cm.sup.3 donor (n-type) dopants. The p-type region 1006 may also consist of a highly doped (about 2E+20/cm.sup.3 acceptor dopants) region and lightly doped (about 1E+16/cm.sup.3 acceptor dopants) region or it may consist of a highly doped or medium doped (1E18/cm.sup.3 acceptor dopants) region. In FIG. 1 a medium doped p-type region 1006 is used for illustration. A pn junction 1010 forms where the silicon changes from p-type to n-type. When a voltage 1020 is applied across the pn junction 1010, a depletion region 1022, across which the voltage is dropped, forms. The depletion region 1022 is essentially devoid of carriers. A small reverse bias current flows within the depletion region due to spontaneous electron hole pair production, but these carriers are immediately swept out of the depletion region by the applied electric field. The electrons are accelerated toward the positive terminal 1020 and the holes are accelerated toward the negative or ground terminal 1002. If the applied voltage 1020 is sufficiently high the carriers which are accelerated by the electric field and may gain sufficient energy to cause impact ionization. Impact ionization occurs when an energetic electron upon impact, imparts sufficient energy to a covalent bonded electron to raise that electron from the valence band into the conduction band. At high electric fields, impact ionization may cause the number of carriers in the conduction band to multiply rapidly resulting in high current, high heat generation, and diode breakdown. The voltage at which this occurs is the diode breakdown voltage, Vb.

(15) The width of the depletion region (WD) 1020 is determined by the n-type, and p-type doping. Since an equal number of active carriers are removed from both the n-type, 1012, and p-type, 1008, portions of the depletion regions, their width are equal if the n-type and p-type doping is equal. If the n-type and p-type doping is not equal, the depletion width of the more lightly doped region is larger, since it requires more volume to remove an equal number of carriers.

(16) The doping profile for a convention diode is illustrated in FIG. 2. The doping profile 2002 in FIG. 2 corresponds to p-type doped region 1006 in FIG. 1. The doping profile 2003 in FIG. 2 corresponds to n-type doped region 1014 and doping profile 2006 corresponds to n-type doped region 1018. Note that the n-type donor concentration is approximately 2E16 in region 2004 and p-type acceptor concentration is less than 1E14. The critical field for this diode is approximately 0.4 MV/cm and the resistivity is about 0.45 m*cm.

(17) One way to increase Vb is to reduce the doping. For example, if the doping of the p-type region 1006 is reduced, the width of the p-type depletion region 1008 is increased and the applied voltage 1018 is dropped across a wider depletion region. This reduces the electric field gradient and therefore reduces the acceleration of the carriers in the depletion region. One problem with reducing doping is that resistance is increased. If the pwell resistance is increased in an integrated circuit, more substrate contacts may be required causing an increase in integrated circuit area which negatively impacts die cost.

(18) According to one embodiment of the invention, the series resistance of a diode may be reduced while maintaining the breakdown voltage by increasing the net (donor minus acceptor) doping and by reducing the mean free path with additional scattering centers. The mean free path of an electron being accelerated must be sufficient for it to gain enough kinetic energy to cause impact ionization. When the mean free path is reduced, a higher voltage gradient is required for the electron to gain sufficient kinetic energy to cause impact ionization in the shorter distance. One method of reducing the mean free path is by adding scattering centers to the depletion region 1022 in FIG. 1, using counterdoping. The reduction of the mean free path enables an increase in the net doping producing a reduction series resistance while keeping the breakdown voltage the same.

(19) An example doping profile to illustrate this embodiment is shown in FIG. 3. In doping region 3004, the donor concentration is raised from 1E16/cm.sup.3 to approximately 5E16/cm.sup.3 (when compared with the donor doping in FIG. 1) and the acceptor concentration is raised from less than 1E14/cm.sup.3 to approximately 3E16/cm.sup.3. The total doping (donor concentration plus the acceptor concentration) is raised to about 8E16/cm.sup.3 whereas the net doping (donor concentration minus the acceptor concentration) is raised from 1E16/cm.sup.3 to 2E16/cm.sup.3. Increasing the number of scattering centers from approximately 1E16/cm.sup.3 to approximately 8E16/cm.sup.3 raises the critical field at which impact ionization begins from approximately 0.4 MV/cm to approximately 0.57 MV/cm. Additionally, the depletion region 1022 resistance is lowered from about 0.45 m*cm to about 0.25 m*cm. In an example embodiment, the counterdoping acceptor concentration may be between 0.2 and 0.9 times the donor concentration.

(20) The critical field may be increased even higher by increasing total (donor plus acceptor) dose while adjusting the net (donor minus acceptor) dose accordingly. The maximum manufacturable amount of counter doping may be determined by the control of the doping levels in an implanter or in an epi reactor.

(21) A second method of reducing the mean free path is to add scattering centers to the depletion region 1020 by implanting neutral species such as silicon, germanium or carbon while still maintaining the same active doping concentration. For example, approximately 6E16/cm.sup.3 germanium atoms may be added by ion implantation to raise the scattering center concentration from approximately 1E16/cm.sup.3 to approximately 8E16/cm3. This increase in scattering center concentration may raise the critical field at which impact ionization avalanche begins from approximately 0.4 MV/cm to approximately 0.57 MV/cm. This method is not limited by implanter control so higher scattering center levels may be achieved adding neutral species.

(22) Adding scattering centers by counter doping or by adding neutral species may be performed separately or counterdoping plus added neutral species may be implemented together.

(23) Raising the critical field raises the breakdown voltage, Vb. Vb may be reduced to the original low scattering center value by increasing the doping which has the added advantage of reducing diode resistance.

(24) Another embodiment may be to raise the voltage handling capability of a DEMOS transistor or to improve the performance of a DEMOS transistor.

(25) The term drift region refers to the region in a lightly doped drain extension which is charge neutral at low drain voltages but gets depleted at high drain voltages. In an extended drain MOS transistor (DEMOS), the voltage drop across this depleted region enables a low voltage transistor to switch a high voltage.

(26) An example horizontal DENMOS transistor 4000 in FIG. 4 is used to illustrate the embodiment. Lightly doped drain extension drift region 4018 depletes when a high voltage is applied to the drain contact 4020, dropping sufficient voltage across the extended drain 4018 to prevent damage to the low voltage gate oxide 4016. The DENMOS transistor 4000 is built in p-type substrate 4002 and includes shallow trench isolation 4006, a pwell 4004, a lightly doped p-type region 4022, a p+ substrate contact 4008, an n doped source lightly doped source extension 4012, an n+ doped source diffusion 4010, a transistor gate 4014 with sidewalls 4013, and an n+ doped drain diffusion 4020.

(27) The length and doping of the drift region 4018 is determined by the voltage to be dropped between the heavily doped drain diffusion 4020 and the transistor gate 4014. The doping must be light enough so that the drain extension fully depletes and long enough so that sufficient voltage is dropped before the depletion region reaches the n+ doped drain diffusion 4020. Lighter doping and a longer drain extension both add series resistance resulting in performance degradation.

(28) An example doping profile for a conventionally designed DENMOS transistor is shown in FIG. 7. The doping profile 7020 represents the doping in the transistor channel 4024, the doping profile 7030 represents the doping in the drift region 4018, and the doping profile 7040 represents the doping in the drain 4020. Note that the n-type (donor) concentration in the drift region 7030 is in the 1E16/cm.sup.3 range whereas the p-type (acceptor) concentration orders of magnitude less (less than 1E14/cm.sup.3).

(29) Resistance, Rs, of the drain extension 4018 is inversely proportional to the carrier mobility and is inversely proportional to the active doping concentration. As shown in FIG. 5, the doping density may be increased to the mid 10.sup.16 range with little negative impact on mobility. FIG. 6 is a plot of Rs versus Vb of the drain extension for different levels of counterdoping. At a constant resistivity of 0.1 m*cm, Vb may be increased from about 20 volts 6004 to about 30 volts 6002 by changing the doping from approximately 4E16/cm.sup.3 phosphorus to about 1.5E17/cm.sup.3 phosphorus counter doped with 9E16/cm.sup.3 boron or, at a constant Vb of 20 volts 6004, Rs may be reduced from 0.1 m*cm 6008 to about 0.04 m*cm 6006.

(30) As mentioned previously, the increase in scattering centers reduces the mean free path of the carriers, resulting in an increase in Vb. In addition to counter doping, an increase in scattering centers may be achieved by implanting neutral species such as Si, Ge, or C into the drain extension. The addition of scattering centers may be accomplished by counterdoping, by adding neutral species, or by a combination of counterdoping plus the addition of neutral species.

(31) The dopants in a counter doped drain extension may be introduced by ion implantation or may be introduced during epitaxial growth. An embodiment of adding scattering centers to improve Vb of a DEMOS is illustrated using FIG. 4. The breakdown voltage, Vb, of the extended drain drift region 4018 may be increased by adding scattering centers either through counterdoping, by implanting neutral scattering centers such as Si, Ge, or C, or by a combination of counterdoping and implanting neutral scattering centers. The preferred method for adding scattering centers to the extended drain is with ion implantation, however, another option may be to etch the silicon from the extended drain area and epitaxially regrow the silicon with a counter doped profile.

(32) The doping profile of a counterdoping embodiment is shown in FIG. 8. The doping profile 8030 of drift region 4018 is shown to consist of approximately 5.0E16/cm.sup.3 n-type (donor) atoms and approximately 3.0E16/cm.sup.3 p-type (acceptor) atoms. In contrast to FIG. 7, where the total doping (donor plus acceptor) in the drift region is approximately equal to the net doping (donor minus acceptor) concentration of 1E16/cm.sup.3, in this example embodiment the total doping is equal to approximately 8.0E16/cm.sup.3 whereas the net doping is equal to 2E16/cm.sup.3. This 8-fold increase in concentration of scattering centers raises the critical field from approximately 0.4 MV/cm to approximately 0.57 MV/cm. The lower series resistance may allow the designer to reduce the length of the drift region reducing area and cost of the DEMOS and improving performance.

(33) Another example embodiment showing a pseudo-vertical DENMOS is shown in FIG. 9. In this vertical DENMOS, a high voltage may be applied to the n+ drain 9002 and the voltage dropped across the n+ substrate 9004 and the n doped extended drain 9006. The transistor gate 9008 turns on the nmos transistor between the extended drain 9006 and the n+ source 9010. The doping profile in the extended drain drift region 9006 may be precisely controlled during the epitaxial growth of this layer. A counter-doped extended-drain drift region 9006 may be formed with a significantly higher breakdown voltage, Vb, than a non counter-doped extended-drain drift region. Additional neutral scattering centers such as Si, Ge, and C may be added to region of peak electrical field in the extended drain drift region 9006 with ion implantation to additionally raise Vb.

(34) The invention is illustrated using horizontal and vertical DENMOS transistors, but horizontal and vertical DEPMOS transistors may also benefit from the instant invention. The design of the DEMOS examples is for illustrative purposes only. Many other DEMOS transistor designs may also be used.

(35) A method for the design of a DEMOS counter-doped extended-drain drift region is given in FIG. 10. Step one 9050 is to determine the breakdown voltage, Vb, required for the DEMOS. This breakdown voltage may also be referred to as BVdss. Step two 9052 is to select the type of DEMOS device to be formed.

(36) The vertical DEMOS device 9054 design procedure is described in steps 9056 through 9064. An DENMOS device is used for illustration, but a DEPMOS device may equally well be used.

(37) Step 9056 is to first determine the doping capability of the epi reactor to control the net doping (donor minus acceptor) concentration and the total doping (donor plus acceptor) concentration within the device specification limits.

(38) In step 9058, the acceptor counderdoping concentration is chosen based upon the epi reactor capabilities and the device voltage requirements.

(39) The donor concentration may then be calculated in step 9070 using empirical equations linking the breakdown voltage, Vb, to the doping concentration N.sub.D. (S. M. Sze, Physics of semiconductor devices, John Wiley & Sons, Inc., 1981, pp 100-102)

(40) $\mathrm{Vb}\frac{130E_{\mathrm{crit}}^2}{\left(N_D-N_A\right)}$
E.sub.crit, the maximum electric field at breakdown is approximately given by

(41) $E_{\mathrm{crit}}\frac{0.4}{1-\frac{1}{3}\log \left(N_D+N_A\right)}$
These equations may be inverted and approximately solved for N.sub.D as in the following equation:

(42) $N_D\frac{400E_{\mathrm{crit}}^{1.5}}{V_b^{1.5}}+N_A\left(1+\frac{10E_{\mathrm{crit}}}{V_b}\right)$

(43) In step 9062, the manufacturability is checked by determining if the control of the donor and acceptor dopants is sufficient to keep the net doping, donor minus acceptor concentration, within specification limits. If manufacturability limits are not met it may be necessary to choose a lower counter-doping acceptor concentration 9072, and repeat steps 9058, 9070, and 9062. If, on the other hand, the manufacturability criteria are met, two choices are possible: 1. If there is more than ample manufacturing margin, it may be desirable to use some of the margin to additionally increase the counterdoping concentration to additionally improve Vb. In this case, the donor concentration may be increased 9060 and steps 9058, 9070, and 9062 may be repeated; 2. If the manufacturing margin is acceptable, proceed to step 9064.

(44) If the manufacturability criteria are met, the approximate thickness required for the epi layer may be determined by calculating the approximate width of the depletion region, WD, in step 9064 using an equation such as:

(45) $\mathrm{WD}\frac{2.6}{\left(N_D-N_A\right)\left[1-\frac{1}{3}\log \left(N_D+N_A\right)\right]}$
The thickness of the epi layer may be approximately 1.1 times the calculated WD.

(46) This completes the design of the extended drain drift region for a vertical DENMOS. The remaining regions of the DENMOS may be simulated in step 9076.

(47) The design of a lateral DEMOS transistor 9066 is illustrated in steps 9068 through 9074 in the example embodiment. A lateral DENMOS is used for illustration, but a lateral DEPMOS may also be used.

(48) Step 9068 determines the doping capability of the implanter to control the net doping (donor minus acceptor) and total doping (donor plus acceptor) concentrations within the device specification limits.

(49) In step 9058, the acceptor counderdoping concentration is chosen based upon the implanter capabilities and the device voltage requirements.

(50) The donor concentration is then calculated in step 9070 as is described above for a vertical DENMOS transistor 9054.

(51) In step 9062, the manufacturability is checked by determining if the control of the donor and acceptor concentrations is sufficient to keep the net doping, donor minus acceptor concentration, within specification limits. If manufacturability limits are not met it may be necessary to choose a lower counter-doping acceptor concentration 9072, and repeat steps 9058, 9070, and 9062. If, on the other hand, the manufacturability criteria are met, two choices are possible: 1. If there is more than ample manufacturing margin it may be desirable to use some of the margin to additionally increase the counter doping concentration to additionally improve Vb. In this case the donor concentration may be increased 9060, and steps 9058, 9070, and 9062 may be repeated; 2. If the manufacturing margin is acceptable, proceed to step 9074.

(52) If the manufacturability criteria are met, the approximate length required for the extended drain drift region may be determined by calculating the width of the depletion region, WD, as is previously described for vertical DENMOS transistor, 9064. The extended drain drift region length may be approximately 1.1 times the calculated WD.

(53) The above method and equations within the embodiment are given to illustrate the embodiment and not intended to limit the method. For example, other more or less detailed equations or simulation software may be used to calculate the N.sub.D, WD, and Vb. In addition, the embodiment technique may be used to design counterdoped drift regions in diodes and other types of transistors.

(54) While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.