Semiconductor apparatus

Abstract

A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n.sup.+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n.sup.-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n.sup.-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

Claims

1. A semiconductor apparatus comprising: an active region formed on a first main surface side; a peripheral region encircling the active region and having a termination; a low-resistance layer formed on a second main surface side; a parallel pn-layer formed between the first main surface and the low-resistance layer and composed of planar first-conductive regions of a first conductivity alternately arranged with planar second-conductive regions of a second conductivity, the parallel pn-layer surrounding the active region and comprising a first sub-region, serving substantially as a region of the first conductivity, being a region of the parallel pn-layer in the peripheral region that extends from the first main surface to a partial depth of the parallel pn-layer, being a region in which the first-conductive regions are wider than adjacent second-conductive regions in a plan-view cross-section, and being a region encircling the active region, and a second sub-region, serving substantially as a region of the second conductivity, being a region of the parallel pn-layer in the peripheral region that extends from the first main surface to a partial depth of the parallel pn-layer, being closer to the active region than is the first sub-region, being a region in which the second-conductive regions are wider than adjacent first-conductive regions in the plan-view cross-section, and being a region encircling the active region and being encircled by the first sub-region; an insulating layer covering the parallel pn-layer in the peripheral region; a first conductive layer covering part of the parallel pn-layer that is closer to the active region in the peripheral region via the insulating layer; and a second conductive layer connected electrically to the termination of the peripheral region and covering part of the parallel pn-layer that is closer to the termination in the peripheral region via the insulating layer, the second sub-region extending from a position that is closer to the termination than the first conductive layer is, to a position under the first conductive layer, and the first sub-region extending from a position that is closer to the active region than the second conductive layer is, to a position under the second conductive layer.

2. The semiconductor apparatus of claim 1, wherein in the second sub-region, a ratio of the second-conductive regions to the first-conductive regions is constant.

3. The semiconductor apparatus of claim 1, wherein in the first sub-region, a ratio of the second-conductive regions to the first-conductive regions is constant.

4. The semiconductor apparatus of claim 1, wherein in the second sub-region, the ratio of the second-conductive regions to the first-conductive regions decreases approaching 1 as the second sub-region comes closer to the termination in peripheral region.

5. The semiconductor apparatus of claim 1, wherein in the first sub-region, the ratio of the second-conductive regions to the first-conductive regions increases approaching 1 as the first sub-region comes closer to the active region.

6. The semiconductor apparatus of claim 1, wherein a region serving substantially as a charge balance region is present between the second sub-region and first sub-region.

7. The semiconductor apparatus of claim 6, wherein a width of the region serving substantially as the charge balance region is one-third or less the distance between the first conductive layer and the second conductive layer.

8. The semiconductor apparatus of claim 1, wherein the first conductive layer or the second conductive layer is formed into a stepped shape having one level difference.

9. The semiconductor apparatus of claim 1, wherein the first conductive layer or the second conductive layer is formed into a stepped shape having two level differences.

10. The semiconductor apparatus of claim 1, wherein the first conductive layer or the second conductive layer is formed into a stepped shape having three or more level differences.

11. The semiconductor apparatus according to claim 1, wherein the first-conductive regions and the second-conductive regions respectively have a stripe planar shape or, either the first-conductive regions or the second-conductive regions have a square or polygonal planar shape.

12. The semiconductor apparatus according to claim 1, wherein, in the plan-view cross-section, a first series of longitudinal sections, of the second-conductive regions, that are within the second sub-region have increased widths, which are greater than widths of adjacent members of the first-conductive regions and greater than that of longitudinal sections of the second-conductive regions outside the second sub-region, the first series of longitudinal sections having increased widths are in a circular formation that encircles the active region, a second series of longitudinal sections, of the first-conductive regions, that are within the first sub-region have increased widths, which are greater than widths of adjacent members of the second-conductive regions and greater than that of longitudinal sections of the first-conductive regions outside the first sub-region, and the second series of longitudinal sections having increased widths are in a circular formation that encircles both the active region and the first sub-region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and/or other aspects and advantages will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

(2) FIG. 1 is a top view of a semiconductor apparatus of a first embodiment.

(3) FIG. 2 is a horizontal sectional view of the semiconductor apparatus of the first embodiment.

(4) FIG. 3 is a vertical sectional view along an A-A line of FIG. 1 of the semiconductor apparatus of the first embodiment.

(5) FIG. 4 is a vertical sectional view along a B-B line of FIG. 1 of the semiconductor apparatus of the first embodiment.

(6) FIG. 5 is a top view of a semiconductor apparatus of a second embodiment.

(7) FIG. 6 is a horizontal sectional view of the semiconductor apparatus of the second embodiment.

(8) FIG. 7 is a vertical sectional view along an A-A line of FIG. 5 of the semiconductor apparatus of the first embodiment.

(9) FIG. 8 is a vertical sectional view along a B-B line of FIG. 5 of the semiconductor apparatus of the second embodiment.

(10) FIG. 9 is a diagram of the simulation results of surface charge dependency on breakdown voltage in the semiconductor apparatus of the second embodiment.

(11) FIG. 10 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the second embodiment.

(12) FIG. 11 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the second embodiment.

(13) FIG. 12 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the second embodiment.

(14) FIG. 13 is a top view of a semiconductor apparatus of a third embodiment.

(15) FIG. 14 is a horizontal sectional view of the semiconductor apparatus of the third embodiment.

(16) FIG. 15 is a vertical sectional view along an A-A line in FIG. 13 of the semiconductor apparatus of the third embodiment.

(17) FIG. 16 is a vertical sectional view along a B-B line in FIG. 13 of the semiconductor apparatus of the third embodiment.

(18) FIG. 17 is a vertical sectional view of a semiconductor apparatus of a fourth embodiment.

(19) FIG. 18 is a vertical sectional view of a semiconductor apparatus of a fourth embodiment.

(20) FIG. 19 is a diagram of the simulation results of surface charge dependency on breakdown voltage in the semiconductor apparatus of the fourth embodiment.

(21) FIG. 20 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the fourth embodiment.

(22) FIG. 21 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the fourth embodiment.

(23) FIG. 22 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the fourth embodiment.

(24) FIG. 23 is a vertical sectional view of a semiconductor apparatus of a fifth embodiment.

(25) FIG. 24 is a vertical sectional view of the semiconductor apparatus of the fifth embodiment.

(26) FIG. 25 is a vertical sectional view if a semiconductor apparatus of a sixth embodiment.

(27) FIG. 26 is a vertical sectional view of the semiconductor apparatus of the sixth embodiment.

(28) FIG. 27 is a top view of a semiconductor apparatus of a seventh embodiment.

(29) FIG. 28 is a vertical sectional view along an A-A line in FIG. 27 of the semiconductor apparatus of the seventh embodiment.

(30) FIG. 29 is a vertical sectional view along a B-B line in FIG. 27 of the semiconductor apparatus of the seventh embodiment.

(31) FIG. 30 is a diagram of the simulation results of surface charge dependency on breakdown voltage in the semiconductor apparatus of the seventh embodiment.

(32) FIG. 31 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the seventh embodiment.

(33) FIG. 32 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the seventh embodiment.

(34) FIG. 33 is a diagram of electric potential distribution in the off-state for the semiconductor apparatus of the seventh embodiment.

(35) FIG. 34 is a top view of a semiconductor apparatus of an eighth embodiment.

(36) FIG. 35 is a vertical sectional view along an A-A line in FIG. 34 of the semiconductor apparatus of the eight embodiment.

(37) FIG. 36 is a vertical sectional view along a B-B line in FIG. 34 of the semiconductor apparatus of the eighth embodiment.

(38) FIG. 37 is a top view of a semiconductor apparatus of a ninth embodiment.

(39) FIG. 38 is horizontal sectional view of the parallel pn-layer of the semiconductor apparatus of the ninth embodiment.

(40) FIG. 39 is a vertical sectional view along an A-A line of FIG. 38 of the semiconductor apparatus of the ninth embodiment.

(41) FIG. 40 is a schematic diagram of electric potential distribution in the off-state for the semiconductor apparatus of the ninth embodiment.

(42) FIG. 41 is a schematic diagram of electric potential distribution in the off-state for the semiconductor apparatus of the ninth embodiment.

(43) FIG. 42 is a schematic diagram of electric potential distribution in the off-state for the semiconductor apparatus of the ninth embodiment.

(44) FIG. 43 is a top view of a semiconductor apparatus of an eleventh embodiment.

(45) FIG. 44 is a top view of a semiconductor apparatus of a twelfth embodiment.

(46) FIG. 45 is a top view of a semiconductor apparatus of a thirteenth embodiment.

(47) FIG. 46 is a plane figure of a semiconductor apparatus of a fourteenth embodiment.

(48) FIG. 47 is a plane figure of the semiconductor apparatus of the fourteenth embodiment.

(49) FIG. 48 is a plane figure of a semiconductor apparatus of a fifteenth embodiment.

(50) FIG. 49 is a plane figure of the semiconductor apparatus of the fifteenth embodiment.

(51) FIG. 50 is a plane figure of a semiconductor apparatus of a sixteenth embodiment.

(52) FIG. 53 is a plane figure of the semiconductor apparatus of the seventeenth embodiment.

(53) FIG. 54 is a diagram of simulation results of surface charge dependency on breakdown voltage in a conventional semiconductor apparatus.

(54) FIG. 55 is a diagram of electric potential distribution in the off-state for the conventional semiconductor apparatus.

(55) FIG. 56 is a diagram of electric potential distribution in the off-state for the conventional semiconductor apparatus.

(56) FIG. 57 is a diagram of electric potential distribution in the off-state for the conventional semiconductor apparatus.

DESCRIPTION OF EMBODIMENTS

(57) Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures.

(58) In the present specification and the accompanying drawings, layers and regions accompanied by n or p represent layers and regions in which electrons or positive holes serve as majority carries. + or appended to n or p means high impurity concentration or low impurity concentration, respectively, indicating that a layer or region accompanied by + or is higher or lower in impurity concentration than a layer or region not accompanied by + or . In the description of the following embodiments and the accompanying drawings, a constituent element common to multiple embodiments will be denoted by the same reference numeral in each of the embodiments, and overlapping description will be omitted.

First Embodiment

(59) FIG. 1 is a top view of a semiconductor apparatus of a first embodiment. FIG. 2 is a horizontal sectional view of the semiconductor apparatus of the first embodiment. FIG. 3 is a vertical sectional view along an A-A line in FIG. 1 of the semiconductor apparatus of the first embodiment. FIG. 4 is a vertical sectional view along a B-B line in FIG. 1 of the semiconductor apparatus of the first embodiment. FIGS. 1 and 2 depict one-fourth of the semiconductor apparatus (FIGS. 5, 6, 13, 14, 27, 34, 37, 38, and 43 to 53 depict the same). FIG. 1 depicts the respective shapes of a parallel pn-layer, an n-channel stopper region, a p-base region at the outermost location of the active region, and p-guard ring regions at a first main surface (FIGS. 5 and 13 depict the same). FIG. 2 depicts shapes along a section that crosses the parallel pn-layer at both active region and peripheral region, for example, shapes along a section at a depth half of the parallel pn-layer of the active region (FIGS. 6, 14, and 46 to 53 depict the same).

(60) As depicted in FIGS. 1 to 4, the semiconductor apparatus includes the active region 1 on the first main surface side and an n.sup.+-drain region (low resistance layer) 2 on the second main surface side. Outside the active region 1, the peripheral region 3 is disposed to encircle the active region 1. The active region 1 includes an n.sup.+-source region 4, a p-base region 5, a p.sup.+-contact region 6, a source electrode 7, an inter-layer insulating film 8, a gate insulating film 9, and a gate electrode 10 that are formed on the first main surface side as an element surface structure. A drain electrode 11 is disposed on the second main surface.

(61) A first parallel pn-layer 12 is disposed between the active region 1 and the n.sup.+-drain region 2. The first parallel pn-layer 12 is formed by first n-regions (first regions of a first conductivity) 13 alternating with first p-regions (first regions of a second conductivity) 14 in a repetitive arrangement. The first n-regions 13 and the first p-regions 14 respectively have a planar shape that is of a stripe. The peripheral region 3 has a second parallel pn-layer 15 formed by second n-regions (second regions of the first conductivity) 16 alternating with second p-regions (second regions of the second conductivity) 17 in a repetitive arrangement. The second n-regions 16 and the second p-regions 17 respectively have a planar shape that is of a stripe. The direction of the stripes of the second parallel pn-layer 15 is the same as the direction of the stripes of the first parallel pn-layer 12. A repetition pitch P2 of the second n-regions 16 and second p-regions 17 is narrower than a repetition pitch P1 of the first n-regions 13 and first p-regions 14. A narrow repetition pitch allows a depletion layer to expand easily toward the outer periphery in the parallel pn-layer, facilitating a higher initial breakdown voltage. The second p-regions 17 work in the same manner as a guard ring does until being depleted of carriers, easing an electric field in the second n-regions 16 and thus, facilitating higher breakdown voltage.

(62) An n.sup.-surface region (third region of the first conductivity) 18 is disposed between the second parallel pn-layer 15 and the first main surface. The n.sup.-surface region 18 has an impurity concentration that is lower than that of the first n-regions 13, and has a thickness that is half or less than half the thickness of the first parallel pn-layer 12. The n.sup.-surface region 18 extends up to the part of active region 1 that is adjacent to the peripheral region 3. In the first embodiment, the second parallel pn-layer 15 extends together with the n.sup.-surface region 18 up to a place under the active region 1. The boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15 coincides with the junction between the n.sup.-surface region 18 and the first parallel pn-layer 12. At the junction between the n.sup.-surface region 18 and the first pn-layer 12, charges are imbalanced, which may invite a drop in breakdown voltage. It is desirable, therefore, for the thickness T of the junction between the n.sup.-surface region 18 and the first parallel pn-layer 12 to be half or less than half the thickness of the first parallel pn-layer 12.

(63) On the first main surface side in the n.sup.-surface region 18, plural p-guard ring regions (third regions of the second conductivity) 19, 20, and 21 are formed to be separated from each other. The p-guard ring regions 19, 20, and 21 have an impurity concentration that is higher than the impurity concentration of the n.sup.-surface region 18. For example, adjacent p-guard ring regions 19, 20, and 21 closer to the termination of the peripheral region 3 are separated by an interval of a larger width than adjacent p-guard ring regions 19, 20, and 21 farther away. This is because that an electric field gradually decreases from the outermost active region 1 to the termination of the peripheral region 3. The n.sup.-surface region 18 is covered with an insulating film 22, on which a field plate electrode (first conductive layer) 23 and a channel stopper electrode (second conductive layer) 24 are disposed to be separated from each other. The field plate electrode 23 is connected electrically to the outermost p-guard ring region 19. In the peripheral region 3, an n-channel stopper region 25 is formed. On the first main surface side in the n-channel stopper region 25, a p-region at the termination in peripheral region 26 is formed. The channel stopper electrode 24 is connected electrically to the outermost p-region 26. The number of the p-guard ring regions may be two or three or more. The field plate electrode may be connected electrically to some or all of the p-guard ring regions other than the outermost p-guard ring region.

(64) Although not particularly limited hereto, for example, the semiconductor apparatus of the first embodiment is a vertical 600V MOSFET, the dimensions and impurity concentration of the constituent elements are as follows. The thickness of a drift region (thickness of the first parallel pn-layer 12) is 44.0 micrometers, the width of the first n-region 13 and of the first p-region 14 is 7.0 micrometers (with a repetition pitch P1 of 14.0 micrometers), and the impurity concentration of the first n-region 13 and of the first p-region 14 is 3.0*10.sup.15 cm.sup.3. The width of the second n-region 16 and of the second p-region 17 is 3.5 micrometers (with the repetition pitch P2 of 7.0 micrometers), and the impurity concentration of the second n-region 16 and of the second p-region 17 is 1.0*10.sup.15 cm.sup.3. The impurity concentration of the n.sup.-surface region 18 is 1.0*10.sup.14 cm.sup.3, and the depth of the same is 15 micrometers. The diffusion depth of the p-guard ring regions 19, 20, and 21 is 3.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.17 cm.sup.3. The diffusion depth of the p-base region 5 is 3.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.17 cm.sup.3. The diffusion depth of the n.sup.+-source region 4 is 0.5 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.20 cm.sup.3. The diffusion depth of a surface n-drift region (n-region above a broken line between p-base regions 5 in FIGS. 3 and 4) is 2.5 micrometers, and the surface impurity concentration of the same is 2.0*10.sup.16 cm.sup.3. The thickness of the n.sup.+-drain region 2 is 300 micrometers, and the impurity concentration of the same is 2.0*10.sup.18 cm.sup.3. The width of the n-channel stopper region 25 is 30.0 micrometers, and the impurity concentration of the same is 5.0*10.sup.16 cm.sup.3. The impurity concentration of the outermost p-region 26 is 3.0*10.sup.17 cm.sup.3.

(65) According to the first embodiment, because the p-guard ring regions 19, 20, and 21 are provided, a high electric field near the outermost active region 1 is relaxed when positive charges (positive ions) are present on the oxide film of the peripheral region. This suppresses the fluctuation of breakdown voltage caused by positive charges. Because the channel stopper electrode 24 is provided, depletion layer expansion reaching the n-channel stopper region 25 of the peripheral region 3 is prevented when negative charges (negative ions) are present on the oxide film of the peripheral region, suppressing a drop in breakdown voltage caused by negative charges. Because the second parallel pn-layer 15 is provided, the depletion layer easily expands in the peripheral region 3, easily achieving high breakdown voltage. Because the surface region 18 has an impurity concentration that is lower than the impurity concentration of the first n-regions 13, the depletion layer expands more easily in the peripheral region 3. Hence, high breakdown voltage is achieved more easily. If the thickness of the n.sup.-surface region 18 is half or less than half the thickness of the first parallel pn-layer 12, the thickness of the junction between the n.sup.-surface region 18 and the first parallel pn-layer 12 is small, suppressing a drop in breakdown voltage. Because the impurity concentration of the p-guard ring regions 19, 20, and 21 is higher than that of the n.sup.-surface region 18, a neutral region remains in the p-guard ring regions 19, 20, and 21 when voltage is applied thereto, consequently fixing the electric potential of the p-guard ring regions 19, 20, and 21. As a result, when charges (ions) are present on the oxide film of the peripheral region, the fluctuation of surface electric potential is suppressed, improving the robustness against charges on breakdown voltage. When intervals between the p-guard ring regions 19, 20, and 21 adjacent to each other widen as the intervals come closer to the termination of the peripheral region 3, the high electric field is eased near the outmost active region 1 that is sensitive to charges (ions), thereby improving the robustness against charges on breakdown voltage.

Second Embodiment

(66) FIG. 5 is a top view of a semiconductor apparatus of a second embodiment. FIG. 6 is a horizontal sectional view of the semiconductor apparatus of the second embodiment. FIG. 7 is a vertical sectional view along an A-A line in FIG. 5 of the semiconductor apparatus of the first embodiment. FIG. 8 is a vertical sectional view along a B-B line in FIG. 5 of the semiconductor apparatus of the second embodiment. As depicted in FIGS. 5 to 8, the second embodiment is different from the first embodiment in the following two respects. One respect is that the pitch transition of the parallel pn-layers, i.e., the boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15 is under the n.sup.-surface region 18. The other respect is that the p-guard ring regions 19, 20, and 21 are connected electrically to field plate electrodes 23, 27, and 28, respectively. The field plate electrodes 23, 27, and 28 are formed to extend over each of the p-guard ring regions 19, 20, and 21, respectively, to the n.sup.-surface region 18. This means that each of the field plate electrodes 23, 27, and 28 overhangs toward the inner periphery or the outer periphery from the junction at the first main surface between each of the p-guard ring regions 19, 20, and 21 to which each filed plate electrode is electrically connected and the n.sup.-surface region 18. The number of the p-guard ring regions may be two or three or more. Any one of the p-guard ring regions except the outermost p-guard ring region may be electrically unconnected to the field plate electrode. In other configurative aspects, the second embodiment is substantially identical to the first embodiment.

(67) FIG. 9 is a diagram of the simulation results of surface charges dependency on breakdown voltage in the semiconductor apparatus of the second embodiment. These simulation results are obtained from simulations for a configuration such that four p-guard ring regions are connected electrically to field plate electrodes. As depicted in FIG. 9, breakdown voltage hardly fluctuates even if positive charges (positive ions) or negative charges (negative ions) are present on the oxide film of the peripheral region. This demonstrates that high breakdown voltage is achieved and the robustness against charges on breakdown voltage is improved in the second embodiment.

(68) FIGS. 10 to 12 depict electric potential distributions in off-state for the semiconductor apparatus of the second embodiment. FIG. 10 depicts an electric potential distribution in the case that a surface charge quantity on the oxide film of the peripheral region is 1.0*10.sup.12 cm.sup.2. FIG. 11 depicts an electric potential distribution in the case that the surface charge quantity is 0.0 cm.sup.2. FIG. 12 depicts an electric potential distribution in the case that the surface charge quantity is +1.0*10.sup.12 cm.sup.2. These figures reveal that breakdown voltage is maintained mainly between the field plate electrode and the channel stopper electrode when surface charges are negative charges (negative ions), and that breakdown voltage is maintained mainly by the p-guard ring regions and the filed plate electrode when surface charges are positive charges (positive ions).

(69) The second embodiment offers the same effect as the first embodiment. At the pitch transition of the parallel pn-layers, a drop in breakdown voltage due to charge imbalance easily occurs. If the pitch transition of the parallel pn-layers is under the n.sup.-surface region 18, a depletion layer easily expands at the lower side of the n.sup.-surface region 18, which suppresses a drop in breakdown voltage. Because the p-guard ring regions 19, 20, and 21 are connected electrically to the field plate electrodes 23, 27, and 28, respectively, charges and ions migrating to the peripheral region 3 are collected by the field plate electrodes 23, 27, and 28. As a result, the influence of charges (ions) on breakdown voltage is reduced. If each of the field plate electrodes 23, 27, and 28 is formed to extend over each of the p-guard ring regions 19, 20, and 21 and the n.sup.-surface region 18, each of the field plate electrodes 23, 27, and 28 extending in both directions toward the outer periphery and the inner periphery is connected to each of p-guard ring regions 19, 20, and 21. As a result, the concentration of an electric field on curvature of the p-guard ring regions 19, 20, and 21 is relaxed when positive charges are present on the oxide film of the peripheral region, and the expansion of the depletion layer is prevented when negative charges are present on the oxide film of the peripheral region. Hence breakdown voltage is stabilized.

Third Embodiment

(70) FIG. 13 is a top view of a semiconductor apparatus according to a third embodiment. FIG. 14 is a horizontal sectional view of the semiconductor apparatus according to the third embodiment. FIG. 15 is a vertical sectional view along an A-A line in FIG. 13 of the semiconductor apparatus according to the third embodiment. FIG. 16 is a vertical sectional view along a B-B line in FIG. 13 of the semiconductor apparatus according to the third embodiment. As depicted in FIGS. 13 to 16, the third embodiment is different from the second embodiment in that the direction of the stripes of the second parallel pn-layer 15 is different from the direction of the stripes of the first parallel pn-layer 12. For example, the direction of the stripes of the second parallel pn-layer 15 may be perpendicular to the direction of the stripes of the first parallel pn-layer 12. In other configurative aspects, the third embodiment is substantially identical to the second embodiment.

(71) The third embodiment offers the same effect as the second embodiment. Even if the first parallel pn-layer 12 and the second parallel pn-layer 15 differ in the direction of stripes, the same effect of the robustness against charges on breakdown voltage is achieved as in the second embodiment as far as the structure of the peripheral region 3 is the same as the structure in the second embodiment.

Fourth Embodiment

(72) FIGS. 17 and 18 are vertical sectional views of a semiconductor apparatus of a fourth embodiment. A top view of the semiconductor apparatus of the fourth embodiment is substantially identical to the top view of FIG. 1. In the top view of the fourth embodiment, a parallel pn-layer 31, n-regions 32, and p-regions 33 are equivalent to the first parallel pn-layer 12, the first n-regions 13, and the first p-regions 14, respectively. FIG. 17 is equivalent to a vertical sectional view along the A-A line in FIG. 1; and FIG. 18 is equivalent to a vertical sectional view along the B-B line in FIG. 1. As depicted in FIGS. 17 and 18, the fourth embodiment is different from the first embodiment in that the parallel pn-layer 31 consisting of the alternately arranged n-regions (fourth regions of the first conductivity) 32 and p-regions (fourth regions of the second conductivity) 33 is formed between the first main surface and the n.sup.+-drain region 2. This means that the pitch of the parallel pn-layer 31 remains the same in the active region 1 and in the peripheral region 3. The n.sup.-surface region 18 has an impurity concentration lower that is than the impurity concentration of the n-regions 32 of the parallel pn-layer 31, and has a thickness that is half or less than half the thickness of the parallel pn-layer 31 under the active region 1. At the junction between the n.sup.-surface region 18 and the pn-layer 31 under the active region 1, charges are imbalanced, which may invite a drop in breakdown voltage. It is desirable, therefore, for the thickness T of the junction between the n.sup.-surface region 18 and the pn-layer 31 under the active region 1 to be half or less than half the thickness of the pn-layer 31 under the active region 1. In other configurative aspects, the fourth embodiment is substantially identical to the first embodiment.

(73) Although not particularly limited hereto, for example, the semiconductor apparatus of the fourth embodiment is a vertical 600V MOSFET, the dimensions and impurity concentration of the constituent elements are as follows. The thickness of a drift region (thickness of the parallel pn-layer 31 in the active region 1) is 44.0 micrometers, the width of the first n-region 32 and of the first p-region 33 is 7.0 micrometers (with a repetition pitch of 14.0 micrometers), and the impurity concentration of the n-region 32 and of the p-region 33 is 3.0*10.sup.15 cm.sup.3. The impurity concentration of the n.sup.-surface region 18 is 1.0*10.sup.14 cm.sup.3. The diffusion depth of the p-guard ring regions 19, 20, and 21 is 3.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.17 cm.sup.3. The diffusion depth of the p-base region 5 is 3.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.17 cm.sup.3. The diffusion depth of the n.sup.+-source region 4 is 1.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.20 cm.sup.3. The diffusion depth of a surface n-drift region (n-region above a broken line between p-base regions 5 in FIGS. 17 and 18) is 2.5 micrometers, and the surface impurity concentration of the same is 2.0*10.sup.16 cm.sup.3. The thickness of the n.sup.+-drain region 2 is 300 micrometers, and the impurity concentration of the same is 2.0*10.sup.18 cm.sup.3. The width of the n-channel stopper region 25 is 30.0 micrometers, and the impurity concentration of the same is 5.0*10.sup.15 cm.sup.3. The impurity concentration of the outermost peripheral p-region 26 is 3.0*10.sup.17 cm.sup.3.

(74) FIG. 19 is a diagram of the simulation results of surface charge dependency on breakdown voltage in the semiconductor apparatus of the fourth embodiment. These simulation results are obtained from simulations for a configuration such that four p-guard ring regions are connected electrically to field plate electrodes. As depicted in FIG. 19, breakdown voltage hardly fluctuates even if positive charges (positive ions) or negative charges (negative ions) are present on the oxide film of the peripheral region. This demonstrates that high breakdown voltage is achieved and the robustness against charges on breakdown voltage is improved in the second embodiment.

(75) FIGS. 20 to 22 depict electric potential distributions in off-state for the semiconductor apparatus of the fourth embodiment. FIG. 20 depicts an electric potential distribution in the case that a surface charge quantity on the oxide film of the peripheral region is 1.0*10.sup.12 cm.sup.2. FIG. 21 depicts an electric potential distribution in the case that the surface charge quantity is 0.0 cm.sup.2. FIG. 22 depicts an electric potential distribution in the case that the surface charge quantity is +1.0*10.sup.12 cm.sup.2. These figures reveal that breakdown voltage is maintained mainly between the field plate electrode and the channel stopper electrode when surface charges are negative charges (negative ions), and that breakdown voltage is maintained mainly by the p-guard ring regions and the filed plate electrode when surface charges are positive charges (positive ions). According to the fourth embodiment, effects identical to those of the first embodiment are achieved.

Fifth Embodiment

(76) FIGS. 23 and 24 are vertical sectional views of a semiconductor apparatus of a fifth embodiment. A top view of the semiconductor apparatus of the fifth embodiment is substantially identical to the top view of FIG. 1. In the top view of the fifth embodiment, a parallel pn-layer 31, n-regions 32, and p-regions 33 are equivalent to the first parallel pn-layer 12, the first n-regions 13, and the first p-regions 14, respectively. FIG. 23 is equivalent to a vertical sectional view along the A-A line in FIG. 1; and FIG. 24 is equivalent to a vertical sectional view along the B-B line in FIG. 1. As depicted in FIGS. 23 and 24, the fifth embodiment is different from the fourth embodiment in that the p-guard ring regions 19 and 20 other than the innermost p-guard ring region 21 are connected electrically to the field plate electrodes 23 and 27, respectively. The innermost p-guard ring region 21 is not connected electrically to the-field plate electrode. The field plate electrodes 23 and 27 are independent of each other. The number of the p-guard ring regions may be two or four or more. In other configurative aspects, the fifth embodiment is substantially identical to the fourth embodiment.

(77) The fifth embodiment offers the same effect as the fourth embodiment. Because the p-guard ring regions 19 and 20 are connected electrically to the field plate electrodes 23 and 27, respectively, charges and ions migrating to the peripheral region 3 are collected by the field plate electrodes 23 and 27. As a result, the influence of charges (ions) on breakdown voltage is reduced.

Sixth Embodiment

(78) FIGS. 25 and 26 are vertical sectional views of a semiconductor apparatus of a sixth embodiment. A top view of the semiconductor apparatus of the sixth embodiment is substantially identical to the top view of FIG. 1. In the top view of the sixth embodiment, a parallel pn-layer 31, n-regions 32, and p-regions 33 are equivalent to the first parallel pn-layer 12, the first n-regions 13, and the first p-regions 14, respectively. FIG. 25 is equivalent to a vertical sectional view along the A-A line of FIG. 1; and FIG. 26 is equivalent to a vertical sectional view along the B-B line in FIG. 1. As depicted in FIGS. 25 and 26, the sixth embodiment is different from the fourth embodiment in that all of the p-guard ring regions 19, 20, and 21 are connected electrically to the field plate electrodes 23, 27, and 28. The field plate electrodes 23, 27, and 28 are independent of each other. In other configurative aspects, the sixth embodiment is substantially identical to the fourth embodiment.

(79) The sixth embodiment offers the same effect as the fourth embodiment. Because the p-guard ring regions 19 and 20 are connected electrically to the field plate electrodes 23, 27, and 28, respectively, charges and ions migrating to the peripheral region 3 are collected by the field plate electrodes 23 and 27. As a result, the influence of charges (ions) on breakdown voltage is reduced.

Seventh Embodiment

(80) FIG. 27 is a top view of a semiconductor apparatus according to a seventh embodiment. FIG. 28 is a vertical sectional view along an A-A line in FIG. 27 of the semiconductor apparatus of the seventh embodiment. FIG. 29 is a vertical sectional view along a B-B line in FIG. 27 of the semiconductor apparatus according to the seventh embodiment. FIG. 27 depicts the shape of the parallel pn-layer, of the n-channel stopper region, of the p-base region at the outermost location of the active region, of the n.sup.-surface region, and of a p.sup.-surface region at the first main surface (FIG. 34 depict the same). As depicted in FIGS. 27 to 29, the seventh embodiment is different from the fourth embodiment in that the n.sup.-surface region 18 and the p.sup.-surface region (fifth region of the second conductivity) 41 are formed between the parallel pn-layer 31 and the first main surface, and that no p-guard ring region is formed in the n.sup.-surface region 18.

(81) The p.sup.-surface region 41 is joined to the n.sup.-surface region 18, and is disposed between the n.sup.-surface region 18 and the active region 1. The junction between the n.sup.-surface region 18 and the p.sup.-surface region 41 is located between the field plate electrode and the channel stopper electrode. The field plate electrode 23 covers a part of p.sup.-surface region 41 that is closer to the active region 1 across the insulating film 22. The channel stopper plate 24 covers a part of n.sup.-surface region 18 that is closer to the termination across the insulating film 22. The n.sup.-surface region 18 has an impurity concentration that is lower than the impurity concentration of the n-regions 32 of the parallel pn-layer 31. The p.sup.-surface region 41 has an impurity concentration lower than the impurity concentration of the p-regions 33 of the parallel pn-layer 31.

(82) The thickness of the n.sup.-surface region 18 and p.sup.-surface region 41, i.e., the thickness T of the junction between the p.sup.-surface region 41 and the parallel pn-layer 31 under the active region 1 is one-third or less of the thickness of the parallel pn-layer 31 under the active region 1. The larger the thickness T of the junction between the p.sup.-surface region 41 and the parallel pn-layer 31 under the active region 1 is, the smaller the thickness of the parallel pn-layer 31 in the peripheral region 3 is. This leads to a drop in breakdown voltage. If the thickness of the n.sup.-surface region 18 is one-third or less of that of the parallel pn-layer 31 under the active region 1, the thickness of the parallel pn-layer 31 in the peripheral region 3 is large, which suppresses a drop in breakdown voltage. It is desirable, therefore, that the thickness T of the n.sup.-surface region 18 and p.sup.-surface region 41 be one-third or less of that of the parallel pn-layer 31 under the active region 1. In other configurative aspects, the seventh embodiment is substantially identical to the fourth embodiment.

(83) Although not particularly limited hereto, for example, the semiconductor apparatus of the seventh embodiment is a vertical 600V MOSFET, the dimensions and impurity concentration of the constituent elements are as follows. The thickness of the drift region (thickness of the parallel pn-layer 31 in the active region 1) is 44.0 micrometers, the width of the n-region 32 and of the p-region 33 is 7.0 micrometers (with the repetition pitch P1 of 14.0 micrometers), and the impurity concentration of the n-region 32 and of the p-region 33 is 3.0*10.sup.15 cm.sup.3. The impurity concentration of the p-surface region 41 is 2.0*10.sup.15 cm.sup.3. The impurity concentration of the n.sup.-surface region 18 is 2.0*10.sup.14 cm.sup.3. The diffusion depth of the p-base region 5 is 3.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.17 cm.sup.3. The diffusion depth of the n.sup.+-source region 4 is 1.0 micrometers, and the surface impurity concentration of the same is 3.0*10.sup.20 cm.sup.3. The diffusion depth of the surface n-drift region (n-region above a broken line between p-base regions 5 in FIGS. 28 and 29) is 2.5 micrometers, and the surface impurity concentration of the same is 2.0*10.sup.16 cm.sup.3. The thickness of the n.sup.+-drain region 2 is 300 micrometers, and the impurity concentration of the same is 2.0*10.sup.18 cm.sup.3. The width of the n-channel stopper region 25 is 30.0 micrometers, and the impurity concentration of the same is 6.0*10.sup.15 cm.sup.3. The impurity concentration of the outermost peripheral p-region 26 is 3.0*10.sup.17 cm.sup.3.

(84) FIG. 30 is a diagram of the simulation results of surface charge dependency on breakdown voltage in the semiconductor apparatus of the seventh embodiment. As depicted in FIG. 30, breakdown voltage hardly fluctuates even if positive charges (positive ions) or negative charges (negative ions) are present on the oxide film of the peripheral region. This demonstrates that high breakdown voltage is achieved and the robustness against charges on breakdown voltage is improved in the seventh embodiment.

(85) FIGS. 31 to 33 depict electrical potential distributions in off-state for the semiconductor apparatus of the seventh embodiment. FIG. 31 depicts an electric potential distribution in the case that a surface charge quantity on the oxide film of the peripheral region is 1.0*10.sup.12 cm.sup.2. FIG. 32 depicts an electric potential distribution in the case that the surface charge quantity is 0.0 cm.sup.2. FIG. 33 depicts an electric potential distribution in the case that the surface charge quantity is +1.0*10.sup.12 cm.sup.2. These figures reveal that breakdown voltage is maintained mainly in the p.sup.-surface region 41 between the field plate electrode and the channel stopper electrode when surface charges are positive charges (positive ions), and that breakdown voltage is maintained mainly in the n.sup.-surface region 18 between the field plate electrode and the channel stopper electrode when surface charges are negative charges (negative ions).

(86) According to the seventh embodiment, when positive charges (positive ions) are present on the oxide film of the peripheral region, the p.sup.-surface region 41 is depleted of carriers to relax a surface electric field. As a result, breakdown voltage is maintained. When negative charges (negative ions) are present on the oxide film of the peripheral region, the n.sup.-surface region 18 is depleted of carriers. As a result, breakdown voltage is maintained. A drop in breakdown voltage, therefore, can be suppressed even if positive charges (positive ions) or negative charges (negative ions) are present on the oxide film of the peripheral region. Hence, the robustness against charges on breakdown voltage is improved. If the impurity concentration of the n.sup.-surface region 18 is lower than that of the n-regions 32 of the parallel pn-layer 31, the n.sup.-surface region 18 is easily depleted of carriers. This facilitates securing initial breakdown voltage. If the impurity concentration of the p.sup.-surface region 41 is lower than that of the n-regions 33 of the parallel pn-layer 31, the p.sup.-surface region 41 is easily depleted of carries. This facilitates securing initial breakdown voltage.

Eighth Embodiment

(87) FIG. 34 is a top view of a semiconductor apparatus of an eighth embodiment. FIG. 35 is a vertical sectional view along an A-A line in FIG. 34 of the semiconductor apparatus according to the eight embodiment. FIG. 36 is a vertical sectional view along a B-B line in FIG. 34 of the semiconductor apparatus according to the eighth embodiment. As depicted in FIGS. 34 to 36, the eighth embodiment is different from the seventh embodiment in that the p.sup.-surface region 41 includes plural sub-regions 42 and 43 different from each other in impurity concentration. The impurity concentration of the sub-regions 42 and 43 included in the p.sup.-surface region 41 may decrease as the sub-regions approach the termination of the peripheral region 3 from the active region 1. In other words, the p.sup.-surface region 41 may have an impurity concentration gradient that decreases as the p.sup.-surface region 41 approaches the termination of the peripheral region 3 from the active region 1. For example, among the sub-regions 42 and 43 included in the p.sup.-surface region 41, the p.sup.-surface sub-region 42 closer to the active region 1 may have an impurity concentration of 2.0*10.sup.15 cm.sup.3, and the p.sup.-surface sub-region 43 closer to the termination of the peripheral region 3 may have an impurity concentration of 1.0*10.sup.15 cm.sup.3. The p.sup.-surface region 41 may have three or more sub-regions different in impurity concentration from each other. The impurity concentration of the p.sup.-surface region 41 may decrease continuously from its end closer to the active region 1 to its end closer to the termination of the peripheral region 3. In other configurative aspects, the eighth embodiment is substantially identical to the fourth embodiment.

(88) The eighth embodiment offers the same effect as the seventh embodiment. Because the impurity concentration of the p.sup.-surface region 41 has the gradient, expansion of the depletion layer toward the outer periphery can be controlled according to the quantity of positive charges (positive ions) when positive charges (positive ions) are present on the oxide film of the peripheral region. In other words, an electric field distribution in the p.sup.-surface region 41 can be controlled. Hence the fluctuation of breakdown voltage caused by positive charges is suppressed.

Ninth Embodiment

(89) FIG. 37 is a top view of a semiconductor apparatus of a ninth embodiment. FIG. 38 is a horizontal cross sectional view of the parallel pn-layer of the semiconductor apparatus of the ninth embodiment. FIG. 39 is a vertical sectional view along an A-A line of FIG. 38 of the semiconductor apparatus of the ninth embodiment. FIG. 37 depicts the field plate electrode, the channel stopper electrode, an N-rich region (region serving substantially as the n-region) in the peripheral region, and a P-rich region (region serving substantially as the p-region) in the peripheral region (FIGS. 43 to 45 depict the same). FIG. 38 depicts the shape of the parallel pn-layer and of the n-channel stopper region at the first main surface. In the ninth embodiment, as depicted in FIGS. 37 to 39, the n.sup.-surface region and the p.sup.-surface region of the seventh embodiment are replaced with an N-rich region 51 and a P-rich region 52, respectively. The first parallel pn-layer 12 having the repetition pitch P1 is disposed to extend through the active region 1 to further stretch up to the middle of the uppermost step of the field plate electrode 23 (the closest step to the termination of the peripheral region 3). The second parallel pn-layer 15 having the repetition pitch P2 is disposed to extend from the middle of the uppermost step of the field plate electrode 23 up to the termination of the peripheral region 3. The repetition pitch P2 is narrower than the repetition pitch P1.

(90) The region in which the first parallel pn-layer 12 is disposed mostly serves as a charge balance region 53. Adjacent to this charge balance region 53, the P-rich region 52 is disposed. The region between the P-rich region 52 and the N-rich region 51 mostly serves as a charge balance region 54. The region between the N-rich region 51 and the n-channel stopper region 25 mostly serves as a charge balance region 55. In FIGS. 37 to 39, reference numeral 61 denotes the termination of field plate electrode 23 that is closer to the channel stopper electrode 24, and reference numerals 62, 63, and 64 denote the level differences of the field plate electrode 23. Reference numeral 65 denotes the termination of the channel stopper electrode 24 that is closer to the field plate electrode 23, and reference numerals 66, 67, and 68 denote the level differences of the channel stopper electrode 24. The N-rich region 51 extends from a location between the channel stopper electrode 24 and the field plate electrode 23 to a location under the channel stopper electrode 24. The P-rich region 52 extends from a location between the channel stopper electrode 24 and the field plate electrode 23 to, for example, a location under the middle of the uppermost step of the filed plate electrode 23.

(91) In the N-rich region 51, the width of each second n-region 16 is larger than that of each second p-region 17 at the first main surface side of the second parallel pn-layer 15. As a result, the N-rich region 51 serves substantially as an n-region. In the N-rich region 51, the width of the second n-region 16 is kept constant and the same of the second p-region 17 is also kept constant. In the p-rich region 52, the width of each second p-region 17 is larger than that of each second n-region 16 at the first main surface side of the second parallel pn-layer 15. As a result, the P-rich region 52 serves substantially as a p-region. In the P-rich region 52, the width of the second n-region 16 is kept constant and the same of the second p-region 17 is also kept constant. When the repetition pitch of the second parallel pn-layer 15 is constant, increasing the width of the second n-region 16 results in a decrease in the width of the second p-region 17 in the decrement corresponding to the increment, while increasing the width of the second p-region 17 results in a decrease in the width of the second n-region 16 in the decrement corresponding to the increment. When the repetition pitch of the second parallel pn-layer 15 is constant and the width of the second n-region 16 and the same of the second p-region 17 is constant in the N-rich region 51 and in the p-rich region 52, the ratio of the second p-regions 17 to the second n-regions 16 is constant in the N-rich region 51 and in the p-rich region 52.

(92) The N-rich region 51 and the P-rich region 52 are formed in the following manner. For example, a process of epitaxial growth on a substrate, a process of injecting n-impurity ions into the entire epitaxial layer surface, and a process of selectively injecting p-impurity ions into the epitaxial layer are repeated. At the final process of p-impurity injection, ion injection is carried out using a mask that has a pattern with a narrow opening as a portion to be formed into the N-rich region 51 and a wide opening as a portion to be formed into the P-rich region 52. The injected impurity is diffused by thermal budget.

(93) FIGS. 40 to 42 are schematic diagrams of electric potential distribution in the off-state for the semiconductor apparatus of the ninth embodiment. FIG. 40 depicts an electric potential distribution in the case that a surface charge quantity on the oxide film of the peripheral region is zero. FIG. 41 depicts an electric potential distribution in the case that the surface charge quantity is positive. FIG. 42 depicts an electric potential distribution in the case that the surface charge quantity is negative.

(94) In these figures, broken lines represent electric potential lines. These figures reveal that breakdown voltage is maintained mainly in the P-rich region 52 between the field plate electrode and the channel stopper electrode when surface charges are positive charges (positive ions), and that breakdown voltage is maintained mainly in the N-rich region 51 between the field plate electrode and the channel stopper electrode when surface charges are negative charges (negative ions).

(95) According to the ninth embodiment, because of the presence of the P-rich region 52, a surface electric field is eased to improve breakdown voltage when positive charges (positive ions) are present on the oxide film of the peripheral region. Because of the presence of the N-rich region 51, breakdown voltage is improved when negative charges (negative ions) are present on the oxide film of the peripheral region. Hence the robustness against charges on breakdown voltage against charges is improved.

Tenth Embodiment

(96) In the ninth embodiment, the width of the second n-region 16 in the N-rich region 51 and the width of the second p-region 17 in the P-rich region 52 may change at each stripe, or may change gradually or step by step in the direction of extension of the second n-region 16 and the second p-region 17 (y direction in FIG. 38). In a tenth embodiment, the width of the second n-region 16 in the N-rich region 51 and the width of the second p-region 17 in the P-rich region 52 of the ninth embodiment are changed at each stripe or changed gradually or step by step in the direction of extension of the second n-region 16 and the second p-region 17 (y direction in FIG. 38). In this case, it is preferable that the width of the second n-region 16 becomes smaller as the second n-region 16 goes away from the channel stopper electrode 24 in the N-rich region 51 to bring the N-rich region 51 closer to a state of charge balance, and that the width of the second p-region 17 becomes smaller as the second p-region 17 goes away from the field plate electrode 23 in the P-rich region 52 to bring the P-rich region 52 closer to a state of charge balance. This allows a depletion layer to expand more easily, which enables maintenance of high breakdown voltage.

(97) In the tenth embodiment (working example 10), breakdown voltage hardly fluctuates even if positive charges (positive ions) or negative charges (negative ions) are present on the oxide film in the peripheral region. In the tenth embodiment (working example 10), initial breakdown voltage is higher. Hence the tenth embodiment offers the same effect as the ninth embodiment.

Eleventh Embodiment

(98) In the ninth embodiment, the N-rich region 51 and the P-rich region 52 may be formed to be closer to each other to reduce the charge balance region 54 between the N-rich region 51 and the P-rich region 52 to a region as small as possible. Between the N-rich region 51 and the P-rich region 52, however, the charge balance region 54 is formed to have a width at least equivalent to half the pitch of the second parallel pn-layer 15. The charge balance region 54 between the N-rich region 51 and the P-rich region 52 may have a width larger than such a width. The larger the width of the charge balance region 54 is, the easier the expansion of a depletion layer is, which improves breakdown voltage. If the width of the charge balance region 54 is one-third or less of the distance between the field plate electrode 23 and the channel stopper electrode 24, the length of the peripheral region 3 is not excessively long, which is preferable. FIG. 43 is a plane figure of a semiconductor apparatus in which the width of the charge balance region 54 between the N-rich region 51 and the P-rich region 52 is made greater. The eleventh embodiment offers the same effect as the ninth embodiment.

Twelfth Embodiment

(99) FIG. 44 is a plane figure of a semiconductor apparatus of a twelfth embodiment. As depicted in FIG. 44, the twelfth embodiment is different from the ninth embodiment in that the charge balance region is not formed at the outside of the N-rich region 51. In the example of FIG. 44, the region serving as the charge balance region 55 in the ninth embodiment is formed into the N-rich region 51. The twelfth embodiment offers the same effect as the ninth embodiment.

Thirteenth Embodiment

(100) FIG. 45 is a plane figure of a semiconductor apparatus of a thirteenth embodiment. As depicted in FIG. 45, the thirteenth embodiment is different from the ninth embodiment in that the boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15 coincides with the boundary between the active region 1 and the peripheral region 3. In this case, the pitch of the parallel pn-layer is caused to change gradually near the boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15. If the pitch of the parallel pn-layer changes suddenly near the boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15, for example, irregular opening widths of a mask used for impurity ion injection in a manufacturing process, irregular ion injection quantities, etc., affect breakdown voltage, causing it to fluctuate easily or to drop to a level below charge balance. Causing the pitch of the parallel pn-layer to change gradually near the boundary between the first parallel pn-layer 12 and the second parallel pn-layer 15 prevents the fluctuation or drop of breakdown voltage. The thirteenth embodiment offers the same effect as the ninth embodiment.

Fourteenth Embodiment

(101) FIGS. 46 and 47 are plane figures of a semiconductor apparatus of a fourteenth embodiment. As depicted in FIG. 46, in the first to thirteenth embodiments, a parallel pn-layer 71 having an n-region 72 in which p-regions 73 of a circular planar shape are arranged may be provided. The parallel pn-layer 71 configured in such a manner may be disposed in the active region 1 and the peripheral region 3 (pattern depicted in FIG. 46), or disposed in the active region 1 only (pattern depicted in FIG. 47), or disposed in the peripheral region 3 only (not depicted). According to the pattern of FIG. 47, a second parallel pn-layer 75 is disposed in the peripheral region 3, the second parallel pn-layer 75 being formed by repeatedly joining stripes of second n-regions (second regions of the first conductivity) 76 and second p-regions (second regions of the second conductivity) 77 that are alternately arranged at a fine pitch. The pitch of repetition of the second n-regions 76 and the second p-regions 77 may be the same as the repetition pitch of the parallel pn-layer 71 in the active region 1. The parallel pn-layer 71 may have the p-region 73 in which the n-regions 72 of a circular planar shape are arranged. The fourteenth embodiment offers the same effect as the first to thirteenth embodiments.

Fifteenth Embodiment

(102) FIGS. 48 and 49 are plane figures of a semiconductor apparatus of a fifteenth embodiment. As depicted in FIG. 48, in the first to thirteenth embodiments, the parallel pn-layer 71 having the n-region 72 in which the p-regions 73 of a square planar shape are arranged may be provided. The parallel pn-layer 71 configured in such a manner may be disposed in the active region 1 and the peripheral region 3 (pattern depicted in FIG. 48), or disposed in the active region 1 only (pattern depicted in FIG. 49), or disposed in the peripheral region 3 only (not depicted). The parallel pn-layer 71 may have the p-region 73 in which the n-regions 72 of a square planar shape are arranged. The fifteenth embodiment offers the same effect as the first to thirteenth embodiments.

Sixteenth Embodiment

(103) FIGS. 50 and 51 are plane figures of a semiconductor apparatus of a sixteenth embodiment. As depicted in FIG. 50, in the first to thirteenth embodiments, the parallel pn-layer 71 having the n-region 72 in which the p-regions 73 of a polygonal (e.g., octagonal) planar shape are arranged may be provided. The parallel pn-layer 71 configured in such a manner may be disposed in the active region 1 and the peripheral region 3 (pattern depicted in FIG. 50), or disposed in the active region 1 only (pattern depicted in FIG. 51), or disposed in the peripheral region 3 only (not depicted). The parallel pn-layer 71 may have the p-region 73 in which the n-regions 72 of a polygonal (e.g., octagonal) planar shape are arranged. The sixteenth embodiment offers the same effect as the first to thirteenth embodiments.

Seventeen Embodiment

(104) FIGS. 52 and 53 are plane figures of a semiconductor apparatus of a seventeenth embodiment. As depicted in FIG. 52, in the first to thirteenth embodiments, the parallel pn-layer 71 having the n-region 72 in which the p-regions 73 of a polygonal (e.g., hexagonal) planar shape are arranged may be provided. The parallel pn-layer 71 configured in such a manner may be disposed in the active region 1 and the peripheral region 3 (pattern depicted in FIG. 52), or disposed in the active region 1 only (pattern depicted in FIG. 53), or disposed in the peripheral region 3 only (not depicted). The parallel pn-layer 71 may have the p-region 73 in which the n-regions 72 of a polygonal (e.g., octagonal) planar shape are arranged. The seventeenth embodiment offers the same effect as the first to thirteenth embodiments.

(105) In the fourteenth to seventeenth embodiments, the p-regions 73 are arranged at equal intervals in the active region 1 and in the peripheral region 3. The interval of arrangement in the active region 1 and the same in the peripheral region 3 may be identical to or different from each other.

(106) The present invention is not limited to the embodiments described above but various modifications of the invention are possible. For example, dimensions and concentrations described in the embodiments are presented as examples, and the values of those dimensions and concentrations do not limit the present invention. While the first-conductive type is defined as the n-type and the second-conductive type is defined as the p-type in the embodiments, the present invention offers the same effect as described in the embodiments even if the first-conductive type is defined as the p-type and the second-conductive type is defined as the n-type. The present invention applies not only to a MOSFET but also to an IGBT, bipolar transistor, FWD (Free Wheel Diode), Schottky diode, etc.

INDUSTRIAL APPLICABILITY

(107) As described above for embodiments of the present invention, the semiconductor apparatus is useful as a semiconductor apparatus for large power consumption, and is particularly applicable as a semiconductor apparatus that achieves both high breakdown voltage and high current capacity in applications to a MOSFET, IGBT, bipolar transistor, FWD, Schottky diode, etc. having a parallel pn-structure in a drift layer.

REFERENCE NUMERALS LIST

(108) The following is a listing of reference numerals as used in the specification and drawings to identify various elements for the semiconductor apparatus: 1 active region 2 low-resistance layer 3 peripheral region 12 first parallel pn-layer 13 first region of a first conductivity 14 first region of a second conductivity 15 second parallel pn-layer 16 second region of the first conductivity 17 second region of the second conductivity 18 third region of the first conductivity 19, 20, 21 third region of the second conductivity 22 insulating film 23, 27, 28 first conductive layer 24 second conductive layer 31 parallel pn-layer 32 fourth region of the first conductivity 33 fourth region of the second conductivity 41, 42, 43 fifth region of the second conductivity

(109) Although a few embodiments have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.