In-Rush Current Protected Power Converter

Abstract

Circuits and methods for protecting the switches of charge pump-based power converters from damage if a V.sub.OUT short circuit event occurs and/or if V.sub.IN falls rapidly with respect to V.sub.X or V.sub.OUT. A general embodiment includes a V.sub.X Detection Block coupled to the core block of a power converter. The V.sub.X Detection Block is coupled to V.sub.X and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in V.sub.X during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a V.sub.IN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of V.sub.IN to the power converter. The V.sub.IN Detection Block is coupled to V.sub.IN, and to V.sub.X or V.sub.OUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.

Claims

1. A power converter including: (a) a converter circuit configured to convert and input voltage V.sub.IN to a different output voltage V.sub.OUT; (b) a control block for disabling operation of the converter circuit; (c) a voltage node V.sub.X between the converter circuit and the output V.sub.OUT; (d) a V.sub.IN detection block, coupled to V.sub.IN and to the control block, and optionally coupled to one of V.sub.OUT or the voltage node V.sub.X, and configured to detect a voltage drop at V.sub.IN and generate a control signal to the control block to disable operation of the converter circuit.

2. The invention of claim 1, wherein the V.sub.IN detection block is configured to detect a voltage drop at V.sub.IN where the voltage drop has a magnitude that induces damage to the converter circuit.

3. The invention of claim 1, wherein the converter circuit, the control block, the voltage node V.sub.X, and the V.sub.IN detection block are embodied in a single integrated circuit die.

4. The invention of claim 1, wherein the V.sub.IN detection block includes: (a) a PMOS FET having a gate coupled to the voltage node V.sub.IN, a source, and a drain; (b) a resistor coupled between the voltage node V.sub.IN and the source of the PMOS FET; (c) a capacitor coupled between the source of the PMOS FET and a reference voltage; (d) an inverter coupled to the drain of the PMOS FET; and (e) a threshold voltage adjustment circuit coupled to the drain of the PMOS FET; wherein the PMOS FET causes the inverter to generate the control signal if a voltage applied to the gate of the PMOS FET from the voltage node V.sub.IN has a voltage drop relative to a voltage across the capacitor.

5. The invention of claim 4, further including a degeneration resistor coupled between the capacitor and the source of the PMOS FET.

6. The invention of claim 1, wherein the V.sub.IN detection block includes: (a) a scaling circuit coupled to V.sub.IN and configured to output a scaled output voltage; (b) a comparator circuit, having a first input coupled to the scaled output voltage and a second input coupled to one of V.sub.OUT or the voltage node V.sub.X, and configured to output the control signal upon the occurrence of a voltage drop in V.sub.IN relative to the voltage coupled to the second input.

7. The invention of claim 1, wherein the converter circuit is coupled to a source of non-overlapping clock signals having ON states separated by a dead time, and wherein the V.sub.IN detection block is configured to detect the voltage drop at the voltage node V.sub.IN during the dead time.

8. A method for protecting a power converter, including: (a) monitoring an input voltage V.sub.IN to a converter circuit of the power converter; and (b) disabling operation of the converter circuit upon detection of a voltage drop of the input voltage V.sub.IN.

9. The method of claim 8, wherein the voltage drop of the input voltage V.sub.IN has a magnitude that induces damage to the power converter.

10. The method of claim 8, further including detecting a voltage drop of the input voltage V.sub.IN relative to one of an output voltage V.sub.OUT of the power converter or a voltage node V.sub.X of the converter circuit.

11. The method of claim 8, wherein the converter circuit is coupled to a source of non-overlapping clock signals having ON states separated by a dead time, and wherein detection of a voltage drop of the input voltage V.sub.IN is enabled only during the dead time.

Description

DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a block diagram showing a prior art adiabatic DC-to-DC power converter.

[0020] FIG. 2 is a schematic diagram of a prior art power converter that includes a divide-by-two Dickson charge pump.

[0021] FIG. 3 is a graph of the ON and OFF states of the clock signals P1 and P2 over time.

[0022] FIG. 4 is a graph showing the relative values of V.sub.X and V.sub.OUT during a sequence of the clock signals P1, P2.

[0023] FIG. 5 is a graph showing the values of V.sub.X and V.sub.OUT as a function of time, both before and after a short circuit event across V.sub.OUT.

[0024] FIG. 6 is a block diagram of a general embodiment of the present invention, including a V.sub.X Detection Block coupled to the core block 101 of a power converter.

[0025] FIG. 7 is a schematic diagram of a first embodiment of a circuit suitable for use as the V.sub.X Detection Block of FIG. 6.

[0026] FIG. 8 is a schematic diagram of a second embodiment of a circuit suitable for use as the V.sub.X Detection Block of FIG. 6.

[0027] FIG. 9 is a schematic diagram of a third embodiment of a circuit suitable for use as the V.sub.X Detection Block of FIG. 6.

[0028] FIG. 10 is a schematic diagram of a first embodiment of a circuit suitable for use as the V.sub.IN Detection Block of FIG. 6.

[0029] FIG. 11 is a process flow chart showing a first method for protecting a power converter from in-rush current.

[0030] FIG. 12 is a process flow chart showing a second method for protecting a power converter from in-rush current.

[0031] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0032] The present invention encompasses circuits and methods for protecting the switches of charge pump-based power converters from damage if a V.sub.OUT short circuit event occurs and/or if V.sub.IN falls rapidly with respect to V.sub.X or V.sub.OUT. Embodiments of the present invention resolve this issue without substantially decreasing the efficiency of such power converters.

Short Circuit Events

[0033] Upon careful investigation of the failure mechanism for damage that occurs during a short circuit event, a number of novel insights were gained. To describe one aspect of the problem, and using FIG. 2 as an example, consider that if the ultimate output, V.sub.OUT, of the power converter 200 is shorted to ground, C.sub.OUT will start to discharge, initially at a rate of about R.sub.SHORT×C.sub.OUT (the discharge rate will be slowed as the charge pump 201 adds charge to the output at V.sub.X). As V.sub.OUT falls, the output current of the charge pump 201 will increase and hence V.sub.X will be maintained—initially—at or near its pre-short value. This then results in a voltage difference across the adiabatic inductor L. Consequently, current will increase in the inductor L according to the well-known inductor equation: V=L×dI/dt.

[0034] While the ultimate output of the power converter 200 is shorted, V.sub.X will initially cycle back close to its nominal value as V.sub.OUT falls because the charge held across the charge pump capacitors Cfly1, Cfly2 increases to compensate (during clock phase P1, the charge pump capacitors Cfly1, Cfly2 charge to V.sub.IN−V.sub.X, so as V.sub.X falls, more charge is stored on the charge pump capacitors). However, the current into V.sub.OUT increases far beyond the capability of the charge pump 201 to replenish charge, and thus all voltage nodes start to fall.

[0035] A critical and inventive insight into the problem of damage from a V.sub.OUT short circuit event is that the dead time between the clock signals P1 and P2 causes an unusual phenomenon. FIG. 3 is a graph 300 of the ON and OFF states of the clock signals P1 and P2 over time. In order to avoid a “shoot through” condition (which wastes charge, thus reducing efficiency) due to an overlap of the clock signals P1, P2, each clock signal is set to an OFF (low) state before the other clock signal is set to an ON (high) state, resulting in a dead time DT between the clock signals P1, P2. As a result, during normal operation of the charge pump 201, V.sub.X is no longer replenished by the charge pump 201 and the value of V.sub.X accordingly declines and dips below V.sub.OUT during the dead time DT by a small amount (less than about 100 millivolts). FIG. 4 is a graph 400 showing the relative values of V.sub.X and V.sub.OUT during a sequence of the clock signals P1, P2 (note that the relative values of V.sub.X and V.sub.OUT may not be to scale).

[0036] It was realized that during the dead time DT between the clock signals P1, P2, the increasing current in the adiabatic inductor L can only be supplied by the relatively small C.sub.VX capacitor. Hence, negative excursions (“spikes”) on V.sub.X increase significantly, from a normal range (generally measured in tens of millivolts) to an overvoltage range that may be several volts. For example, FIG. 5 is a graph 500 showing the values of V.sub.X and V.sub.OUT as a function of time, both before and after a short circuit event across V.sub.OUT. Before a short circuit event indicated by a vertical dashed line 502, the value of V.sub.X (indicated by graph lines 504a, 504b as example points only) makes only small excursions below V.sub.OUT (indicated by graph line 506) during the dead time DT. Thus, the pre-short circuit behavior is the same as shown in FIG. 4 (but the scale of relative values for of V.sub.X and V.sub.OUT in FIG. 5 is more accurate). After the short circuit event indicated by the dashed line 502, V.sub.OUT steadily falls towards zero volts at the output capacitor C.sub.OUT discharges. However, while a first negative excursion of V.sub.X at graph line 508 may be relatively small, V.sub.X exhibits a significant multi-volt negative excursion with respect to V.sub.OUT during a dead time DT intervals, as shown within the dotted oval 510. This multi-volt negative excursion is potentially quite damaging to the switches and/or charge pump capacitors of a power converter 200. After the multi-volt negative excursion at V.sub.X shown within the dotted oval 510, generally the power converter 200 will be turned OFF, but V.sub.X will oscillate as energy is still in the resonant tank circuit formed by the inductor L and the C.sub.VX capacitor; the frequency of oscillation is 1/(2π×sqrt(LC.sub.VX)).

[0037] The dead time excursions of V.sub.X with respect to V.sub.OUT during a short circuit event, as exemplified in FIG. 5, results in a damaging voltage spike, Vsp. A large Vsp spike results in a high in-rush current spike through the charge pump 201. In integrated circuit implementations, parasitic inductances exist (for example, due to on-die conductor routing and printed circuit board conductor routing) which transform a current spike to a voltage spike. Such voltage spikes electrically overstress the charge pump switches, affecting their reliability, potentially to destruction.

[0038] For example, in normal operation, in-rush current to the switches of the charge pump 201, such as during startup, is limited. The charge pump switches may have a very low ON resistance (e.g., 1-10 milliohms). During the dead time DT of a short circuit event, Vsp may be several volts due to V.sub.X falling significantly during the dead time DT. Accordingly, when the switches close and Vsp is large, very large in-rush current spikes occur as the charge pump capacitors charge. Because of Ohm's Law (I=V/R), the combination of very low ON resistance in the charge pump switches and small parasitic inductances can create a large Vsp which can then damage the switches. As a more specific example, assume that a pump switch has a 10 milliohm resistance and V.sub.X across the C.sub.VX capacitor droops by only 1V (i.e., Vsp=1V). Ohm's law gives a current of I=V/R=100 A. Inductor theory states that V=L×dI/dt. So a 100 A current spike happens very quickly as the pump switches open and close, typically in 1-2 ns. A typical damage threshold for the pump switches may be about 10V. For a 1 ns 100 A pulse to generate 10V across the pump switches, the parasitic inductance needs only to be L=V/(dI/dt)=100 pH. This is tiny given that parasitic inductances (e.g., PCB traces, on-die conductor routing) are often measured in nH (i.e., more than 10 times larger than 100 pH). Accordingly, a 1 ns 100 A pulse may generate much more than 10V across the pump switches. Of note, this problem arises with many types of converter circuits 102, and not just the charge pump 201 configuration of FIG. 2.

[0039] While higher voltage switches could be used for robustness, the larger size of such switches can make an IC embodiment uncompetitive. In conventional designs, excess current in-rush to a charge pump has been measured by monitoring I.sub.OUT for an over-current condition, but conventional designs measure the average DC output current over the switching period of the charge pump and not the much faster current spikes that can occur during the dead time DT, thus allowing damaging over-currents and voltages to remain undetected. A short circuit detection circuit at V.sub.OUT may also be added to shut down the charge pump 201 if V.sub.OUT drops by at a certain percentage, such as 80% of the nominal V.sub.OUT value, but such circuits are not fast enough to prevent damage to the charge pump switches for low-ohmic shorts during the dead time DT. Accordingly, there remains a strong need for a reliable detection technique that can protect critical charge pump circuitry from output short circuits. One aspect of embodiments of the present invention is to provide charge pump protection against dead time short circuits without any significant decrease in conversion efficiency or the addition of substantial power-consuming circuitry.

[0040] FIG. 6 is a block diagram of a general embodiment of the present invention, including a V.sub.X Detection Block 600 coupled to the core block 101 of a power converter. An input to the V.sub.X Detection Block 600 is coupled to V.sub.X. An output of the V.sub.X Detection Block 600, ΔV.sub.X Detected, is coupled to a control circuit to disable operation of an associated converter circuit 102 of the power converter and/or the entire power converter, such as by disabling the clock signals P1, P2 to the converter circuit 102 or causing the power converter to enter a safe mode of operation (for example, a safe discharge mode or high switch resistance mode). The control circuit may be the controller 104 for the core block 101, or alternatively may be any other control circuitry that can disable operation of the associated converter circuit 102 and/or the entire power converter, or cause the power converter to enter a safe mode of operation.

[0041] The V.sub.X Detection Block 600 should detect large, rapid falls in V.sub.X during the dead time DT between clock phase signals, and, as a result, generate a ΔV.sub.X Detected signal that disables or interrupts operation of the converter circuit 102 (e.g., disable or interrupt the switches of a charge pump), thereby prevent damaging current spikes. As stated above, a large and rapid drop in V.sub.X occurs during the dead time DT between the clock signals P1, P2 when a short circuit event occurs. Since the dead time DT is typically on the order of about 10 to 50 nanoseconds, the V.sub.X Detection Block 600 and the control circuit should have very short response times. The V.sub.X Detection Block 600 should also avoid overly loading the V.sub.X line, which would deteriorate efficiency.

[0042] FIG. 7 is a schematic diagram of a first embodiment of a circuit suitable for use as the V.sub.X Detection Block 600 of FIG. 6. The voltage V.sub.X is applied to a first input of a comparator 702 and to a switch Sw1. The switch Sw1 is normally closed, allowing V.sub.X to be applied to a shunt-connected capacitor C1 and to a first input of an op-amp 704 that isolates the capacitor C1 from down-stream circuitry. A resistive divider 706 comprising series-coupled resistors R1 and R2 is coupled between the output of the op-amp 704 and a reference potential, such as circuit ground. The output of the op-amp 704 is also fed back to a second input of the op-amp 704. Accordingly, the op-amp 704 functions as a voltage follower with respect to the voltage across the capacitor C1. A node between the series-coupled resistors R1 and R2 is coupled to a second input of the comparator 702 and provides a scaled voltage to the comparator 702. In some embodiment, one or both of the resistors R1 and R2 may be settable or variable in order to provide a desired scaled voltage to the comparator 702 (only R2 is shown as variable in the illustrated example).

[0043] In operation, the switch Sw1 would be opened at a point just before each dead time DT interval in order to sample the voltage on V.sub.X at that moment of time and hold that sampled voltage, V.sub.X′, on the capacitor C1. The sampled-and-held voltage value, V.sub.X′, is propagated by the op-amp 704 and scaled by the resistive divider 706, the output of which, V.sub.X″, is then compared to the then—current value of V.sub.X by the comparator 702. If the actual V.sub.X value should fall below the sampled and scaled value V.sub.X″, then the output of the comparator 702 would change state, which may be used to command a control circuit (e.g., the controller 104) to, for example, disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102) and/or the entire power converter, or cause the power converter to enter a safe mode of operation.

[0044] FIG. 8 is a schematic diagram of a second embodiment of a circuit suitable for use as the V.sub.X Detection Block 600 of FIG. 6. In this embodiment, V.sub.X is applied to a resistor R3 and to the gate of an enhancement-mode PMOS FET M1. The output of the resistor R3 is coupled to a shunt-connected capacitor C2 and to the source of the PMOS FET M1. The output (drain) of the PMOS FET M1 is coupled to an inverter 802 and to a threshold voltage adjustment circuit 804 that may comprise a small current source or a resistor that provides a voltage drop (V=I×R) to adjust the relative threshold voltage of the PMOS FET M1 as needed. In the illustrated example, the threshold voltage adjustment circuit 804 is coupled to a reference potential, such as circuit ground.

[0045] In operation, the resistor R3 and capacitor C2 function as a filter, removing small spikes in V.sub.X and outputting an averaged value V.sub.X′. While the filtered (averaged) value V.sub.X′ applied to the source of the PMOS FET M1 is equal to the value of V.sub.X applied to the gate of the PMOS FET M1 (i.e., V.sub.S=V.sub.G), then the PMOS FET M1 will be OFF (non-conducting). Accordingly, the input to the inverter 802 will be in a first logic state (e.g., “1”) and the output of the inverter 802 will be in an inverted second logic state (e.g., “0”). However, if V.sub.X rapidly falls below V.sub.X′ by at least the threshold voltage V.sub.T of the PMOS FET M1, then the PMOS FET M1 will be ON (conducting), since V.sub.S<V.sub.G. Accordingly, the input to the inverter 802 will be in the second logic state (e.g., “0”) and the output of the inverter 802 will be inverted to the first logic state (e.g., “1”). Thus, the change in state of the inverter 802 output may be used to command a control circuit (e.g., the controller 104) to, for example, disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102) and/or the entire power converter, or cause the power converter to enter a safe mode of operation.

[0046] An optional source degeneration resistor R4, which may be tunable or settable, may be coupled between a node coupling resistor R3 and capacitor C2, and the source of the PMOS FET M1. The value of the resistor R4 may be selected to adjust the effective threshold voltage V.sub.T of the PMOS FET M1, for example, to compensate for process and temperature variations in V.sub.T. In some embodiments, the resistor R4 may have a programmable value that can be dynamically altered by a temperature measurement circuit (not shown) to counter temperature-induced changes in the threshold voltage V.sub.T of the PMOS FET M1 or to adjust its apparent threshold voltage, in known fashion. In some embodiments, it may be useful to configure the threshold voltage adjustment circuit 804 to counter temperature-induced changes in the threshold voltage V.sub.T of the PMOS FET M1, again in known fashion.

[0047] FIG. 9 is a schematic diagram of a third embodiment of a circuit suitable for use as the V.sub.X Detection Block 600 of FIG. 6. The voltage V.sub.X is applied to a switch Sw2, which is normally closed, allowing V.sub.X to be applied to a shunt-connected capacitor C3 and to the source of an enhancement-mode PMOS FET M2. The voltage V.sub.X is also coupled to the gate of the PMOS FET M2. The output (drain) of the PMOS FET M2 is coupled to an inverter 802 and a threshold voltage adjustment circuit 804, as in FIG. 8. An optional source degeneration resistor R5, which may be tunable or settable, may be coupled between the voltage V.sub.X′ at the capacitor C3 and the source of the PMOS FET M2. The value of the resistor R5 may be selected to adjust the effective threshold voltage V.sub.T of the PMOS FET M2.

[0048] In operation, the switch Sw2 would be opened at a point just before each dead time DT interval in order to sample the voltage on V.sub.X at that moment of time and hold that sampled voltage, V.sub.X′, on the capacitor C3. While V.sub.X as applied to the gate of the PMOS FET M2 is equal to the sampled-and-held voltage value V.sub.X′ applied to the source of the PMOS FET M2 (i.e., V.sub.S=V.sub.G), then the PMOS FET M2 will be OFF (non-conducting). Accordingly, the input to the inverter 802 will be in a first logic state (e.g., “1”) and the output of the inverter 802 will be in an inverted second logic state (e.g., “0”). However, if V.sub.X rapidly falls below V.sub.X′ by at least the threshold voltage V.sub.T of the PMOS FET M2, then the PMOS FET M2 will be ON (conducting). Accordingly, the input to the inverter 802 will be in the second logic state (e.g., “0”) and the output of the inverter 802 will be inverted to the first logic state (e.g., “1”). Thus, the change in state of the inverter 802 output may be used to command a control circuit (e.g., the controller 104) to, for example, disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102) and/or the entire power converter, or cause the power converter to enter a safe mode of operation.

[0049] Advantages of the embodiment of FIG. 9 include that the circuit may be operated independent of the converter circuit clock signal (P1, P2) frequency, the circuit requires no high-power consuming circuitry (such as high bandwidth op-amps or comparators), and the circuit is quite small in IC area (e.g., embodiments may be 10-20 smaller than the circuit of FIG. 8). Embodiments of the circuit shown in FIG. 9 solution may be configured to have a very fast response time and so can easily protect a converter circuit 102. Some embodiments have a response time of about 5 ns, well-less than a typical dead time duration of 10 ns or more.

[0050] As should be appreciated, other circuits may be used to implement the V.sub.X Detection Block 600 of FIG. 6 now that this disclosure makes clear the connection between dead time DT and V.sub.X drop with respect to V.sub.OUT leading to excessive in-rush current and resulting switch damage in a converter circuit. Further, the converter circuit, the control circuit, the voltage node V.sub.X, and the V.sub.X Detection Block 600 may be embodied in a single integrated circuit die.

Falling V.SUB.IN .Events in Adiabatic Charge Pumps

[0051] Some of the circuits described above for preventing excessive in-rush current during dead time periods concurrent with short circuit events by monitoring for rapid changes in V.sub.X are also useful for preventing excessive in-rush current due to rapidly falling values of V.sub.IN.

[0052] To understand the problem of rapidly falling values of V.sub.IN, it may be useful to refer back to FIG. 2 as one example of a divide-by-two adiabatic converter circuit. When the charge pump 201 operates normally, the circuit is considered to be “balanced”. During the cycle period when the clock signal P1 in ON and the clock signal P2 is OFF, then charge equal to V.sub.IN−V.sub.X accumulates across the charge pump capacitors Cfly1, Cfly2. For example, if V.sub.IN=10V, then the divide-by-two voltage V.sub.X=5V, and the charge across the charge pump capacitors Cfly1, Cfly2 is thus 5V. During the cycle period when the clock signal P1 in OFF and the clock signal P2 is ON, then the charge pump capacitors Cfly1, Cfly2 are switched to ground and hence V.sub.X (and V.sub.OUT) are refreshed with charge; in this example, to 5V. Accordingly, during normal balanced operation, the voltage differential across any switch (P1x and P2x in this example) is very small and in-rush current is limited.

[0053] However, if V.sub.IN falls rapidly (for example, from 10V to 9V), then the charge that accumulates across the charge pump capacitors Cfly1, Cfly2 is V.sub.IN−V.sub.X, or 4V in this numeric example. When the charge pump capacitors Cfly1, Cfly2 are then coupled to the C.sub.VX and C.sub.OUT capacitors, previously charged to V.sub.X and V.sub.OUT values of 5V before the rapid fall of V.sub.IN, then a voltage differential of 1V is present across the P2x switches. If each P2x switch has an ON resistance of 5 milliohms, then 200 A could momentarily flow in those switches. This level of current spike, in combination with parasitic inductances, can produce voltage spikes that are high enough to damage the switches. Note that if V.sub.IN falls relatively slowly (e.g., over several charge pump cycles), the switches will not be damaged, and charge is transferred from V.sub.OUT back to V.sub.INas a ×2 function (i.e., multiplication from V.sub.OUT to V.sub.IN, rather than normal division from V.sub.IN to V.sub.OUT).

[0054] Thus, as in the case of excessive in-rush current during dead time periods concurrent with short circuit events caused by rapid changes in V.sub.X, excessive in-rush current can be caused by rapidly falling values of V.sub.IN to a converter circuit 102. There are several reasons why V.sub.IN may fall rapidly and cause damage, including (but not limited to): a fault in the power supply providing V.sub.IN; a user switching from a mains supply to a battery; a sudden fault in a battery pack; a sudden drain on a power supply source for V.sub.IN by another circuit that results in V.sub.IN dropping; a damage to a capacitor coupled to V.sub.IN; and/or a short circuit. Ideally, in any of these cases, the converter circuit 102 should not be damaged.

[0055] Referring to FIG. 6, in addition to the V.sub.X Detection Block 600 described above, a V.sub.IN Detection Block 602 may be included. One input to the V.sub.IN Detection Block 602 is coupled to V.sub.IN. As described in greater detail below, in some embodiments, another input to the V.sub.IN Detection Block 602 is coupled to V.sub.X or to V.sub.OUT. An output of the V.sub.IN Detection Block 602, ΔV.sub.IN Detected, is coupled to a control circuit to disable operation of an associated converter circuit 102, such as by disabling the clock signals P1, P2 to the converter circuit 102. The control circuit may be the controller 104 for the core block 101, or alternatively may be any other control circuitry that disables operation of the associated converter circuit 102.

[0056] The V.sub.IN Detection Block 602 should detect large, rapid falls in V.sub.IN, and, as a result, generate a ΔV.sub.IN Detected signal that disables or interrupts operation of the converter circuit 102 (e.g., disable or interrupt the switches of a charge pump), thereby prevent damaging current spikes. The V.sub.IN Detection Block 602 may detect large, rapid falls in V.sub.IN on an absolute basis, or may compare V.sub.IN to V.sub.X or V.sub.OUT to determine if V.sub.IN has fallen below the correct multiple of V.sub.X or V.sub.OUT corresponding to the boost or buck factor of a particular converter circuit 102. The V.sub.IN Detection Block 602 and the control circuit should have relatively short response times (e.g., around 500 ns or less), but in most cases need not be as fast as the V.sub.X Detection Block 600. The V.sub.IN Detection Block 602 should also avoid overly loading the V.sub.X line, which would deteriorate efficiency.

[0057] FIG. 10 is a schematic diagram of a first embodiment of a circuit suitable for use as the V.sub.IN Detection Block 602 of FIG. 6. The voltage V.sub.IN is coupled to a scaling circuit 1002, shown as a resistive divider comprising series-coupled resistors R1 and R2 coupled between V.sub.IN and a reference potential, such as circuit ground. A node between the series-coupled resistors R1 and R2 is coupled to a first input of a comparator 1004 and provides a scaled voltage V.sub.IN′ to the comparator 1004 (preferably just below the usual operational level of V.sub.X). A second input of the comparator 1004 is coupled to either V.sub.X or V.sub.OUT; V.sub.X may be preferred over V.sub.OUT as being closer to the switches P1x, P2x in the converter circuit 102 and not affected as much by the inductor L. In some embodiments, one or both of the resistors R1 and R2 may be settable or variable in order to provide a desired scaled voltage to the comparator 1004 (only R2 is shown as variable in the illustrated example).

[0058] In operation, V.sub.IN is scaled by the scaling circuit 1002, the output of which, V.sub.IN′, is then compared to the then-current value of V.sub.X (or V.sub.OUT) by the comparator 1004. If V.sub.IN′ should rapidly fall below V.sub.X (or V.sub.OUT), then the output of the comparator 1004 would change state, which may be used to command a control circuit (e.g., the controller 104) to disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102). Note that in some embodiments, filtering and hysteresis circuits may be added to filter out glitches and spikes from V.sub.IN and V.sub.X (or V.sub.OUT). The circuit shown in FIG. 10 is particularly useful for step-down (buck) power converters.

[0059] The circuit of FIG. 8 may also be used to implement the V.sub.IN Detection Block 602 of FIG. 6. The circuit would work as described above, except that the input would be V.sub.IN rather than V.sub.X, and the filtered (averaged) value would be V.sub.IN′ rather than V.sub.X′. The values of R3 and C2 may be selected to result in an RC time constant that ensures a minimal voltage fall for V.sub.IN over one clock cycle of the converter circuit 102. In operation, while the filtered (averaged) value of V.sub.IN applied to the source of the PMOS FET M1 is equal to the value of V.sub.IN applied to the gate of the PMOS FET M1, then the PMOS FET M1 will be OFF, the input to the inverter 802 will be in a first logic state, and the output of the inverter 802 will be in an inverted second logic state. However, if V.sub.IN rapidly falls below the filtered (averaged) value of V.sub.IN by at least the threshold voltage V.sub.T of the PMOS FET M1, then the PMOS FET M1 will be ON, the input to the inverter 802 will be in the second logic state, and the output of the inverter 802 will be inverted to the first logic state. Thus, the change in state of the inverter 802 output may be used to command a control circuit (e.g., the controller 104) to, for example, disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102) and/or the entire power converter, or cause the power converter to enter a safe mode of operation. As described above, an optional source degeneration resistor R4 may be coupled between a node coupling resistor R3 and capacitor C2, and the source of the PMOS FET M1, to allow adjustment of the effective threshold voltage V.sub.T of the PMOS FET M1.

[0060] Similarly, the circuit of FIG. 9 may also be used to implement the V.sub.IN Detection Block 602 of FIG. 6. The circuit would work as described above, except that the input would be V.sub.IN rather than V.sub.X, and the sampled-and-held value would be V.sub.IN′ rather than V.sub.X′. In operation, the switch Sw2 would be opened periodically in order to sample the voltage on V.sub.IN at that moment of time and hold that sampled voltage, V.sub.IN′, on the capacitor C3. While V.sub.IN as applied to the gate of the PMOS FET M2 is equal to the sampled-and-held voltage value V.sub.IN′ applied to the source of the PMOS FET M2 (i.e., V.sub.S=V.sub.G), then the PMOS FET M2 will be OFF (non-conducting). Accordingly, the input to the inverter 802 will be in a first logic state (e.g., “1”) and the output of the inverter 802 will be in an inverted second logic state (e.g., “0”). However, if V.sub.IN rapidly falls below V.sub.IN′ by at least the threshold voltage V.sub.T of the PMOS FET M2, then the PMOS FET M2 will be ON (conducting). Accordingly, the input to the inverter 802 will be in the second logic state (e.g., “0”) and the output of the inverter 802 will be inverted to the first logic state (e.g., “1”). Thus, the change in state of the inverter 802 output may be used to command a control circuit (e.g., the controller 104) to, for example, disable operation of the associated converter circuit 102 (e.g., by interrupting the clock signals P1, P2 driving the converter circuit 102) and/or the entire power converter, or cause the power converter to enter a safe mode of operation. As described above, an optional source degeneration resistor R5 may be coupled between the voltage V.sub.IN′ at the capacitor C3 and the source of the PMOS FET M2 to allow adjustment of the effective threshold voltage V.sub.T of the PMOS FET M1.

[0061] As should be appreciated, other circuits may be used to monitor V.sub.IN, including variants of the circuit shown in FIG. 7. Of note, use of the circuits of FIGS. 7, 8, and 9 for the V.sub.IN Detection Block 602 of FIG. 6 require monitoring of only V.sub.IN, and thus impose no load on V.sub.X or V.sub.OUT. Further, the converter circuit, the control circuit, and the V.sub.IN Detection Block 602 may be embodied in a single integrated circuit die.

System Aspects

[0062] Embodiments of the present invention may be used to protect many types of power converters, including buck and/or boost power converters, and whether or not of an adiabatic inductor design, in which even a low voltage difference between the charge pump capacitors and V.sub.X may cause high in-rush currents leading to a large voltage spike across switch devices, particularly MOSFET switches.

[0063] Embodiments of the present invention provide circuits and methods for protecting the switches of charge pump-based power converters from damage if a V.sub.OUT short circuit event occurs and/or if V.sub.IN falls rapidly with respect to V.sub.X or V.sub.OUT, all without substantially decreasing the efficiency of such power converters. As a person of ordinary skill in the art will understand, a system architecture is beneficially impacted by the current invention in critical ways, including greater reliability and durability.

Methods

[0064] Another aspect of the invention includes methods for protecting a power converter from in-rush current. For example, FIG. 11 is a process flow chart 1100 showing a first method for protecting a power converter from in-rush current. The method includes monitoring a voltage node V.sub.X of a converter circuit of the power converter (Block 1102); and disabling operation of the converter circuit upon detection of a voltage drop (especially a large, rapid voltage drop) at the voltage node V.sub.X (Block 1104). An additional aspect of the above method may include monitoring the voltage node V.sub.X for a voltage drop that occurs during a dead time between non-overlapping clock signals controlling operation of the converter circuit.

[0065] As another example, FIG. 12 is a process flow chart 1200 showing a second method for protecting a power converter from in-rush current. The method includes monitoring a voltage node V.sub.IN of a converter circuit of the power converter (Block 1102); and disabling operation of the converter circuit upon detection of a voltage drop (especially a large, rapid voltage drop) at the voltage node V.sub.IN (Block 1104). An additional aspect of the above method may include detecting a voltage drop of the input voltage V.sub.IN relative to one of an output voltage V.sub.OUT of the power converter or a voltage node V.sub.X of the converter circuit.

Fabrication Technologies & Options

[0066] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0067] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0068] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0069] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0070] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

Conclusion

[0071] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.

[0072] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).