Abstract
A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a TFT serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the TFT, and a source potential of the TFT is connected to a fixed potential through a TFT serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.
Claims
1. A display device, comprising a plurality of pixel circuits, wherein at least one of the plurality of pixel circuits includes: a drive transistor having a gate, a source and a drain electrode, and configured to supply a drive current from a power supply line to a light emitting element, the source electrode being directly connected to an anode electrode of the electro-optic element; a capacitor having a first electrode connected to the source electrode and a second electrode connected to the gate electrode, and wherein the drive transistor is an n-type TFT and includes amorphous silicon.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0052] These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the accompanying drawings, in which:
[0053] FIG. 1 is a block diagram of the configuration of a general organic EL display device;
[0054] FIG. 2 is a circuit diagram of an example of the configuration of a pixel circuit of FIG. 1;
[0055] FIG. 3 is a graph of the change along with time of the current-voltage (I-V) characteristic of an organic EL device;
[0056] FIG. 4 is a circuit diagram of a pixel circuit in which p-channel TFTs of the circuit of FIG. 2 are replaced by re-channel TFTs;
[0057] FIG. 5 is a graph showing the operating point of a TFT serving as a drive transistor and an EL emitting element in the initial state;
[0058] FIG. 6 is a graph showing the operating point of a TFT serving as a drive transistor and an EL emitting element after change along with time;
[0059] FIG. 7 is a circuit diagram of a pixel circuit connecting a source of an n-channel TFT serving as a drive transistor to a ground potential;
[0060] FIG. 8 is a circuit diagram of an example of an ideal pixel circuit enabling source-follower output with no deterioration of luminance even after the I-V characteristic of an EL light emitting element changes along with time;
[0061] FIG. 9 is a view for explaining the layout of Vss (reference power source) interconnects and Vcc (power source voltage) interconnects in the related art;
[0062] FIG. 10 is a block diagram of the configuration of an organic EL display device employing a pixel circuit according to a first embodiment of the present invention;
[0063] FIG. 11 is a circuit diagram of a specific configuration of a pixel circuit according to the first embodiment of the invention in the organic EL display device of FIG. 10;
[0064] FIG. 12 is a view for explaining the layout of Vss (reference power source) interconnects and Vcc (power source voltage) interconnects according to the first embodiment of the invention;
[0065] FIG. 13A is a view of an equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0066] FIG. 13B is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0067] FIG. 13C is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0068] FIG. 13D is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0069] FIG. 13E is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0070] FIG. 13F is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 11;
[0071] FIG. 14A is a timing chart for explaining the operation of the circuit of FIG. 11;
[0072] FIG. 14B is another timing chart for explaining the operation of the circuit of FIG. 11;
[0073] FIG. 14C is another timing chart for explaining the operation of the circuit of FIG. 11;
[0074] FIG. 14D is another timing chart for explaining the operation of the circuit of FIG. 11;
[0075] FIG. 14E is another timing chart for explaining the operation of the circuit of FIG. 11;
[0076] FIG. 14F is another timing chart for explaining the operation of the circuit of FIG. 11;
[0077] FIG. 15 is a block diagram of the configuration of an organic EL display device employing a pixel circuit according to a second embodiment of the present invention;
[0078] FIG. 16 is a circuit diagram of a specific configuration of a pixel circuit according to the second embodiment of the invention in the organic EL display device of FIG. 15;
[0079] FIG. 17A is a view of an equivalent circuit for explaining the operation of the circuit of FIG. 16;
[0080] FIG. 17B is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 16;
[0081] FIG. 17C is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 16;
[0082] FIG. 17D is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 16;
[0083] FIG. 17E is another view of the equivalent circuit for explaining the operation of the circuit of FIG. 16;
[0084] FIG. 18A is a timing chart for explaining the operation of the circuit of FIG. 16;
[0085] FIG. 18B is another timing chart for explaining the operation of the circuit of FIG. 16;
[0086] FIG. 18C is another timing chart for explaining the operation of the circuit of FIG. 16
[0087] FIG. 18D is another timing chart for explaining the operation of the circuit of FIG. 16;
[0088] FIG. 18E is another timing chart for explaining the operation of the circuit of FIG. 16;
[0089] FIG. 18F is another timing chart for explaining the operation of the circuit of FIG. 16;
[0090] FIG. 18G is another timing chart for explaining the operation of the circuit of FIG. 16; and
[0091] FIG. 18H is another timing chart for explaining the operation of the circuit of FIG. 16.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0092] Below, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
First Embodiment
[0093] FIG. 10 is a block diagram of the configuration of an organic EL display device employing pixel circuits according to the first embodiment. FIG. 11 is a circuit diagram of the concrete configuration of a pixel circuit according to the first embodiment in the organic EL display device of FIG. 10. This display device 100 has, as shown in FIG. 10 and FIG. 11, a pixel array portion 102 having pixel circuits (PXLC) 101 arranged in an m×n matrix, a horizontal selector (HSEL) 103, a write scanner (WSCN) 104, a drive scanner (DSCN) 105, data lines DTL101 to DTL10n selected by the horizontal selector 103 and supplied with a data signal in accordance with the luminance information, scanning lines WSL101 to WSL10m selectively driven by the write scanner 104, and drive lines DSL101 to DSL10m selectively driven by the drive scanner 105.
[0094] Note that while the pixel circuits 101 are arranged in an m×n matrix in the pixel array portion 102, FIG. 11 shows an example wherein the pixel circuits are arranged in a 2 (=m)×3 (=n) matrix for the simplification of the drawing. Further, in FIG. 11, the concrete configuration of one pixel circuit is shown for simplification of the drawing.
[0095] The pixel circuit 101 according to the first embodiment has, as shown in FIG. 11, an n-channel TFT 111 to TFT 113, a capacitor C111, a light emitting element 114 made of an organic EL element (OLED), a node ND111, and a node ND112. Further, in FIG. 11, DTL101 indicates a data line, WSL101 indicates a scanning line, and DSL101 indicates a drive line. Among these constituent elements, TFT 111 configures the drive transistor according to the present invention, TFT 112 configures the first switch, TFT 113 configures the second switch, and the capacitor C111 configures the pixel capacitance element according to the present invention. Further, the supply line of the power source voltage Vcc corresponds to the power source voltage source, while the ground potential GND corresponds to the reference potential.
[0096] In the pixel circuit 101, a light emitting element (OLED) 114 is connected between the source of the TFT 111 and the reference potential (in this present embodiment, the ground potential GND). Specifically, the anode of the light emitting diode 114 is connected to the source of the TFT 111, while the cathode side is connected to the ground potential GND. The connection point of the anode of the light emitting element 114 and the source of the TFT 111 constitutes a node ND111. The source of the TFT 111 is connected to the drain of the TFT 113 and a first electrode of the capacitor C111, while the gate of the TFT 111 is connected to a node ND112. The source of the TFT 113 is connected to a fixed potential (in the present embodiment, a reference power source interconnect Vss line VSL101 set to the ground potential GND), while the gate of the TFT 113 is connected to the drive line DSL101. Further, a second electrode of the capacitor C111 is connected to the node ND112. The data line DTL101 and node ND112 are connected to a source and drain of the TFT 112 serving as the first switch. Further, the gate of the TFT 112 is connected to the scanning line WSL101.
[0097] In this way, the pixel circuit 101 according to the present embodiment is configured with a capacitor C111 connected between the gate and source of the TFT 111 serving as the drive transistor and with a source potential of the TFT 111 connected to a fixed potential through the TFT 113 serving as the switch transistor.
[0098] In the present embodiment, as shown in FIG. 12, the pixel circuit power source voltage Vcc lines VCL101 to VCL10n are input from a pad 106 above the panel including the pixel array portion 102. These interconnects are laid out in a vertical direction with respect to the panel, that is, for every column of the pixel array. Further, the Vss lines VSL are taken out from the left and right of the panel in the figure at the cathode Vss pads 107 and 108 as the Vss lines VSLL and VSLR. Further, a Vss line VSLU connected at an upper side of the panel and a Vss line VSLB connected at a bottom side of the panel are provided. As shown in FIG. 11 and FIG. 12, the pixel circuit Vss lines VSL101 to VSL10n are connected between the Vss line VSLU and Vss VSLB and are arranged in parallel to the pixel circuit power source voltage Vcc lines VCL101 to VCL10n. That is, the Vss (reference power source) interconnects are arranged at the entire periphery of the pixel array portion 102. In the figure, the Vss lines VSL101 to VSL10n are laid out for each column of the pixel array between the Vss line VSLU and Vss line VSLB arranged in the x-direction above and below the pixel array portion 102. In the present embodiment, overlap between the Vss (reference power source) interconnects and Vcc (power source voltage source) interconnects is prevented. Therefore, it is possible to lay out the Vss interconnects by a lower resistance than in the past. Further, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than horizontal direction (x-direction) in a general angle of view, so if the line width is the same, it is possible to lay out Vss interconnects with a lower resistance than the past.
[0099] Next, the operation of the above configuration will be explained focusing on the operation of a pixel circuit with reference to FIGS. 13A to 13F and FIGS. 14A to 14F. Note that FIG. 14A shows a scanning signal ws[101] applied to the first scanning line WSL101 of the pixel array, FIG. 14B shows a scanning signal ws[102] applied to the second scanning line WSL102 of the pixel array, FIG. 14C shows a drive signal ds[101] applied to the first drive line DSL101 of the pixel array, FIG. 14D shows a drive signal ds[101] applied to the second drive line DSL102 of the pixel array, FIG. 14E shows a gate potential Vg of the TFT 111, and FIG. 14F shows a source potential Vs of the TFT 111.
[0100] First, at the time of the emitting state of an ordinary EL light emitting element 114, as shown in FIGS. 14A to 14D, the scanning signals ws[101], ws[102], . . . to the scanning lines WSL101, WSL102, . . . are selectively set to the low level by the write scanner 104, and the drive signals ds[101], ds[102], . . . to the drive lines DSL101, DSL102, . . . are selectively set to the low level by the drive scanner 105. As a result, in the pixel circuits 101, as shown in FIG. 13A, the TFT 112 and TFT 113 are held in the off state.
[0101] Next, in the non-emitting period of the EL light emitting element 114, as shown in FIGS. 14A to 14D, the scanning signals ws[101], ws[102], . . . to the scanning lines WSL101, WSL102, . . . are held at the low level by the write scanner 104, and the drive signals ds[101], ds[102], . . . to the drive lines DSL101, DSL102, . . . are selectively set to the high level by the drive scanner 105. As a result, in the pixel circuits 101, as shown in FIG. 13B, the TFT 112 is held in the off state and the TFT 113 is turned on. At this time, current flows through the TFT 113 and, as shown in FIG. 14F, the source potential Vs of the TFT 111 falls to the ground potential GND. Therefore, the voltage applied to the EL light emitting element 114 also becomes 0V and the EL light emitting element 114 becomes non-emitting in state.
[0102] Next, in the non-emitting period of the EL light emitting element 114, as shown in FIGS. 14A to 14D, the drive signals ds[101], ds[102], . . . to the drive lines DSL101, DSL102, . . . are held at the high level by the drive scanner 105, and the scanning signals ws[101], ws[102], . . . to the scanning lines WSL101, WSL102, . . . are selectively set to the high level by the write scanner 104. As a result, in the pixel circuits 101, as shown in FIG. 13C, the TFT 113 is held in the on state and the TFT 112 is turned on. Due to this, the input signal (Vin) propagated to the data line DTL101 by the horizontal selector 103 is written into the capacitor C111 as the pixel capacity. At this time, as shown in FIG. 14F, the source potential Vs of the TFT 111 serving as the drive transistor is at the ground potential level (GND level), so, as shown in FIGS. 14E and 14F, the potential difference between the gate and source of the TFT 111 becomes equal to the voltage Vin of the input signal.
[0103] After this, in the non-emitting period of the EL light emitting element 114, as shown in FIGS. 14A to 14D, the drive signals ds[101], ds[102], . . . to the drive lines DSL101, DSL102, . . . are held at the high level by the drive scanner 105 and the scanning signals ws[101], ws[102], . . . to the scanning lines WSL101, WSL102, . . . are selectively set to the low level by the write scanner 104. As a result, in the pixel circuit 101, as shown in FIG. 13D, the TFT 112 is turned off and the write operation of the input signal to the capacitor C111 serving as the pixel capacity ends.
[0104] After this, as shown in FIGS. 14A to 14D, the scanning signals ws[101], ws[102], . . . to the scanning lines WSL101, WSL102, . . . are held at the low level by the write scanner 104 and the drive signals ds[101], ds[102], . . . to the drive lines DSL101, DSL102, . . . are selectively set to the low level by the drive scanner 104. As a result, in the pixel circuit 101, as shown in FIG. 13E, the TFT 113 is turned off. By turning the TFT 113 off, as shown in FIG. 14F, the source potential Vs of the TFT 111 serving as the drive transistor rises and current also flows to the EL light emitting element 114.
[0105] The source potential Vs of the TFT 111 fluctuates, but despite this, since there is a capacity between the gate and source of the TFT 111, as shown in FIGS. 14E and 14F, the gate-source potential is constantly held at Vin. At this time, the TFT 111 serving as the drive transistor drives in the saturated region, so the current Ids flowing through the TFT 111 becomes the value shown in the above equation 1. This value is determined by the gate source potential Vin of the TFT 111. This current Ids similarly flows to the EL light emitting element 114, whereby the EL light emitting element 114 emits light. The equivalent circuit of the EL light emitting element 114 becomes as shown in FIG. 13F, so at this time the potential of the node ND111 rises to the gate potential by which the current Ids flows through the EL light emitting element 114. Along with this rise in potential, the potential of the node ND112 also similarly rises through the capacitor 111 (pixel capacity Cs). Due to this, as explained above, the gate-source potential of the TFT 111 is held at Vin.
[0106] Here, consider the problems in the source-follower system of the related art in the circuit of the present invention. In this circuit as well, the EL light emitting element deteriorates in its I-V characteristic along with the increase in the emitting period. Therefore, even if the drive transistor sends the same current, the potential applied to the EL light emitting diode changes and the potential of the node ND111 falls. However, in this circuit, the potential of the node ND111 falls while the gate-source potential of the drive transistor is held constant, so the current flowing through the drive transistor (TFT 111) does not change. Accordingly, the current flowing through the EL light emitting element also does not change. Even if the I-V characteristic of the EL light emitting element deteriorates, a current corresponding to the input voltage Vin constantly flows. Therefore, the problem of the related art can be solved.
[0107] As explained above, according to the present embodiment, the source of each TFT 111 serving as a drive transistor is connected to the anode of the light emitting element 114, the drain is connected to the power source potential Vcc, a capacitor C111 is connected between the gate and source of the TFT 111, and the source potential of the TFT 111 is connected to a fixed potential through the TFT 113 serving as the switch transistor and, further, the pixel circuit Vss lines VSL101 to VSL10n are connected by the Vss line VSLU and Vss line VSLB and arranged in parallel to the pixel circuit power source voltage Vcc lines VCL101 to VCL10n, so the following effects can be obtained.
[0108] Since the Vss interconnects are laid out in the y-direction (vertical direction), the TFTs 113 of the pixel circuits connected to the Vss lines VSL101 to VSL10n turn on at a single timing for 1H. Therefore, the fluctuation entering the interconnects becomes smaller and the uniformity is improved.
[0109] In addition, as explained above, the Vcc interconnects of the pixel array portion 102 are generally laid out in parallel in the y-direction with respect to the panel. Accordingly, in this embodiment, in the interconnects at the valid pixel portion, it is possible to lay out the Vss interconnects and the Vcc interconnects in parallel and possible to prevent overlap of the Vss interconnects and Vcc interconnects. Therefore, it is possible to lay out the Vss interconnects with less resistance than the past. In addition, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so with the same line width, it is possible to lay out the Vss interconnects by a lower resistance than the past. Further, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of an EL light emitting element along with time becomes possible. Further, a source-follower circuit of n-channel transistors becomes possible, so it is possible to use an n-channel transistor as a drive element of an EL light emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible.
Second Embodiment
[0110] FIG. 15 is a block diagram of the configuration of an organic EL display device employing pixel circuits according to a second embodiment. FIG. 16 is a circuit diagram of the concrete configuration of a pixel circuit according to the second embodiment in the organic EL display device of FIG. 15.
[0111] The display device 200, as shown in FIG. 15 and FIG. 16, has a pixel array portion 202 having pixel circuits (PXLC) 201 arranged in an m×n matrix, a horizontal selector (HSEL) 203, a first write scanner (WSCN1) 204, a second write scanner (WSCN2) 205, a drive scanner (DSCN) 206, data lines DTL201 to DTL20n selected by the horizontal selector 203 and supplied with a data signal in accordance with the luminance information, scanning lines WSL201 to WSL20m selectively driven by the write scanner 204, scanning lines WSL211 to WSL21m selectively driven by the write scanner 205, and drive lines DSL201 to DSL20m selectively driven by the drive scanner 206.
[0112] Note that while the pixel circuits 201 are arranged in an m×n matrix in the pixel array portion 202, FIG. 15 shows an example wherein the pixel circuits are arranged in a 2 (=m)×3 (=n) matrix for the simplification of the drawing. Further, in FIG. 16 as well, the concrete configuration of one pixel circuit is shown for simplification of the drawing.
[0113] In the second embodiment as well, like in the first embodiment, as shown in FIG. 12, the pixel circuit power source voltage Vcc lines VCL201 to VCL20n are input from a pad 106 above the panel including the pixel array portion 202 and are laid out in the vertical direction with respect to the panel, that is, for each column of the pixel array. Further, the Vss lines VSL are taken out from the left and right of the panel in the figure at the cathode Vss pads 107 and 108 as the Vss lines VSLL and VSLR. Further, a Vss line VSLU connected at an upper side of the panel and a Vss line VSLB connected at a bottom side of the panel are provided. As shown in FIG. 16 and FIG. 12, the pixel circuit Vss lines VSL101 to VSL10n are connected between the Vss line VSLU and Vss line VSLB and are arranged in parallel to the pixel circuit power source voltage Vcc lines VCL201 to VCL20n. That is, the Vss (reference power source) interconnects are arranged at the entire periphery of the pixel array portion 202. In the figure, Vss lines VSL201 to VSL20n are laid out for each column of the pixel array between the Vss line VSLU and Vss line VSLB arranged in the x-direction above and below the pixel array portion 202. In the present embodiment, overlap between the Vss (reference power source) interconnects and the Vcc (power source voltage source) interconnects is prevented. Therefore, the Vss interconnects can be laid out by a lower resistance than in the past. Further, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so with the same line width, it is possible to lay out the Vss inerconnects with a lower resistance than the past.
[0114] Each pixel circuit 201 according to the second embodiment has, as shown in FIG. 16, an n-channel TFT 211 to TFT 214, a capacitor C211, a light emitting element 215 made of an organic EL element (OLED), a node ND211, and a node ND212. Further, in FIG. 16, DTL201 indicates a data line, WSL201 and WSL211 indicate scanning lines, and DSL201 indicates a drive line. Among these constituent elements, TFT 211 configures the FET according to the present invention, TFT 212 configures the first switch, TFT 213 configures the second switch, TFT 214 configures the third switch, and the capacitor C211 configures the pixel capacitance element according to the present invention. Further, the supply line of the power source voltage Vcc corresponds to the power source voltage source, while the ground potential GND corresponds to the reference potential.
[0115] In each pixel circuit 201, the source and drain of the TFT 213 are connected between the source of the TFT 211 and the anode of the light emitting element 215, the drain of the TFT 211 is connected to the power source potential Vcc, and the cathode of the light emitting element 215 is connected to the ground potential GND. That is, the TFT 211 serving as the drive transistor, the TFT 213 serving as the switch transistor, and the light emitting element 215 are connected in series between the power source potential Vcc and the ground potential GND. Further, the connection point of the source of the TFT 213 and the anode of the light emitting element 215 constitutes a node ND211. The gate of the TFT 211 is connected to the node ND212. Further, a capacitor C211 serving as the pixel capacity Cs is connected between the nodes ND211 and ND212, that is, between the gate and source of the TFT 211. The first electrode of the capacitor C211 is connected to the node ND211, while the second electrode is connected to the node ND212. The gate of the TFT 213 is connected to the drive line DSL201. Further, the source and drain of the TFT 212 serving as the first switch are connected to the data line DTL201 and the node ND212. Further, the gate of the TFT 212 is connected to the scanning line WSL201. Further, the source and drain of the TFT 214 are connected between the source (node ND211) of the TFT 213 and the Vss line VSL201, while the gate of the TFT 214 is connected to the scanning line WSL211.
[0116] In this way, the pixel circuit 201 according to the present embodiment is configured with the source of the TFT 211 serving as the drive transistor and the anode of the light emitting element 215 connected by the TFT 213 serving as the switching transistor, with a capacitor C211 connected between the gate and source of the TFT 211, and with a source potential of the TFT 213 connected to the reference power source interconnect constituted by the Vss line VSL201 (fixed voltage line) through the TFT 214.
[0117] Next, the operation of the above configuration will be explained focusing on the operation of a pixel circuit with reference to FIGS. 17A to 17E and FIGS. 18A to 18H. Note that FIG. 18A shows a scanning signal ws[201] applied to the first scanning line WSL201 of the pixel array, FIG. 18B shows a scanning signal ws[202] applied to the second scanning line WSL202 of the pixel array, FIG. 18C shows a scanning signal ws[211] applied to the first scanning line WSL211 of the pixel array, FIG. 18D shows a scanning signal ws[212] applied to the second scanning line WSL212 of the pixel array, FIG. 18E shows a drive signal ds[201] applied to the first drive line DSL201 of the pixel array, FIG. 18F shows a drive signal ds[202] applied to the second drive line DSL202 of the pixel array, FIG. 18G shows a gate potential Vg of the TFT 211, and FIG. 18H shows an anode side potential of the TFT 211, that is, the potential VND211 of the node ND211.
[0118] First, at the ordinary emitting state of an EL light emitting element 215, as shown in FIGS. 18A to 18F, the scanning signals ws[201], ws[202], . . . to the scanning lines WSL201, WSL202, . . . are selectively set to the low level by the write scanner 204, the scanning signals ws[211], ws[212], . . . to the scanning lines WSL211, WSL212, . . . are selectively set to the low level by the write scanner 205, and the drive signals ds[201], ds[202], . . . to the drive lines DSL201, DSL202, . . . are selectively set to the high level by the drive scanner 206. As a result, in the pixel circuit 201, as shown in FIG. 17A, the TFT 212 and TFT 214 are held in the off state and the TFT 213 is held in the on state. At this time, the TFT 211 serving as the drive transistor drives in the saturated region, so the current Ids for the gate-source voltage Vgs flows to the TFT 211 and the EL light emitting element 215.
[0119] Next, in the non-emitting period of an EL light emitting element 215, as shown in FIGS. 18A to 18F, the scanning signals ws[201], ws[202], . . . to the scanning lines WSL201, WSL202, . . . are held at the low level by the write scanner 204, the scanning signals ws[211], ws[212], . . . to the scanning lines WSL211, WSL212, . . . are held at the low level by the write scanner 205, and the drive signals ds[201], ds[202], . . . to the drive lines DSL201, DSL202, . . . are selectively set to the low level by the drive scanner 206. As a result, in the pixel circuit 201, as shown in FIG. 17B, the TFT 212 and TFT 214 are held in the off state and the TFT 213 is turned off. At this time, the potential held at the EL light emitting element 215 falls since the source of supply disappears and the EL light emitting element 215 no longer emits light. The potential falls to the threshold voltage Vth of the EL light emitting element 215. However, since current also flows to the EL light emitting element 215, if the non-emitting period continues, the potential will fall to GND. On the other hand, the TFT 211 serving as the drive transistor is held in the on state since the gate potential is high. As shown in FIG. 18G, the source potential of the TFT 211 is boosted to the power source voltage Vcc. This boosting is performed in a short period. After boosting of the Vcc, no current is supplied to the TFT 211. That is, in the pixel circuit 201 of the second embodiment, it is possible to operate without the supply of current in the pixel circuit during the non-emitting period and therefore possible to suppress the power consumption of the panel.
[0120] Next, in the non-emitting period of an EL light emitting element 215, as shown in FIGS. 18A to 18F, the drive signals ds[201], ds[202], . . . to the drive lines DSL201, DSL202, . . . are held at the low level by the drive scanner 206, the scanning signals ws[201], ws[202], . . . to the scanning lines WSL201, WSL202, . . . are selectively set to the high level by the write scanner 204, and the scanning signals ws[211], ws[212], . . . to the scanning lines WSL211, WSL212, . . . are selectively set to the high level by the write scanner 205. As a result, in the pixel circuit 201, as shown in FIG. 17C, the TFT 213 is held in the off state and the TFT 212 and TFT 214 are turned on. Due to this, the input signal (Vin) propagated to the data line DTL201 by the horizontal selector 203 is written into the capacitor C211 serving as the pixel capacity Cs. When writing the signal line voltage, it is important that the TFT 214 be turned on. If there were no TFT 214, if the TFT 212 were turned on and the video signal were written in the pixel capacity Cs, coupling would enter the source potential Vs of the TFT 211. As opposed to this, if turning on the TFT 214 connecting the node ND211 to the Vss line VSL201, it will be connected to the low impedance interconnect line, so the voltage of the interconnect line would be written into the source potential of the TFT 211. At this time, if making the potential of the interconnect line Vo, the source potential of the TFT 211 serving as the drive transistor becomes Vo, so a potential equal to (Vin-Vo) is held with respect to the voltage Vin of the input signal at the fixed capacity Cs.
[0121] After this, in the non-emitting period of the EL light emitting element 215, as shown in FIGS. 18A to 18F, the drive signals ds[201], ds[202], . . . to the drive lines DSL201, DSL202, . . . are held at the low level by the drive scanner 206, the scanning signals ws[211], ws[212], . . . to the scanning lines WSL211, WSL212, . . . are held at the high level by the write scanner 205, and the scanning signals ws[201], ws[202], . . . to the scanning lines WSL201, WSL202, . . . are selectively set to the low level by the write scanner 204. As a result, in the pixel circuit 201, as shown in FIG. 17D, the TFT 212 is turned off and the write operation of the input signal to the capacitor C211 serving as the pixel capacity ends. At this time, the source potential of the TFT 211 has to hold the low impedance, so the TFT 214 is left on.
[0122] After this, as shown in FIGS. 18A to 18F, the scanning signals ws[201], ws[202], . . . to the scanning lines WSL201, WSL202, . . . are held at the low level by the write scanner 204, the scanning signals ws[211], ws[212], . . . to the scanning lines WSL211, WSL212, . . . are set to the low level by the write scanner 205, and the drive signals ds[201], ds[202], . . . to the drive lines DSL201, DSL202, . . . are selectively set to the high level by the drive scanner 206. As a result, in the pixel circuit 201, as shown in FIG. 17E, the TFT 214 is turned off and the TFT 213 is turned on. By turning the TFT 213 on, current flows to the EL light emitting element 215 and the source potential of the TFT 211 serving as the drive transistor falls. The source potential Vs of the TFT 1211 serving as the drive transistor fluctuates, but despite this, since there is a capacity between the gate of the TFT 211 and the anode of the EL light emitting element 215, the gate-source potential of the TFT 211 is constantly held at (Vin-Vo).
[0123] At this time, the TFT 211 serving as the drive transistor drives in the saturated region, so the current Ids flowing through the TFT 211 becomes the value shown in the above equation 1. This is the gate-source voltage Vgs of the drive transistor and is (Vin-Vo). That is, the current flowing through the TFT 211 can be said to be determined by the Vin.
[0124] In this way, by turning the TFT 214 on during a signal write period to make the source of the TFT 211 low in impedance, it is possible to make the source side of the TFT 211 of the pixel capacitor a fixed potential (Vss) at all times, there is no need to consider deterioration of image quality due to coupling at the time of a signal line write operation, and it is possible to write the signal line voltage in a short time. Further, it is possible to increase the pixel capacity to take measures against a leak characteristic.
[0125] Due to the above, even if the EL light emitting element 215 changes in its I-V characteristic along with the increase in the emitting period, in the pixel circuit 201 of the second embodiment, the potential of the node ND211 falls while the potential between the gate and source of the TFT 211 serving as the drive transistor is held constant, so the current flowing through the TFT 211 does not change. Accordingly, the current flowing through the EL light emitting element 215 also does not change. Even if the I-V characteristic of the EL light emitting element 215 deteriorates, the current corresponding to the input voltage Vin constantly flows. Source-follower output with no deterioration of the luminance becomes possible even if the I-V characteristic of the EL light emitting element changes along with time. In addition, since there is no transistor other than the pixel capacitor Cs between the gate and source of the TFT 211, the gate-source voltage Vgs of the TFT 211 serving as the drive transistor will not change due to fluctuations in the threshold voltage Vth like in the conventional system.
[0126] Further, in FIG. 16, the potential of the cathode electrode of the light emitting element 215 is made the ground potential GND, but this may be made any other potential as well. Rather, making it a negative power source enables the potential of the Vcc to be lowered and enables the potential of the input signal voltage to be lowered as well. Due to this, it is possible to design a circuit without placing a load on the external IC.
[0127] The transistors of the pixel circuits need not be re-channel transistors. p-channel TFTs may also be used to form each pixel circuit. In this case, the power source is connected to the anode side of the EL light emitting element, while the TFT 211 serving as the drive transistor is connected to the cathode side.
[0128] Further, the TFT 212, TFT 213, and TFT 214 serving as the switching transistors may also be transistors of different polarities from the TFT 211 serving as the drive transistor.
[0129] According to the second embodiment, since the Vss interconnects are laid out in the y-direction, the TFTs 213 of the pixel circuits connected to the Vss lines VSL201 to VSL20n turn on at a single timing with respect to 1H. Accordingly, there is little fluctuation entering the interconnects and the uniformity can be improved. In addition, as explained above, the Vcc interconnects of the pixel array portion 202 are in general laid out in parallel to the y-direction with respect to the panel. Therefore, according to the present embodiment, in the interconnects at the valid pixel parts, the Vss interconnects and Vcc interconnects can be laid out in parallel and overlap between the Vss interconnects and Vcc interconnects can be prevented. For this reason, the Vss interconnects can be laid out with a lower resistance than the past. Further, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so if the line width is the same, it is possible to lay out Vss interconnects with a lower resistance than the past. Further, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of the organic EL emitting element along with time becomes possible. A source-follower circuit of n-channel transistors becomes possible, so it is possible to use an re-channel transistor as a drive element of an organic EL emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible. In addition, according to the second embodiment, it is possible to write a signal line voltage in a short time even for example with a black signal and therefore possible to obtain an image quality of a high uniformity. Simultaneously, it is possible to increase the signal line capacity and suppress a leak characteristic.
[0130] Summarizing the effects of the invention, as explained above, according to the present invention, the pixel circuits connected to the reference power source interconnects turn on at a single timing during the signal sampling period. Therefore, there is little fluctuation entering the interconnects and the uniformity can be improved. In addition, it is possible to prevent overlap between the reference power source interconnects and the power source voltage source interconnects. Therefore, it is possible to lay out the reference power source interconnects by a lower resistance than the past. In addition, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so with the same line width, it is possible to lay out the reference power source interconnects by a lower resistance than the past.
[0131] Further, according to the present invention, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of the organic EL emitting element along with time becomes possible. Further, a source-follower circuit of n-channel transistors becomes possible, so it is possible to use an n-channel transistor as a drive element of an organic EL emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible.
[0132] While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.
