DC BIAS REGULATOR FOR CASCODE AMPLIFIER

Abstract

An amplifier having a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source. A DC bias regulator is provided having: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: and a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source. The DC bias regulator produces a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source.

Claims

1-3. (canceled)

5. An amplifier, comprising: a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source; a DC bias regulator, comprising: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source to produce a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source; and wherein the combiner includes a pair of resistors, and wherein a first one of the pair of resistors is connected between a first one of the pair of inputs and an output of the combiner and a second one of the pair of resistors is connected between a second one of the pair of inputs and the output of the combiner.

6. The amplifier recited in claim 5 wherein the pair of resistors have the same resistances.

7. The amplifier recited in claim 5 wherein the pair of resistors have different resistances.

8. The amplifier recited in claim 5 wherein the pair of resistors have variable resistances.

9. The amplifier recited in claim 5 wherein the DC bias regulator includes a voltage divider circuit and wherein the reference current passes through the voltage divider circuit.

10. The amplifier recited in claim 9 wherein the voltage divider includes a pair of serially connected resistors and wherein the reference current passes through the serially connected resistors, one of the resistors producing the voltage coupled to the control electrode of the first one of the pair of transistors and the combination of the resistors producing the voltage coupled to the combiner.

11. The amplifier recited in claim 5 wherein the DC bias regulator includes a voltage divider circuit and wherein the reference current passes through the voltage divider circuit.

12. The amplifier recited in claim 11 wherein the voltage divider includes a pair of serially connected resistors and wherein the reference current passes through the serially connected resistors, the combination of the resistors producing the voltage coupled to the combiner and the other one of the resistors producing the voltage coupled to the control electrode of the first one of the pair of transistors.

13. The amplifier recited in claim 12 wherein the pair of resistors in the voltage divider have the same resistance.

14. An amplifier, comprising: a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source; a DC bias regulator, comprising: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source to produce a DC bias voltage at a control electrode of a second one of the pair; and wherein the DC bias regulator comprises: a voltage divider; wherein the voltage divider produces: a first output voltage related to the reference current and a second voltage, the second voltage being a predetermined fraction of the first output voltage, the second voltage being coupled to a control electrode of a first one of the pair of transistors; wherein the combiner circuit has a pair of inputs coupled to: the first output voltage produced by the voltage divider; and the first voltage source, respectively, to produce the DC bias voltage at the control electrode of the second one of the pair of transistors related to a combination of the first output voltage produced by the reference voltage and the first voltage source.

15. The amplifier recited in claim 14 wherein the combiner circuit produces the DC bias voltage as a function of the sum of the output voltage produced by the reference voltage and the first voltage source.

16. The amplifier recited in claim 15 wherein the combiner circuit produces the DC bias voltage as a function of the average of the output voltage produced by the reference voltage and the first voltage source.

17. The amplifier recited in claim 15 wherein the current through the reference transistor is a saturation current for the reference transistor and current from the voltage supply to the reference potential is a saturation current for both the first one of the pair of transistors and the second one of the pair of transistors.

18. A cascode amplifier, comprising: a first transistor having a control electrode for controlling a flow of carriers between a first and second electrode; a second transistor having a control electrode for controlling a flow of carriers between a first and second electrode; wherein the first electrode of the first transistor is coupled to a reference potential, the first electrode of the second transistor is coupled to the second electrode of the first transistor, and the second electrode of the second transistor is coupled to a first voltage source; a DC bias regulator, comprising: a reference transistor coupled to a second voltage source; a reference voltage divider circuit serially connected between the reference transistor and the reference potential; wherein the DC bias regulator produces a reference current through the reference transistor and the reference voltage divider produces: a first output voltage related to the reference current and a second voltage, the second voltage being a predetermined fraction of the first output voltage, the second voltage being coupled to the control electrode of the first transistor; a voltage combiner circuit having a pair of inputs coupled to: the first output voltage produced by the reference voltage divider circuit; and the first voltage source, respectively, to produce a DC bias voltage at the control electrode of the second transistor related to a combination of the first output voltage produced by the reference voltage divider circuit and the first voltage source.

19. The cascode amplifier recited in claim 18 wherein the combiner circuit produces the DC bias voltage as a function of the sum of the output voltage produced by the reference voltage and the first voltage source.

20. The cascode amplifier recited in claim 19 wherein the combiner circuit produces the DC bias voltage as a function of the average of the output voltage produced by the reference voltage and the first voltage source

21. The cascode amplifier recited in claim 20 wherein the current through the reference transistor is a saturation current for the reference transistor and current from the voltage supply to the reference potential is a saturation current for both the first and second transistors.

22. The cascode amplifier recited in claim 18 wherein the DC bias voltages produced at the control electrodes of the first transistor and the second transistor produces a voltage across the first and second electrodes the first transistor equal to the voltage across the first and second electrodes of the second transistor.

23-24. (canceled)

25. An amplifier comprising: a first transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode of the first transistor, the first electrode being coupled to a voltage source; a second transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode of the second transistor, the second electrode being coupled to a reference potential; a resistor having one end connected to the second electrode of the first transistor and a second end connected to the first electrode of the second transistor; a DC bias regulator, comprising: a reference transistor; wherein the DC bias regulator produce a reference current through the reference transistor; and wherein the DC bias regulator produces DC bias voltages for each of the pair of transistors as a function of the reference current through the reference transistor; and wherein the DC bias regulator comprises: a voltage combiner circuit; wherein the DC bias regulator produces: a voltage related to the reference current, such voltage being coupled to a control electrode of a first one of the pair of transistors; wherein the combiner circuit has a pair of inputs coupled to: the voltage produced by the DC bias regulator and the voltage source, respectively, to produce a bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the voltage produced by the voltage regulator and the voltage source.

26. The amplifier recited in claim 25 wherein the combiner is a Millman passive averager.

27. The amplifier recited in claim 25 wherein the DC bias voltage produced at the control electrode of the second one of the pair of transistors is independent of variations on a current passing serially through both the first one of the pair of transistors and the second one of the pair of transistors.

28. The amplifier recited in claim 25 wherein the combiner includes a pair of resistors, and wherein a first one of the pair of resistors is connected between a first one of the pair of inputs and an output of the combiner and a second one of the pair of resistors is connected between a second one of the pair of inputs and the output of the combiner.

29. The amplifier recited in claim 28 wherein the pair of resistors have the same resistances.

30. The amplifier recited in claim 28 wherein the pair of resistors have the different resistances.

31. The amplifier recited in claim 28 wherein the pair of resistors have the variable resistance.

32. The amplifier recited in claim 25 wherein the DC bias regulator includes a voltage divider circuit and wherein the reference current passes through a voltage divider circuit.

33. The amplifier recited in claim 32 wherein the voltage divider includes a pair of serially connected resistors and wherein the reference current passes through the serially connected resistors, one of the resistors producing the voltage coupled to the control electrode of the first one of the pair of transistors and the other one of the resistors producing the voltage coupled to the combiner.

34. The amplifier recited in claim 28 wherein the DC bias regulator includes a voltage divider circuit and wherein the reference current passes through voltage divider circuit.

35. The amplifier recited in claim 34 wherein the voltage divider includes a pair of serially connected resistors and wherein the reference current passes through the serially connected resistors, the combination of the resistors producing the voltage coupled to the control electrode of the first one of the pair of transistors and the other one of the resistors producing the voltage coupled to the combiner.

36. The amplifier recited in claim 35 wherein the pair of resistors in the voltage divider have the same resistance.

37. The amplifier recited in claim 25 wherein the DC bias regulator comprises: a bias circuit; a voltage combiner circuit; wherein the bias circuit produces: a first output voltage related to the reference current and a second voltage, the second voltage being a predetermined fraction of the first output voltage, the second voltage being coupled to the control electrode of the second transistor; wherein the combiner circuit has a pair of inputs coupled to: the first output voltage produced by the voltage divider; and the first voltage source, respectively, to produce a DC bias voltage at the control electrode of the first transistor related to a combination of the first output voltage produced by the reference voltage and the voltage source.

38. The amplifier recited in claim 36 wherein the combiner circuit produces the DC bias voltage as a function of the sum of the output voltage produced by the reference voltage and the voltage source.

39. The amplifier recited in claim 38 wherein the combiner circuit produces the DC bias voltage as a function of the average of the output voltage produced by the reference voltage and the voltage source.

40. The amplifier recited in claim 38 wherein the current through the reference transistor is a saturation current for the reference transistor and current from the voltage supply to the reference potential is a saturation current for both the first transistor and the second transistor.

41. The amplifier recited in claim 5 wherein the combiner is a Millman passive averager.

42. The amplifier recited in claim 14 wherein the combiner is a Millman passive averager.

43. The amplifier recited in claim 18 wherein the combiner is a Millman passive averager.

Description

DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a schematic diagram of a Millman Passive Averager with two inputs according to the PRIOR ART;

[0032] FIG. 2 is a schematic diagram of a common-source FET amplifier with bias regulator according to the PRIOR ART;

[0033] FIG. 3 is a schematic diagram of a cascode amplifier according to the disclosure;

[0034] FIGS. 4A and 4B are computer simulation results of the cascode amplifier of FIG. 3 using circuit models of GaAs FETs to represent transistors; FIG. 3A showing percent change in DC drain current, I.sub.CASCODE as a function of change in pinch off voltage for: (A) an cascode amplifier without any DC bias regulator; (B) a cascode amplifier with regulator to control DC bias of the gate electrode of only the common source FET; (C) a cascode amplifier according to the disclosure; FIG. 4B shows Vds_cg/Vds_cs ratio as a function of change in pinch off voltage for: (A) an cascode amplifier without any DC bias regulator; (B) a cascode amplifier with regulator to control DC bias of the gate electrode of only the common source FET; and (C) a cascode amplifier according to the disclosure;

[0035] FIG. 5 is a schematic diagram of a cascode amplifier having a stabilization resistor coupled between the pair of cascode arranged transistors according to the disclosure;

[0036] FIG. 6 is a schematic diagram of a two-stage cascaded amplifier having a first cascode amplifier stage feeding a second common-source amplifier stage according to the disclosure.

[0037] FIG. 7A is a schematic of a Millman Passive Averager with two inputs and with variable resistors Rx and Ry.

[0038] FIG. 7B is a schematic of a Millman Passive Averager with two inputs and with voltage-variable resistors implemented as transistors Qx and Qy.

[0039] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0040] Referring now to FIG. 3, an amplifier 10 is shown having: a pair of transistors, here PETS, CS FET and CO FET of equal total gate widths, Wg_cs=Wg_cg, arranged as a cascode amplifier 12, as shown, and a DC bias regulator 14. The pair of transistors CS FET and CO FET, of the cascode amplifier 10 is serially connected between a first voltage source, Vdd and ground potential, as shown. An input RF signal is fed to the gate of CS FET, as shown, for amplification by the amplifier 10 to produce an output RF signal at the drain of CG_FET, as indicated,

[0041] In order for the voltage Vds_cs between the source (S) and drain (D) electrodes of the CG FET to be equal to the voltage Vds_cg between the source (S) and drain (D) electrodes of the CS FET, Vd_cs needs to be equal to Vdd/2 (assuming that Vdd=Vd_cg, i.e., the RF choke L1 separating Vdd and Vd_cg has zero DC resistance). Note that in this commonly used notation, (A) Vds_cs=Vd_csVs_cs=Vd_cs since Vs_cs=0 and (B) Vds_cg=Vd_cgVs_cg=VddVd_cs.

[0042] In order for Vds_cs to be equal to Vds_cg, Vgs_cg needs to be equal to Vgs_cs because they share the same current I.sub.CASCODE and their sizes are equal Wg_cs=Wg_cg. It is noted that both the CG FET and the CS FET operate with a saturation current I.sub.CASCODE and the cascode arrangement is a current-sharing arrangement. Therefore, Vgs_cg =Vg_cgVs_cg=Vg_cg Vd_cs=Vg_cg Vdd/2; or Vg_cg Vdd/2+Vgs_cg. Since we want Vgs_cg to be equal to Vgs_cs, we want Vg_cg=Vdd/2 +Vgs_cs. Thus, Vg_cg must equal [Vdd+2 Vgs_cs]/2 in order for Vds_cs=Vds_cg.

[0043] It should be noted that Qref, CS FET and CG FET are all formed in near proximity on the same integrated circuit, so that both the semiconductor material properties and environmental conditions are the same for the three transistors. Thus, the reference transistor QREF, produces a reference current I.sub.REF, here for example, the saturation current, through the source electrode S and drain electrode D of the reference transistor Q.sub.REF, and through the serially connected resistors R1a and R1b. The DC bias regulator 14 produces bias voltages Vg_cs and Vg_cg for the gate electrodes of the CS FET and CG FET, respectively, as a function of the reference current I.sub.REF through the reference transistor Q.sub.REF and the serially connected resistors R1a and R1b.

[0044] More particularly, the DC bias regulator 14 includes a bias circuit 16 and a voltage combiner circuit 18, here a Millman averaging circuit, FIG. 1. The bias circuit 16 includes a reference transistor Q.sub.REF, connected as a current source 15, serially connected between a voltage Vss and ground through a voltage divider 17, having serially connected resistors R1a and R1b, as shown. The voltage divider 17 of the bias circuit 16 produces: a first output voltage V1b related to the reference current I.sub.REF and the sum of resistors R1a and R2b V1b=I.sub.REF (R1a+R1b) and a second voltage, Vg_cs=I.sub.REFR1a/(R1a+R1b). Thus, Vg_cs is a predetermined fraction R1a/(R1a+R1b) of the output voltage V1b, the second voltage Vg_cs being coupled to the control electrode, here the gate electrode G of a first one of the pair of transistors, here CS FET.

[0045] The combiner circuit 18 has a pair of inputs 20, 22 coupled to: the first output voltage Vg_cs produced by the voltage divider 17 and the first voltage source, Vdd, respectively, to produce a DC bias voltage Vg_cg at the control electrode, here the gate electrode G of the second transistor CO FET related to a combination of the first output voltage Vg_cs and the first voltage source Vdd. More particularly, here R1a=R1b so that Vg_cs =V1b/2 and therefore with Rx and Ry of the combiner 18 being equal and being much greater than R1a, so that the combiner circuit 18 produces the DC bias voltage Vg_cg as a function of the sum of the voltage V1b and the first voltage source Vdd; here [V1b+Vdd]/2. Since, V1b 2 Vg_cs, Vg_cg =[2 Vg_cs +Vdd]/2 and therefore as described above, the voltage Vds_cg across the source and drain electrode S, D of the CG FET will be equal to the voltage Vds_cs across the source drain electrode S, D of the CS FET. It should be noted that in this arrangement, Vg cg does not have direct dependence on I.sub.CASCODE, only through Vg_cs. It should also be noted that Vg_cg traces Vg_cs, i.e. if the pinch-off voltage for CS, CG and Qref FETs changes due to manufacturing and/or temperature, both Vg_cs and Vg_cg get adjusted automatically by the bias regulator arrangement to keep the I.sub.CASCODE constant and Vds_cs =Vds_cg.

[0046] Finally it is noted that because R1a=R1b (as noted above, fabrication of resistors or equal resistances is very precise), the voltage divider 17 produces a voltage Vg_cs which is precisely one half of the output voltage fed to input 20 of the combiner 18 (that is, from the equations described above, Vdd will split between Vds_cs and Vds_cg independent of the actual voltage Vdd). Therefore, the voltage Vds_cg across the source and drain electrodes S, D of the CG FET will be equal to the voltage Vds_cs across the source drain electrodes S, D of the CS FET independent of the actual voltage of Vdd resulting in a circuit independent of variations in Vdd and is, as described in detail below, independent of variations in pinch off voltage, Vp:

[0047] Referring to FIG. 3, according to the Millman Theorem described above:

[00003]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{\frac{V_{\mathrm{dd}}}{R_y}+\frac{V_{1.Math.b}}{R_x}}{\frac{1}{R_y}+\frac{1}{R_x}}& \left(1\right)\end{array}$

[0048] If we select R.sub.y=R.sub.x, and assume that L2 has zero DC resistance, then:

[00004]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{V_{\mathrm{dd}}+V_{1.Math.b}}{2}& \left(2\right)\end{array}$

[0049] We need to ensure that (it is assumed that L1 has zero DC resistance):

[00005]$\begin{array}{cc}{V}_{\mathrm{ds}.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{\mathrm{ds}.Math..Math.\_.Math..Math.\mathrm{cs}}{V}_{d.Math..Math.\_.Math..Math.\mathrm{cs}}=\frac{V_{\mathrm{dd}}}{2}& \left(3\right)\end{array}$

[0050] For this to be true, the following must be enforced (assuming that L3 has zero DC resistance, the voltage drop across Rh is negligible, and CS FET and CG FET have the same total gate width Wg_cs=Wg_cg)

[00006]$\begin{array}{cc}{V}_{\mathrm{gs}.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{\mathrm{gs}.Math..Math.\_.Math..Math.\mathrm{cs}}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}-V_{s.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{\mathrm{gs}.Math..Math.\_.Math..Math.\mathrm{cs}}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{V_{\mathrm{dd}}}{2}+V_{\mathrm{gs}.Math..Math.\_.Math..Math.\mathrm{cs}}& \left(4\right)\\ .Math.V_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{V_{\mathrm{dd}}+2.Math.V_{g.Math..Math.\_.Math..Math.\mathrm{cs}}}{2}& \left(5\right)\end{array}$

[0051] If R1a=R1b (assuming that Rx>>R1a), the equal voltage division Vds_cg=Vds_cs in (3) is enforced from (2) and (5) by ensuring that V1b=2 Vg_cs.

[0052] Thus, in summary, and referring to FIG. 3:

[0053] For the voltage across the source-drain of the CS FET (Vds_cs) to be equal to the voltage across the source-drain of the CG FET (Vds_cg): [0054] Vg_cg should be equal to (Vdd+2 Vg_cs)/2; [0055] R1a=R1b so that the voltage V1b at the first input 20 of the Millman Passive Averager 18 is equal to 2 Vg_cs; [0056] Rx=Ry>>R1a so that: [0057] the voltage Vg_cg at the output 21 of the Millman Passive Averager is equal to the average of the voltages at the Millman Passive Averager inputs 20 and 22 thus satisfying the condition of Vg_cg=(Vdd+2 Vg_cs)/2 to enforce Vds_cs=Vds_cg; [0058] the current through resistor Rx of the Millman Passive Averager is much smaller than the reference current Iref through the reference transistor Qref.

[0059] To complete the circuit 10, the RF input signal is fed to the gate electrode G of the CS PET through a conventional DC blocking capacitor C5, drain of the CG PET is coupled to the RF output through a DC blocking capacitor C2. C1, C3 and C4 DC are bypass capacitors that along with RP blocking inductors L1-L3 allow for DC connection between the bias regulator and Vdd on one side and transistors CS_FET and CG_FET on the other while preventing an RF connection. Resistor Rh provides additional low-frequency (where L3 and C4 are no longer effective in blocking the AC signal) isolation between the bias regulator and the gate electrode G of the CS FET.

[0060] Referring now to FIGS. 4A and 4B, FIGS. 4A and 4B show computer simulation results of the cascode amplifier of FIG. 3; FIG. 4A showing percent change in DC drain current, I.sub.CASCODE, as a function of change in pinch off voltage for: (A) an cascode amplifier without any DC bias regulator; (B) a cascode amplifier with regulator to control DC bias of the gate electrode of only the common-source PET; (C) a cascode amplifier according to the disclosure and FIG. 3B shows Vds_cg/Vds_cs ratio as a function of change in pinch off voltage for (A) an cascode amplifier without any DC bias regulator; (B) a cascode amplifier with regulator to control DC bias of the gate electrode of only the common-source PET; (C) cascode amplifier according to the disclosure. The curves demonstrate that the Cascode DC Bias Regulator demonstrates the required functionality:

[0061] 1. reduced sensitivity to pinch-off voltage, Vp, variation;

[0062] 2. enforced equality of drain-source voltages across the FET CS and FET CG

[0063] Referring now to FIG. 5, a cascode amplifier 10 is shown. Here, a stabilization resistor Rn is connected between the source of the CO FET and the drain of the CS FET, as shown. The function of the resistor Rn is to improve circuit's stability at the expense of lowering its gain. Because of the inclusion of the resistor Rn, to ensure Vds_cs=Vds_cg, the resistance values for resistors Rx and Ry now need to satisfy the ratio shown and derived in equation (16).

[0064] Referring to FIG. 5, according to the Millman Theorem (assuming that L2 has zero DC resistance):

[00007]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{\frac{V_{\mathrm{dd}}}{R_y}+\frac{V_{b.Math..Math.c}}{R_x}}{\frac{1}{R_y}+\frac{1}{R_x}}& \left(6\right)\end{array}$

[0065] If R.sub.y=aR.sub.x and Rx>>R1, then:

[00008]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{V_{\mathrm{dd}}+{\mathrm{aV}}_{.Math.\mathrm{bc}}}{a+1}& \left(7\right)\end{array}$

[0066] We need to ensure that:

V.sub.ds.sub._.sub.cg=V.sub.ds.sub._.sub.csV.sub.d.sub.cgV.sub.s.sub._.sub.cg=V.sub.d.sub._.sub.cs(8)

[0067] For this to be true, the following must be enforced (assuming that Vg_cs1=Vbc, in other words, L3 has zero DC resistance and the voltage drop across Rh is negligible, and also making CS FET and CG FET have the same total gate width Wg_cs=Wg_cg)

V.sub.gs.sub._.sub.cg=V.sub.gs.sub._.sub.csV.sub.gs.sub._.sub.cg=V.sub.bcV.sub.g.sub._.sub.cg=V.sub.s.sub._.sub.cg+V.sub.bc(9)

[0068] Now, we need to express V.sub.s.sub._.sub.cg in terms of R.sub.k, R.sub.l, R, V.sub.dd and I.sub.cascode (assuming L1 has zero DC resistance)

V.sub.d.sub._.sub.cg=V.sub.dd(10)

V.sub.ds.sub._.sub.cg+V.sub.d.sub._.sub.cs=V.sub.ddI.sub.cascodeR.sub.n(11)

Since V.sub.ds.sub._.sub.cg=V.sub.d.sub._.sub.cs

[00009]$\begin{array}{cc}{V}_{d.Math..Math.\_.Math..Math.\mathrm{cs}}=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}}.Math.R_n}{2}& \left(12\right)\\ V_{s.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{d.Math..Math.\_.Math..Math.\mathrm{cs}}+I_{\mathrm{cascode}}.Math.R_n=\frac{V_{\mathrm{dd}}+I_{\mathrm{cascode}}.Math.R_n}{2}& \left(13\right)\end{array}$

[0069] From (9) and (13)

[00010]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{s.Math..Math.\_.Math..Math.\mathrm{cg}}+V_{\mathrm{bc}}=\frac{V_{\mathrm{dd}}+I_{\mathrm{cascode}}.Math.R_n}{2}+V_{\mathrm{bc}}& \left(14\right)\end{array}$

[0070] Combining (7) and (14)

[00011]$\begin{array}{cc}\frac{V_{\mathrm{dd}}+{\mathrm{aV}}_{\mathrm{bc}}}{a+1}=\frac{V_{\mathrm{dd}}+I_{\mathrm{cascode}}.Math.R_n}{2}+V_{\mathrm{bc}}& \left(15\right)\end{array}$

[0071] Using (15), the ratio a=Ry/Rx, which enforces Vds_cs=Vds_cg, can be derived as:

[00012]$\begin{array}{cc}a=\frac{R_y}{R_x}=\frac{V_{\mathrm{dd}}-2.Math.V_{\mathrm{bc}}-I_{\mathrm{cascode}}.Math.R_n}{V_{\mathrm{dd}}+I_{\mathrm{cascode}}.Math.R_n}& \left(16\right)\end{array}$

[0072] Referring now to FIG. 6, a two-stage cascade amplifier 10 having a first cascode amplifier stage 12 feeding a second. common-source amplifier stage 13 is shown. Further, it is noted that here, because of the cascade of the two amplifiers 14 and 13, input, interstage, and output matching networks 30, 32, and 34, respectively, are included as shown. Here, in order to improve stability of the amplifier 10, the cascode amplifier 12 also includes the resistor Rn connected serially between the source of CG FET1 and the drain of CS FET2, as shown. Also included is an isolation circuit 36, here resistors Rk and RL, serially connected between Vdd and the drain of CG FET1, as shown to improve low frequency (i.e., at frequencies much lower than the frequency of the RF input signal) isolation between the cascode amplifier stage 12 and the common-source amplifier stage 13; the impedance matching between the cascode amplifier stage 12 and the common-source amplifier stage 13 being provided by the interstage matching network 32. It is noted that also included are by-pass capacitors C1, C3, C4, C6 and C7 and RF chokes L2, L6 and L7, arranged as shown.

[0073] It is also noted that the bias circuit 16 includes only one resistor R1 serially connected to the current source 15. Here, the current source produces a reference current IREF, as indicated. The reference current I.sub.REF passes through R1 to produce an output voltage Vbc from the DC bias circuit 16, as indicated, The output voltage Vbc is fed to:

[0074] (A) the gate of CS FET1 to provide a DC bias voltage Vg_cs1 through RF choke L3 and resistor Rh, here used to enhance low frequency isolation between the bias regulator 14 and the transistor CS FET1;

[0075] (B) the gate of CS FET2 of the common-source stage 13 to provide a DC bias voltage Vg_cs2 through low-frequency isolating resistor Re and RF choke L7; and,

[0076] (C) the input 20 of the voltage combiner circuit 18, as shown.

[0077] The second input 22 of the combiner is fed a voltage at the junction between resistors Rk and RL, as shown. Thus, the voltage at input 22 is a fraction of the voltage Vdd, as to be described.

[0078] The values Rx and Ry for the resistors in the combiner 18 are calculated based on is chosen Rk, RL, and Rn values to enforce equal drain-source voltage division for the CS and CG FETs within the cascode amplifier 12; more particularly that Vds_cs of CS FET 1 (V.sub.ds.sub._.sub.CS FET1) be equal to Vds_cg of CG FET1 V.sub.ds.sub._.sub.CG FET1. More particularly, to ensure that V.sub.ds.sub._.sub.CS FET1=V.sub.ds.sub._.sub.CG FET1, the relation (27), shown and derived below, must be satisfied:

[0079] Referring to FIG. 6, according to the Millman Theorem (assuming that L2 has zero DC resistance)

[00013]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}.Math.R_k}{R_y}+\frac{V_{\mathrm{bc}}}{R_x}}{\frac{1}{R_y}+\frac{1}{R_x}}& \left(17\right)\end{array}$

If R.sub.y=aR.sub.x and Rx>>R1, then:

[00014]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}.Math.R_k+{\mathrm{aV}}_{\mathrm{bc}}}{a+1}& \left(18\right)\end{array}$

We need to ensure that:

V.sub.ds.sub._.sub.cg1=V.sub.ds.sub._.sub.cs1V.sub.d.sub._.sub.cg1V.sub.s.sub._.sub.cg1=V.sub.d.sub._.sub.cs1(19)

[0080] For this to be true, the following must be enforced (assuming that Vg_cs1=Vbc, in other words, L3 has zero DC resistance and the voltage drop across Rh is negligible, and also making CS FET and CG FET have the same total gate width Wg_cs=Wg_cg)

V.sub.gs.sub._.sub.cg=V.sub.gs.sub._.sub.csV.sub.gs.sub._.sub.cg=V.sub.bcV.sub.g.sub._.sub.cg=V.sub.s.sub._.sub.cs1+V.sub.bc(20)

[0081] Now, we need to express V.sub.g.sub._.sub.cg1 in terms of R.sub.k, R.sub.l, R.sub.n, V.sub.dd and I.sub.cascode. Assuming L1 has zero DC resistance

V.sub.ds.sub.cg1+V.sub.d.sub.cs1=V.sub.d.sub.cg1I.sub.cascode1R.sub.n(21)

V.sub.ds.sub._.sub.cg1=V.sub.ddI.sub.cascode1R.sub.k+R.sub.l)(22)

Since V.sub.ds.sub._.sub.cg1=V.sub.d.sub._.sub.cs1

[00015]$\begin{array}{cc}{V}_{d.Math..Math.\_.Math..Math.\mathrm{cs}.Math..Math.1}=\frac{V_{d.Math..Math.\_.Math..Math.\mathrm{cg}.Math..Math.1}-I_{\mathrm{cascode}.Math..Math.1}.Math.R_n}{2}=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}\left(R_k+R_l+R_n\right)}{2}& \left(23\right)\\ V_{s.Math..Math.\_.Math..Math.\mathrm{cg}.Math..Math.1}=V_{d.Math..Math.\_.Math..Math.\mathrm{cs}.Math..Math.1}+I_{\mathrm{cascode}.Math..Math.1}.Math.R_n=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}\left(R_k+R_l-R_n\right)}{2}& \left(24\right)\end{array}$

From (20) and (24)

[0082] [00016]$\begin{array}{cc}{V}_{g.Math..Math.\_.Math..Math.\mathrm{cg}}=V_{s.Math..Math.\_.Math..Math.\mathrm{cg}.Math..Math.1}+V_{\mathrm{bc}}=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}\left(R_k+R_l-R_n\right)}{2}+V_{\mathrm{bc}}& \left(25\right)\end{array}$

Combining (18) and (25)

[0083] [00017]$\begin{array}{cc}\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}.Math.R_k+{\mathrm{aV}}_{\mathrm{bc}}}{a+1}=\frac{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}\left(R_k+R_l-R_n\right)}{2}+V_{\mathrm{bc}}& \left(26\right)\end{array}$

Using (26), the ratio a=Ry/Rx, which enforces Vds_cs1=Vds_cg1, can he derived as:

[00018]$\begin{array}{cc}a=\frac{R_y}{R_x}=\frac{V_{\mathrm{dd}}-2.Math.V_{b.Math..Math.c}+I_{\mathrm{cascode}.Math..Math.1}\left(-R_k+R_l-R_n\right)}{V_{\mathrm{dd}}-I_{\mathrm{cascode}.Math..Math.1}\left(R_k+R_l-R_n\right)}& \left(27\right)\end{array}$

[0084] Alternatively, Ry and Rx can be set to obtain an arbitrary relationship between V.sub.ds.sub._.sub.CS1 and V.sub.ds.sub._.sub.CG1.

[0085] Rk and RL are typically set to small resistance values to have small associated DC voltage drops across them At the same time their non-zero resistances help to reduce quality factors of potential resonances associated with electrical interconnections and the reactive circuit components L1, L6, C1 and C6. In turn, lower resonances' quality factors improve circuit's stability.

[0086] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, as noted above, the transistors may be BJTs. Further, the resistors Rx and Ry and R1a and R1b may be selected to produce a ratio of Vds_cs to Vds_cg other than 1. Note, that if R1a and R1b are kept constant, changing Rx and Ry can produce different Vds_cs/Vds_cg ratios without changing the current flowing through the cascade between Vdd and ground. Further, the resistors Rx and Ry may be implemented as variable resistors, shown in FIG. 7A to dynamically change the Vds_cs/Vds_cg ratio. Further, the resistors Rx and Ry may be implemented as voltage-variable resistors in the form of field-effect transistors (FED) Qx and Qy, shown in FIG. 7B, where two external voltages Vx and Vy applied to the control (gate) electrodes of such FETs) set the drain-source resistances of the FETs Qx and Qy respectively, Thus, it should be noted that while one DC bias circuit 16 has been used to produce the reference current as described, other bias circuits may be used. Accordingly, other embodiments are within the scope of the following claims.