HIGH-FREQUENCY POWER SUPPLY DEVICE AND OUTPUT CONTROL METHOD THEREFOR

Abstract

A high-frequency power supply device, which outputs high-frequency pulses to a target device on the basis of a synchronous pulse and a clock pulse, and the output control method therefor are such that a period reference signal is generated from output timing information pertaining to the synchronous pulse, an output level signal is generated from output level information, an output stop time is timed on the basis of the period reference signal and an output stop signal is generated, and, when the period reference signal, the output level signal, and the clock pulse are received and a high-frequency pulse is formed on the basis of these signals, transmission of the output level signal is stopped while the output stop signal is being received.

Claims

1. A high-frequency power supply device for outputting a high-frequency pulse to a target device based on a synchronous pulse and a clock pulse, comprising: a synchronous pulse generation mechanism that generates a synchronous pulse containing output level information and output timing information of the high-frequency pulse; an output level setting mechanism that generates an output level signal for setting an output level of the high-frequency pulse based on the output level information; and an oscillation mechanism that receives a period reference signal of the synchronous pulse and the output level signal to oscillate the high-frequency pulse, wherein the synchronous pulse generation mechanism comprises a synchronous pulse formation circuit that forms the synchronous pulse, a period reference signal generation unit that generates a period reference signal at a period reference time of the synchronous pulse, and a clocking mechanism that clocks an output stop time based on the period reference signal and sends an output stop signal to the output level setting mechanism, the output level setting mechanism comprises a level determination unit that determines an output level set in the high-frequency pulse in response to the output level signal, and a level setting signal generation unit that generates a level setting signal based on a result of the determination made by the level determination unit, the oscillation mechanism comprises a clock pulse generator that generates the clock pulse, and an oscillation amplifier that receives the period reference signal, the level setting signal and the clock pulse to generate the high-frequency pulse based on these signals, wherein the output level setting mechanism stops sending out the level setting signal while the output stop signal is being received.

2. The high-frequency power supply device according to claim 1, wherein the level setting signal includes a first level setting signal for defining a first output level of the high-frequency pulse and a second level setting signal for defining a second output level of the high-frequency pulse, and the level setting signal generation unit comprises a first level setting signal generator that generates the first level setting signal, and a second level setting signal generator that generates the second level setting signal.

3. The high-frequency power supply device according to claim 1, wherein the output level setting mechanism further comprises a level-zero signal generator that generates a level-zero signal for making an amplitude value of the high-frequency pulse to be zero, wherein the level-zero signal generator sends out the level-zero signal while the output stop signal is being received, the oscillation mechanism setting an output of the high-frequency pulse to zero while the level-zero signal is being received.

4. An output control method for a high-frequency power supply device that outputs a high-frequency pulse to a target device based on a synchronous pulse and a clock pulse, comprising generating an output level signal for setting an output level of the high-frequency pulse from output level information contained in a waveform of the synchronous pulse, and generating a period reference signal from output timing information, generating a level setting signal based on the output level signal, and clocking an output stop time based on the period reference signal as well as generating an output stop signal, receiving the period reference signal, the level setting signal and the clock pulse, and when forming the high-frequency pulse based on these signals, stopping sending the level setting signal while the output stop signal is being received.

5. The output control method for the high-frequency power supply device according to claim 4, wherein the level setting signal includes a first level setting signal for defining a first output level of the high-frequency pulse, and a second level setting signal for defining a second output level of the high-frequency pulse.

6. The output control method for the high-frequency power supply device according to claim 4, further generates a level-zero signal for making an amplitude value of the high-frequency pulse to be zero while the output stop signal is being received, and setting an output of the high-frequency pulse to zero while the level-zero signal is being received.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a block diagram showing a schematic configuration of a high-frequency power supply device according to Embodiment 1 which is a representative example of the invention;

[0014] FIG. 2 is a block diagram showing an example of a specific configuration of a synchronous pulse generation mechanism according to Embodiment 1;

[0015] FIG. 3 is a block diagram showing an example of a specific configuration of an output level setting mechanism according to Embodiment 1;

[0016] FIG. 4 is a block diagram showing an example of a specific configuration of an oscillation mechanism according to Embodiment 1;

[0017] FIGS. 5 is a graph showing an example of an output waveform obtained by an output control method for the high-frequency power supply device according to Embodiment 1;

[0018] FIGS. 6 is a graph showing a variation of the output waveform obtained by the output control method for the high-frequency power supply device according to Embodiment 1;

[0019] FIG. 7 is a block diagram showing a schematic configuration of a high-frequency power supply device according to Embodiment 2;

[0020] FIG. 8 is a block diagram showing an example of a specific configuration of an output level setting mechanism according to Embodiment 2;

[0021] FIG. 9 is a block diagram showing an example of a specific configuration of an oscillation mechanism according to Embodiment 2; and

[0022] FIGS. 10 a graph showing an example of an output waveform obtained by an output control method for the high-frequency power supply device according to Embodiment 2.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] A description will now be made about representative illustrative embodiments of a high-frequency power supply device and an output control method therefor according to the present invention by referring to FIGS. 1 to 10.

Embodiment 1

[0024] FIG. 1 is a block diagram that shows a schematic configuration of a high-frequency power supply device according to Embodiment 1 which is a representative example of the invention. As shown in FIG. 1, a high-frequency power supply device 100 according to Embodiment 1 includes, by way of example, a synchronous pulse generation mechanism 110 that generates a synchronous pulse P1 that includes output level information and output timing information of a high-frequency pulse PO to be output, an output level setting mechanism 120 that generates output level signals S.sub.L1, S.sub.L2 for setting output levels of the high-frequency pulse PO based on the output level information of the synchronous pulse P1, and an oscillation mechanism 130 that receives a period reference signal S.sub.s based on the output timing information of the synchronous pulse P1 and the above-mentioned output level signals S.sub.L1, S.sub.L2 to thereby oscillate the high-frequency pulse PO. The high-frequency pulse PO output from the high-frequency power supply device 100 is fed to a target device 10, such as plasma or laser generation device, induction heating device, ultrasonic oscillation device or others.

[0025] FIG. 2 is a block diagram showing an example of a specific configuration of the synchronous pulse generation mechanism according to Embodiment 1. As shown in FIG. 2, the synchronous pulse generation mechanism 110 of Embodiment 1 includes a synchronous pulse formation circuit 112 that forms the above-mentioned synchronous pulse P1, a period reference signal generation unit 114 that generates the period reference signal S.sub.s at a period reference time in the synchronous pulse P1, and a clocking mechanism 116 that clocks an output stop time based on the period reference signal S.sub.s to send out an output stop signal S.sub.T to the output level setting mechanism 120. In addition to that, the synchronous pulse P1 output from the synchronous pulse formation circuit 112 is also fed to the output level setting mechanism 120, about which will be described later.

[0026] The synchronous pulse formation circuit 112 includes output level information (amplitude value) and output timing information (amplitude changing timing), by way of example, and outputs an approximately rectangular periodic pulse waveform that defines two output levels L1, L2 on a vertical axis with respect to an elapsed time on a horizontal axis. Although FIG. 2 illustrates the case where the output levels are the high level L1 and the low level L2, the pulse waveform may have three or more output levels as long as the waveform is an approximately rectangular periodic wave.

[0027] In addition to that, the synchronous pulse P1 is not limited to the rectangular wave, and may include any waveform that contains the output level information and the output timing information, such as sine wave or extremely-short pulse. Furthermore, the synchronous pulse P1 may consist of a plurality of signal waveforms. For example, there is a technique for performing AND operation on a plurality of signal waveforms to obtain an output level and output timing.

[0028] The period reference signal generation unit 114 uses the synchronous pulse P1 received from the synchronous pulse formation circuit 112 to identify the output timing information which is a time reference of a period as one of the features of this synchronous pulse P1, and outputs the period reference signal S.sub.s at the identified timing. In this context, the time reference of the period is a time of switching from the low level L2 to the high level L1 (rising time), by way of example. Moreover, the number of the period reference signals S.sub.s is not limited to one in one period, and for example, a time of switching from the high level L1 to the low level L2 (falling time) may be employed, in addition to the above-mentioned rising time from the low level L2 to the high level L1.

[0029] The clocking mechanism 116 is configured, by way of example, to receive the period reference signal S.sub.s from the period reference signal generation unit 114, and then continue to send out an output stop signal S.sub.T to the output level setting mechanism 120, which will be described later, from the time of receiving the period reference signal until after a lapse of a predetermined output stop time. In this case, the clocking mechanism 116 is configured such that any timing can be selected for the predetermined output stop time with respect to a clock period of a clock pulse generator 132, which will be described later (see FIG. 4). This enables to arbitrarily select timing when the sending of the output stop signal S.sub.T is stopped.

[0030] FIG. 3 is a block diagram showing an example of a specific configuration of the output level setting mechanism according to Embodiment 1. As shown in FIG. 3, the output level setting mechanism 120 of Embodiment 1 includes a level determination unit 122 for issuing a first level setting command S.sub.1 or second level setting command S.sub.2 in accordance with an amplitude value (output level information) of the synchronous pulse P1, and a level setting signal generation unit 124 for generating level setting signals (first level setting signal S.sub.L1 and second level setting signal S.sub.L2) in response to the output stop signal S.sub.T as well as the first level setting command S.sub.1 and the second level setting command S.sub.2. Furthermore, the level setting signal generation unit 124 includes a first level setting signal generator 126 for generating the first level setting signal S.sub.L1 while the first level setting command S.sub.1 is being received, and a second level setting signal generator 128 for generating the second level setting signal S.sub.L2 while the second level setting command S.sub.2 is being received.

[0031] The level determination unit 122 is configured to receive the synchronous pulse P1 from the synchronous pulse formation circuit 112, and send out a predetermined setting command in real time according to the output level of the received synchronous pulse P1. For example, the level determination unit 122 in Embodiment 1 sends out the first level setting command S.sub.1 while the synchronous pulse P1 is at the high level L1, and when the level of the synchronous pulse P1 is changed to the low level L2, sends out the second level setting command S.sub.2.

[0032] The first level setting signal generator 126 generates the first level setting signal S.sub.L1 in response to the first level setting command S.sub.1 received from the level determination unit 122. Correspondingly, the second level setting signal generator 128 generates the second level setting signal S.sub.L2 in response to the second level setting command S.sub.2 received from the level determination unit 122. In this connection, the level setting signal generation unit 124 is configured not to output the first level setting signal S.sub.L1 generated by the first level setting signal generator 126 or the second level setting signal S.sub.L2 generated by the second level setting signal generator 128 to the oscillation mechanism 130 while receiving the output stop signal S.sub.T from the synchronous pulse generation mechanism 110.

[0033] FIG. 4 is a block diagram showing an example of a specific configuration of the oscillation mechanism according to Embodiment 1. As shown in FIG. 4, the oscillation mechanism 130 includes a clock pulse generator 132 for generating a clock pulse P2 in a predetermined high frequency range, and an oscillation amplifier 134 for receiving the period reference signal S.sub.s from the synchronous pulse generation mechanism 110, the first level setting signal S.sub.L1 and the second level setting signal S.sub.L2 from the output level setting mechanism 120, and the above-mentioned clock pulse P2, so as to form a high-frequency pulse PO based on these signals.

[0034] The clock pulse generator 132 is for generating the clock pulse P2 at high frequency (several hundreds of kHz to several tens of MHz) according to the output of the high-frequency pulse PO, e.g., generating the clock pulse P2 of 13.56 MHz. Moreover, in addition to generating the above-described clock pulse P2 at a certain high frequency at regular intervals, the clock pulse generator 132 has another function of resetting timing of the generation of the clock pulse P2 (set to a desired phase) at a desired time t.sub.rst (see FIGS. 5 or 6). Furthermore, the oscillation amplifier 134 determines oscillation timing for the high-frequency pulse PO based on the period reference signal S.sub.s, and amplifies the amplitude value of the clock pulse P2 based on the first level setting signal S.sub.L1 and the second level setting signal S.sub.L2 to generate the high-frequency pulse PO.

[0035] FIGS. 5 is a graph showing an example of an output waveform that can be obtained by an output control method for the high-frequency power supply device according to Embodiment 1. In the output control method for the high-frequency power supply device according to Embodiment 1, as shown in FIG. 5(a)as an example, the synchronous pulse P1 formed by the synchronous pulse formation circuit 112 in the synchronous pulse generation mechanism 110 is formed as a periodic pulse signal that will be at the high level L1 at an interval of a time T.sub.L1 and at the low level L2 at an interval of a time T.sub.L2. Then, as described above, a rising time to the high level L1, which is a time reference of one pulse period, is derived from the concerned synchronous pulse P1, and the period reference signal generation unit 114 sends out the period reference signal S.sub.s at each rising time, by way of example.

[0036] The synchronous pulse P1 is also fed to the output level setting mechanism 120, and the level determination unit 122 in the output level setting mechanism 120 sets an output level for each time, so that the first level setting signal generator 126 or the second level setting signal generator 128 sends out the first level setting signal S.sub.L1 or the second level setting signal S.sub.L2 to the oscillation mechanism 130. That is to say, by referring to FIG. 5(a), the first level setting signal S.sub.L1 is sent out at the interval of the time T.sub.L1 and the second level setting signal S.sub.L2 is sent out at the interval of the time T.sub.L2.

[0037] Then, the oscillation amplifier 134 in the oscillation mechanism 130 amplifies an amplitude value of the clock pulse P2 in accordance with the received first level setting signal S.sub.L1 or second level setting signal S.sub.L2. More specifically, when the first level setting signals S.sub.L1 are received repeatedly, consecutive pulses having average height of the clock pulse P2 at the high level L1 are output as shown in FIG. 5(b). When the second level setting signals S.sub.L2 are received repeatedly, consecutive pulses having average height of the clock pulse P2 at the low level L2 are output as shown in FIG. 5(c).

[0038] As shown in FIG. 5(d), when an output stop signal S.sub.T that will be an output stop time T.sub.st is sent out from the clocking mechanism 116, the clock pulse P2 formed by the clock pulse generator 132 is reset at an arbitrary time t.sub.rst during the output stop time T.sub.st (the arbitrary time is defined as “rest time t.sub.rst”). Then, when this operation is performed continuously over time from the generation of the synchronous pulse P1, the outputting of the high-frequency pulse PO is started at a time of receiving the period reference signal S.sub.s by the oscillation mechanism 130, and thereby continuous pulses at the high level L1 are output at the interval of time T.sub.L1, as shown in FIG. 5(e). Correspondingly, continuous pulses at the low level L2 are output at the interval of the time T.sub.L2.

[0039] As described above, since the output level setting mechanism 120 is configured not to send out the first level setting signal S.sub.L1 while the output stop signal S.sub.T is being received, the continuous pulses at the high level L1 are not output from the start of the interval of the time T.sub.L1 until after a lapse of the output stop time T.sub.st. In this case, the timing of the reset time t.sub.rst is defined in accordance with a phase 0.sub.st of the high-frequency pulse PO that is firstly output after the expiration of the output stop time T.sub.st. More specifically, a phase of the clock pulse P2 is reset at the reset time t.sub.rst, so that the phase of the high-frequency pulse PO after the lapse of the output stop time T.sub.st will be the same phase at all times.

[0040] FIGS. 6 is a graph showing a variation of an output waveform obtained by the output control method for the high-frequency power supply device according to Embodiment 1. As shown in FIG. 6(a), in the output control method for the high-frequency power supply device according to the variation shown in FIGS. 6, for instance, a rising time to the high level L1, which is a time reference of one pulse period, is firstly derived from a synchronous pulse P1 formed by the synchronous pulse formation circuit 112 in the synchronous pulse generation mechanism 110, and the period reference signal generation unit 114 sends out a period reference signal S.sub.s at each rising time, as with the case shown in FIGS. 5. Furthermore, the output level setting mechanism 120 sends out a first level setting signal S.sub.L1 at an interval of a time T.sub.L1 and a second level setting signal S.sub.L2 at an interval of a time T.sub.L2 to the oscillation mechanism 130.

[0041] Secondly, as with the case of FIGS. 5, the oscillation amplifier 134 in the oscillation mechanism 130 amplifies an amplitude value of a clock pulse P2 in accordance with the received first level setting signal S.sub.L1 or second level setting signal S.sub.L2. Then, consecutive pulses having average height of the clock pulse P2 at the high level L1 as shown in FIG. 6(b)and consecutive pulses having average height of a clock pulse P2 at a low level L2 as shown in FIG. 6(c)are output.

[0042] As shown in FIG. 6(d), when an output stop signal S.sub.T that will be an output stop time T.sub.st is sent out from the clocking mechanism 116, the clock pulse P2 formed by the clock pulse generator 132 is reset at an arbitrary time t.sub.rst during the output stop time T.sub.st (the arbitrary time is defined as “reset time t.sub.rst”). Since the output level setting mechanism 120 is configured not to send out the first level setting signal S.sub.L1 while receiving the output stop signal S.sub.T, when this operation is performed continuously over time from the generation of the synchronous pulse P1, the outputting of a high-frequency pulse PO is started at a time of receiving the period reference signal S.sub.s by the oscillation mechanism 130, and thereby the continuous pulses at the high level L1 are output at the interval of time T.sub.L1, as shown in FIG. 6(e). Correspondingly, the continuous pulses at the low level L2 are output at the interval of the time T.sub.L2.

[0043] At this time, in the variation shown in FIGS. 6, timing of the reset time t.sub.rst is set such that a phase 0.sub.st of the high-frequency pulse PO, which is the first to be output after a lapse of the output stop time T.sub.st, is zero at all times. Thus, the reset of the phase of the clock pulse P2 at the reset time t.sub.rst enables to stably output the high-frequency pulse PO after the lapse of the output stop time T.sub.st such that the phase of the pulse PO is zero at all times, and yet at the same time, the outputting of the pulse PO delays by a waiting time a for matching output phases to be zero, as shown in FIG. 6(e).

[0044] With the above-described configuration, the high-frequency power supply device and the output control method therefor according to Embodiment 1 are adapted to receive the period reference signal S.sub.s based on the synchronous pulse P1, the first level setting signal S.sub.L1, the second level setting signal S.sub.L2 and the clock pulse P2, and when forming the high-frequency pulse PO based on these signals, set the output stop time T.sub.s clocked based on the period reference signal S.sub.s to be integral multiple of the clock period of the clock pulse P2, and thereby the output level setting mechanism stops sending out the first level setting signal S.sub.L1 or second level setting signal S.sub.L2 while the output stop signal S.sub.T is being received, so that the phases of the output high-frequency pulse can be matched on all occasions even if the synchronous pulse and the clock pulse are generated separately.

Embodiment 2

[0045] FIG. 7 is a block diagram showing a schematic configuration of a high-frequency power supply device according to Embodiment 2. In here, constituent elements of a high-frequency power supply device 200 according to Embodiment 2 that are the same as or similar to those of Embodiment 1 will be denoted by the same reference numerals in Embodiment 1, and the descriptions about them will not be repeated.

[0046] As shown in FIG. 7, the high-frequency power supply device 200 according to Embodiment 2 includes a synchronous pulse generation mechanism 110, an output level setting mechanism 120 and an oscillation mechanism 130. The high-frequency power supply device 200 of Embodiment 2 differs from the high-frequency power supply device 100 of Embodiment 1 in that the output level setting mechanism 120 sends out a level-zero signal S.sub.L0 to the oscillation mechanism 130.

[0047] FIG. 8 is a block diagram showing an example of a specific configuration of the output level setting mechanism according to Embodiment 2. As shown in FIG. 8, the output level setting mechanism 120 according to Embodiment 2 includes a level determination unit 122 that receives an output stop signal S.sub.T and a synchronous pulse P1, and issues a first level setting command S.sub.1 or second level setting command S.sub.2 in accordance with an amplitude value (output level) of the synchronous pulse P1, and a level setting signal generation unit 124 that generates level setting signals (level-zero signal S.sub.L0, first level setting signal S.sub.L1 and second level setting signal S.sub.L2) in response to the output stop signal S.sub.T as well as the first level setting command S.sub.1 and the second level setting command S.sub.2. In addition to that, the level setting signal generation unit 124 includes a level-zero signal generator 223 that generates the level-zero signal S.sub.L0 based on the output stop signal S.sub.T, and a first level setting signal generator 126 and a second level setting signal generator 128, which are similar to those of Embodiment 1.

[0048] The level determination unit 122 is configured, as with the case of Embodiment 1, to receive the synchronous pulse P1 from the synchronous pulse formation circuit 112, and according to the output level of the synchronous pulse P1, send out the first level setting command S.sub.1 while the synchronous pulse P1 is at a high level L1 and send out the second level setting command S.sub.2 when the level of the synchronous pulse P1 is changed to a low level L2.

[0049] The level-zero signal generator 223 is configured to be activated while the level setting signal generation unit 124 is receiving the output stop signal S.sub.T, and send out the level-zero signal S.sub.L0 that makes an amplitude value of a high-frequency pulse PO to be zero while the output stop signal S.sub.T is being received. On the other hand, the first level setting signal generator 126 and the second level setting signal generator 128 are configured, as with the case of Embodiment 1, to receive the first level setting command S.sub.1 or second level setting command S.sub.2 from the level determination unit 122 to thereby send out the first level setting signal S.sub.L1 or second level setting signal S.sub.L2 to the oscillation mechanism 130. In this way, the level setting signal generation unit 124 outputs only the level-zero signal S.sub.L0 to the oscillation mechanism 130 and does not output the first level setting signal S.sub.L1 or second level setting signal S.sub.L2 while receiving the output stop signal S.sub.T from the synchronous pulse generation mechanism 110.

[0050] FIG. 9 is a block diagram showing an example of a specific configuration of the oscillation mechanism according to Embodiment 2. As shown in FIG. 9, the oscillation mechanism 130 of Embodiment 2 includes a clock pulse generator 132, and an oscillation amplifier 234 that receives a period reference signal S.sub.s from the synchronous pulse generation mechanism 110, the level-zero signal S.sub.L0, the first level setting signal S.sub.L1 and the second level setting signal S.sub.L2 from the output level setting mechanism 120, and the clock pulse P2, so as to form a high-frequency pulse PO based on these signals.

[0051] The oscillation amplifier 234 according to Embodiment 2 is configured to determine oscillation timing for the high-frequency pulse PO based on the period reference signal S.sub.s, and define an amplitude value of the high-frequency pulse PO to be zero while receiving the level-zero signal S.sub.L0. On the other hand, when the first level setting signal S.sub.L1 and the second level setting signal S.sub.L2 are being received, the oscillation amplifier 234 amplifies the amplitude value of the clock pulse P2 to be at a high level L1 or low level L2 based on the received signals, so as to generate the high-frequency pulse PO.

[0052] FIGS. 10 is a graph showing an example of an output waveform obtained by the high-frequency power supply device and an output control method therefor according to Embodiment 2. In the output control method for the high-frequency power supply device according to Embodiment 2, the relationship between a synchronous pulse P1 and an output stop signal S.sub.T shown in FIGS. 10(a) to 10(d) and amplification of amplitude values with respect to a high level L1 and a low level L2 of a high-frequency pulse PO is the same as the relationship in Embodiment 1, and thus a description about it will not be repeated in here.

[0053] In the output control method for the high-frequency power supply device of Embodiment 2, the output level setting mechanism controls the outputting of the level-zero signal Z.sub.L0 for making the output level to be zero to the oscillation mechanism while the output stop signal S.sub.T is being output, thereby enabling to perform the control such that even if a dummy bounce pulse (damping pulse P.sub.D) is produced due to the switching of the output level at an end of an output interval (time T.sub.L2) of a last high-frequency pulse PO, an erroneous pulse output is prevented by making an amplitude value in an actual output to be zero, as shown in FIG. 9(e).

[0054] The above embodiments and the variations thereof are a few examples of the high-frequency power supply device and the output control method therefor of the present invention, and thus the present invention is not limited thereto. Furthermore, those skilled in the art can modify the present invention in various ways based on the gist of the invention, which modifications are not excluded from the scope of the present invention.

[0055] For example, Embodiments 1 and 2 illustrate that the output stop time T.sub.st is set at the early outputting stages at the high level L1. Alternatively, the output stop time T.sub.st can be set at the early outputting stages at the low level L2, or at the early outputting stages at the high level L1 and the low level L2. This makes it possible to control the wave number to be kept at a constant value for each period during outputting the high-frequency pulse PO.

[0056] The configurations illustrated in Embodiments 1 and 2 may not be separate constitutions of the invention, and may be applied as one high-frequency power supply device by combining their respective features.

REFERENCE SIGNS LIST

[0057] 10 Target Device [0058] 100, 200, 300 High-Frequency Power Supply Device [0059] 110 Synchronous Pulse Generation Mechanism [0060] 112 Synchronous Pulse Formation Circuit [0061] 114 Period Reference Signal Generation Unit [0062] 116 Clocking Mechanism [0063] 120 Output Level Setting Mechanism [0064] 122 Level Determination Unit [0065] 124 Level Setting Signal Generation Unit [0066] 126 First Level Setting Signal Generator [0067] 128 Second Level Setting Signal Generator [0068] 130 Oscillation Mechanism [0069] 132 Clock Pulse Generator [0070] 134, 234 Oscillation Amplifier [0071] 223 Level-Zero Signal Generator [0072] PO High-Frequency Pulse [0073] P1 Synchronous Pulse [0074] P2 Clock Pulse [0075] S.sub.s Period Reference Signal [0076] S.sub.T Output Stop Signal [0077] S.sub.L0 Level-Zero Signal [0078] S.sub.L1 First Level Setting Signal [0079] S.sub.L2 Second Level Setting Signal [0080] T.sub.st Output Stop Time