Low-Latency, Average Input Current Cancellation For Differential Input, Voltage-Sensing, Switched-Capacitor, Sigma-Delta Modulators

Abstract

An analog-to-digital converter circuit usable for measuring a voltage having a large common-mode voltage includes two input voltage nodes, a voltage sensing circuit (that includes a sigma-delta modulator) that senses a voltage between the nodes, a digital filter that outputs a multi-bit digital value, and an input current cancellation circuit. The input current cancellation circuit supplies/draws cancellation currents to/from the nodes to compensate for currents drawn from/supplied to the nodes by the voltage sensing circuit. The input current cancellation circuit includes a digitally-programmable digital processing circuit and a current canceling circuit. In one example, the digital processing circuit includes a sigma-delta modulator that transforms a single-bit digital signal output by the voltage sensing circuit into a single-bit digital signal that drives the current canceling circuit. The transfer function of the current compensation loop is programmable and adjustable by loading digital trim values into the circuit.

Claims

1. An integrated circuit, comprising: a first node; a second node; an analog-to-digital circuit, comprising: a differential input, voltage sensing circuit that senses a voltage between the first node and the second node, and that outputs a multi-bit digital output value indicative of the voltage, wherein the voltage sensing circuit conducts a first current between the voltage sensing circuit and the first node as the analog-to-digital circuit performs analog-to-digital conversions, wherein the voltage sensing circuit conducts a second current between the voltage sensing circuit and the second node as the analog-to-digital circuit performs analog-to-digital conversions; and an input current cancellation circuit that is coupled to the first node and to the second node, wherein the input current cancellation circuit conducts a third current between the input current cancellation circuit and the first node so that the first current is substantially canceled, wherein the input current cancellation circuit conducts a fourth current between the input current cancellation circuit and the second node so that the second current is substantially canceled, wherein the input current cancellation circuit comprises: a digital processing circuit that outputs a modulated single-bit digital bit stream; and an average current canceling circuit that receives the modulated single-bit digital bit stream signal from the digital processing circuit and that outputs the third and fourth currents.

2. The integrated circuit of claim 1, wherein the voltage sensing circuit also outputs a single-bit digital bit stream, wherein the digital processing circuit of the input current cancellation circuit receives the single-bit digital bit stream from the voltage sensing circuit.

3. The integrated circuit of claim 1, wherein the digital processing circuit comprises a digital sigma-delta modulator.

4. The integrated circuit of claim 3, further comprising: one or more registers that store a multi-bit digital input gain value, wherein the multi-bit digital input gain value is supplied to the digital processing circuit.

5. The integrated circuit of claim 3, further comprising: one or more registers that store a multi-bit digital input gain value, a multi-bit digital input offset value, and a multi-bit digital feedback gain value, wherein the multi-bit digital input gain value, the multi-bit digital input offset value, and the multi-bit digital feedback gain value are supplied to the digital processing circuit.

6. The integrated circuit of claim 1, wherein the average current canceling circuit comprises a switched-capacitor, serially-modulated, charge injector.

7. The integrated circuit of claim 6, further comprising: one or more registers that store a multi-bit compensation voltage value; and a compensation voltage generator circuit that receives the multi-bit compensation voltage value and that outputs a compensation voltage that is supplied to the average current canceling circuit.

8. The integrated circuit of claim 1, further comprising: a first terminal; a first analog multiplexer coupled to supply a voltage on the first terminal onto the first node; a second terminal; and a second analog multiplexer coupled to supply a voltage on the second terminal onto the second node.

9. The integrated circuit of claim 1, wherein there is a high common mode voltage that is present on both the first and second nodes during a time period when the analog-to-digital circuit is performing analog-to-digital conversions, wherein the high common mode voltage is greater than twenty-five volts.

10. A method comprising: (a) sensing a voltage between a first input node of a voltage sensing circuit and a second input node of the voltage sensing circuit and outputting a multi-bit digital output value indicative of the voltage, wherein the voltage sensing circuit conducts a first current between the voltage sensing circuit and the first input node, wherein the voltage sensing circuit conducts a second current between the voltage sensing circuit and the second input node, wherein a first terminal of an integrated circuit is coupled to the first input node, and wherein a second terminal of the integrated circuit is coupled to the second input node; (b) conducting a third current between an input current cancellation circuit and the first input node so that the third current substantially cancels the first current such that substantially no current flows into or out of the integrated circuit through the first terminal, and conducting a fourth current between the input current cancellation circuit and the second input node so that the fourth current substantially cancels the second current such that substantially no current flows into or out of the integrated circuit through the second terminal; (c) receiving a single-bit digital bit stream from the voltage sensing circuit onto a digital processing circuit, and from the single-bit digital bit stream generating a modulated single-bit digital bit stream; and (d) receiving the modulated single-bit digital bit stream from the digital processing circuit and onto a charge injector circuit and using the modulated single-bit digital bit stream to control the charge injector circuit, wherein the charge injector circuit is coupled to the first and second input nodes, wherein the voltage sensing circuit, the first terminal, the second terminal, and the input current cancellation circuit are all parts of the integrated circuit, and wherein (a) through (d) are performed by the integrated circuit.

11. The method of claim 10, wherein the digital processing circuit comprises a digital sigma-delta modulator.

12. The method of claim 10, wherein the charge injector circuit comprises a switched-capacitor, serially-modulated, charge injector.

13. The method of claim 10, further comprising: (e) storing on the integrated circuit in one or more digital registers a multi-bit digital gain value, wherein the multi-bit digital gain value is supplied to the digital processing circuit.

14. The method of claim 10, further comprising: (e) storing on the integrated circuit in one or more digital registers a multi-bit compensation voltage value; and (f) using the multi-bit compensation voltage value to control a compensation voltage generator circuit so that the compensation voltage generator circuit outputs a compensation voltage, wherein the compensation voltage is supplied to the charge injector circuit.

15. The method of claim 10, wherein there is a high common mode voltage that is present on both the first input node and the second input node during a time period when the voltage sensing circuit is outputting the multi-bit digital output value.

16. An integrated circuit, comprising: a first integrated circuit terminal; a second integrated circuit terminal; an analog-to-digital converter circuit that senses a voltage between a first input node and a second input node and outputs a multi-bit digital output value indicative of the voltage, wherein a first current flows into the analog-to-digital converter circuit from the first node during a time period when the analog-to-digital converter circuit is performing an analog-to-digital conversion, wherein a second current flows out of the voltage sensing circuit to the second node during the time period when the analog-to-digital converter circuit is performing the analog-to-digital conversion, wherein there is a high common mode voltage that is present on both the first and second input nodes during the time period, and wherein the high common mode voltage during the time period is greater than twenty-five volts; a first multiplexer that is controlled during the time period to couple the first integrated circuit terminal to the first input node; a second multiplexer that is controlled during the time period to couple the second integrated circuit terminal to the second input node; means for canceling the first current and the second current, wherein the means for canceling is for canceling the first current by supplying a third current from the means for canceling and onto the first input node, wherein the means for canceling is also for canceling the second current by drawing a fourth current into the means for canceling from the second input node, wherein the means for canceling comprises: a digital processing circuit; and an average current canceling circuit that receives a control signal from the digital processing circuit, wherein the average current canceling circuit is coupled to the first input node and to the second input node.

17. The integrated circuit of claim 16, further comprising: one or more digital registers that store a multi-bit digital gain value, wherein the multi-bit digital gain value is supplied to the digital processing circuit.

18. The integrated circuit of claim 16, wherein the digital processing circuit comprises a digital sigma-delta modulator, and wherein the digital sigma-delta modulator receives a single-bit digital bit stream from the analog-to-digital converter circuit.

19. The integrated circuit of claim 16, wherein the control signal that the average current canceling circuit receives from the digital processing circuit is a modulated single-bit digital bit stream.

20. The integrated circuit of claim 16, wherein the analog-to-digital converter circuit comprises an input switches portion, an analog sigma-delta modulator portion, and a digital filter portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.

[0021] FIG. 1 illustrates an example of prior art for sensing the differential voltage between two nodes that have a differential signal and may have a non-zero, common-mode voltage that can be high. The common mode voltage is limited by the electrical breakdown voltage of the capacitor's dielectric.

[0022] FIG. 2 illustrates the quadrature (2-phase), non-overlapping clock signals that are used to control the operation and timing of the switches in the prior art of FIG. 1 and similar precision switched-capacitor circuits.

[0023] FIG. 3 illustrates an additional example of prior art that is capable of sensing the differential voltage in the presence of a high, non-zero common-mode voltage.

[0024] FIG. 4 illustrates an additional example of prior art that is capable of sensing the differential voltage in the presence of a high, non-zero common-mode voltage.

[0025] FIG. 5 illustrates an example of prior art where the differential signal can be integrated over time, in the presence of a high, non-zero common-mode voltage, while still maintaining a fully differential output signal. Examples of this prior art are common as the first stage of sigma-delta modulators which comprise the critical component of sigma-delta Analog-to-Digital Converters.

[0026] FIG. 6 illustrates the flow of charging currents for the voltage sensing capacitors (C1P and C1N) inherent in the operation of the circuit of FIG. 5.

[0027] FIG. 7 illustrates how the time-averaged, charging currents shown by FIG. 6 interact with any low-pass input filter to create an error in the sensing of the true voltage at the battery terminals and derives an approximation for the finite input impedance of the sensing circuit.

[0028] FIG. 8 illustrates an example of prior art where a switched-capacitor network is used to create a compensating, opposing current at the input terminals. With the correct capacitor and compensating voltage values, the differential input charging currents may be completely canceled.

[0029] FIG. 9 illustrates prior art where a parallel input sampling path is used to sense the input voltage and then present this to the compensating circuit of FIG. 8 such that the conditions for input current cancellation may be realized over a wide range of input voltage values. This creates the appearance of an infinite differential input impedance for the complete circuit at nodes N1 and N2.

[0030] FIG. 10 illustrates prior art where the sensing circuit comprises a switched-capacitor, 1st-order sigma-delta modulator. The modulator's digital bit-stream is used in conjunction with the cancellation switched-capacitor network of FIG. 8, a voltage reversing switch and appropriate timing control to cancel the input current and create a high differential input impedance.

[0031] FIG. 11 illustrates prior art which shows an alternative method to achieve high differential input impedance when the sensing circuit is a switched capacitor, 1st order sigma-delta modulator. In this case the modulator bit-stream uses a series of current mirrors to achieve the differential input current injection and cancellation.

[0032] FIG. 12 illustrates an improvement over the compensation circuit of FIG. 8 such that the injected charge may be directly modulated by a synchronized, serial data stream, such that the time averaged compensation current is directly proportional to the average pulse density of the serial data over a finite time interval comprising multiple sample periods.

[0033] FIG. 13 illustrates how the improved circuit of FIG. 12 may be used to directly compensate the differential input impedance of a voltage sensing circuit, when that sensing circuit comprises a switched capacitor, 1st order sigma-delta modulator with a uni-polar input signal range, effected by using an offset generating, switched-capacitor signal path.

[0034] FIG. 14 is a diagram of a circuit 1 including a stack of eighteen batteries connected in series, a set of filter resistors and filter capacitors, and an analog-to-digital converter integrated circuit 3.

[0035] FIG. 15 is a simplified diagram of one example of the circuitry of the VCOMP generator 25 of FIG. 14.

[0036] FIG. 16 is a diagram of a part of the analog-to-digital converter integrated circuit 3 in accordance with one embodiment of the invention. The analog-to-digital converter integrated circuit 3 includes two input voltage terminals and corresponding nodes N1 and N2, a voltage sensing circuit 18, a digital filter 19, a digital processing circuit (a digital sigma-delta modulator) 21, and an average current canceling circuit 22. The digital sigma-delta modulator 21 transforms the analog modulator's data stream DOUT into a second data stream DCOMP, the pulse density of which is more appropriately optimized for the cancellation of the analog modulator's average differential input current over a desired operating region.

[0037] FIG. 17 is a more detailed diagram of the average current canceling circuit 22 of FIG. 16.

[0038] FIG. 18 is a more detailed diagram of the digital sigma-delta modulator circuit 21 of FIG. 16.

[0039] FIG. 19 is a plot that shows the input-to-output data stream pulse-density transformation that is achieved by the digital sigma-delta modulator of FIG. 18 with a chosen set of coefficients applicable to an analog modulator which produces a 12.5% pulse density at 0V differential input voltage and 87.5% pulse density at the desired full-scale input voltage. Such characteristics are common to a uni-polar input, range optimized, 2nd order, analog modulator.

[0040] FIG. 20 shows a typical waveform observed at nodes N1 and N2 of the prior art circuit of FIG. 9.

[0041] FIG. 21, FIG. 22 and FIG. 23 are diagrams that show typical waveforms observed at nodes N1 and N2 of the novel circuit of FIG. 16 for different differential input voltages, relative to the available input range.

DETAILED DESCRIPTION

[0042] Reference will now be made in detail to background examples and some embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0043] It is often necessary to sense and to measure a small differential voltage between nodes that have a large common-mode voltage. For example, it may be necessary to measure the voltage of one battery cell that is connected in a large series of battery cells. The large common-mode voltage must not create a significant error in the measurement of the differential voltage.

[0044] FIG. 1 illustrates an example of prior art for sensing the differential voltage between two nodes that have a differential signal and may have a non-zero, common-mode voltage that can be high. The circuit comprises electronic switches operating in phases A and B, capacitors C1 and C2 and an inverting amplifier.

[0045] FIG. 2 illustrates an example of prior art, quadrature (2-phase), non-overlapping clock signals that are used to control the operation and timing of the switches in the prior art of FIG. 1. The electronic switches labeled A in FIG. 1 were arranged to close when CLK A in FIG. 2 is high and open when CLK A is low. The electronic switches labeled B in FIG. 1 were arranged to close when CLK B in FIG. 2 is high and open when CLK B is low. Since CLK A was only allowed to be high after CLK B was low and CLK B was only allowed to be high after CLK A was low, switches labeled A were never closed at the same time as switches labeled B.

[0046] Periodically opening and closing the groups of switches A and B sequentially caused charge to be transferred between the battery cell and the capacitors. When averaged over a period time equal to one or more full clock periods (T) the charge transfer resembles a current of magnitude I=Q/T. This charge transfer is a fundamental principle by which switched-capacitor circuits operate.

[0047] The charge transfer equations, now presented, illustrate how the circuit of FIG. 1 amplified the battery voltage VBAT while rejecting the common-mode voltage (VP+VN)/2.

[0048] During Phase A, the charges on the capacitors C1 and C2 is given by:

[00001]$\begin{array}{cc}\mathrm{QC}1A=C1*\left(V_P-0\right)& \left(\mathrm{Eq}.1A\right)\end{array}$$\begin{array}{cc}\mathrm{QC}2A=C2*\left(0-0\right)& \left(\mathrm{Eq}.1B\right)\end{array}$

[0049] During Phase B, the charges on the capacitors become.

[00002]$\begin{array}{cc}\mathrm{QC}1B=C1*\left(V_N-V-\right)& \left(\mathrm{Eq}.2A\right)\end{array}$$\begin{array}{cc}\mathrm{QC}2B=C2*\left(V_{\mathrm{OUT}}B-V-\right)& \left(\mathrm{Eq}.2B\right)\end{array}$

[0050] The inverting amplifier was arranged to have a very high gain and forces the signal Vat the inverting terminal of the amplifier to be very, very close to ground by way of negative feedback through C2. If the gain is sufficiently high V=0V. In this case we can simplify Equations 2A and 2B as:

[00003]$\begin{array}{cc}\mathrm{QC}1B=C1*\left(V_N-0\right)& \left(\mathrm{Eq}.3A\right)\end{array}$$\begin{array}{cc}\mathrm{QC}2B=C2*\left(V_{\mathrm{OUT}}B-0\right)& \left(\mathrm{Eq}.3B\right)\end{array}$

[0051] The principle of conservation of charge requires that the sum of change in charge on C1 and the change in charge on C2 is zerosuch that charge is not created or destroyed.

[00004]$\begin{array}{cc}\left(\mathrm{QC}1A-\mathrm{QC}1B\right)+\left(\mathrm{QC}2A-Q2\mathrm{CB}\right)=0& \left(\mathrm{Eq}.4\right)\end{array}$

[0052] Substituting Equations 1A, 1B, 3A and 3B into Equation 4 yields:

[00005]$\begin{array}{cc}C1*\left(V_P-V_N\right)+C2*\left(0-V_{\mathrm{OUT}}B\right)=0& \left(\mathrm{Eq}.5\right)\end{array}$

[0053] Rearranging to solve for V.sub.OUTB:

[00006]$\begin{array}{cc}{V}_{\mathrm{OUT}}B=C1/C2*\left(V_P-V_N\right)& \left(\mathrm{Eq}.6\right)\end{array}$$\begin{array}{cc}\mathrm{QC}1B=C1*\left(V_{N-}V-\right)& \left(\mathrm{Eq}.2A\right)\end{array}$$\begin{array}{cc}\mathrm{QC}2B=C2*\left(V_{\mathrm{OUT}}B-V-\right)& \left(\mathrm{Eq}.3A\right)\end{array}$

[0054] It is clear that the output voltage of the amplifier is an amplified version of the differential input voltage (V.sub.PV.sub.N) or more generally V.sub.BAT. The common mode voltage of (V.sub.P+V.sub.N)/2 has been completely rejected.

[0055] In the circuit of FIG. 1, the capacitor C1 forms a voltage isolation barrier across the capacitor's dielectric layerillustrated by the dashed line. The switches to the left of this isolation barrier and the connected capacitor plate are exposed to high voltages. All the components to the right of the barrierthe majority of the circuit-see only low voltages of similar magnitude to the differential voltage signal. The common-mode voltage which may be rejected is limited by the electrical breakdown voltage of the capacitor used for C1. The breakdown voltage may be controlled by the physical spacing between the capacitor plates and by the specific material used to form the dielectric.

[0056] Those skilled in the art will recognize that the circuit of FIG. 1 is not limited to performing only an amplification function and, with small changes to the circuitry on the low-voltage side of the isolation barrier, the circuit may be further enhanced to implement many important functions. Examples include the input stage of a sample and hold function as might be used in a Successive Approximation or Cyclic ADC or to form the first stage, fully differential, integrator of an analog sigma-delta modulator, as shown in FIG. 5. Standard error correction techniques, common in the equivalent low-voltage circuits, such as auto-zero (to remove the input stage offset error and flicker noise) may equally well be applied to the circuit of FIG. 1 and in FIG. 5 despite the use of the capacitor(s) C1 as an isolation barrier.

[0057] Moreover, as long as C1 is manufactured using standard semiconductor manufacturing techniques, on a semiconductor die alongside similar capacitors the properties of tight parameter matching allow for the same ratio-metric accuracy as is commonly achieved in standard low-voltage circuits.

[0058] The restriction of the high common-mode voltages to a small region of the circuit, limited to switches and capacitor plates, is highly advantageous allowing the majority of the circuit to be built with smaller spacing and therefore to be physically smaller and to operate at higher speeds and with lower power.

[0059] FIG. 3 and FIG. 4 illustrate additional prior art circuits that have been used to reject common-mode voltages. When the common-mode voltages are high, both of these circuits expose more of the active circuitry to the high voltages. In the example of FIG. 3, both plates of capacitor C1 and all the input switches will see high voltages. The inputs of the amplifier and switch B for capacitor C2 will also experience short periods of time where high voltages are present. In the example of FIG. 4, the input current is minimized because capacitor C1 is never discharged and does not need to be completely recharged each clock cycle. However, the amplifier, the capacitor and most switches experience high voltages. As a result, the circuits of FIG. 3 and FIG. 4 are difficult to protect from high voltage damage and are unsuitable for applications where there exist high common-mode voltages. The term high common-mode voltage as the term is used here denotes a common-mode voltage of 5 volts to 90 volts or more.

[0060] FIG. 5 illustrates a fully-differential input, fully-differential output integrator circuit that retains all the isolation advantages of FIG. 1. Those skilled in the art will recognize the advantages of the fully-differential input and output structure for achieving good rejection of power supply interference and other common-mode signal corruption. With the addition of matched (to C1) low-voltage, switched capacitors to form a reference feedback network path this circuit can form an analog, 1st order sigma-delta modulator. Adding additional, purely low-voltage, integrators inside the feedback loop, with the addition of appropriate compensation paths, allows for the realization of higher order sigma-delta modulators. Higher order modulators allow for substantially lower quantization noise at a given over-sampling factor which results in faster, higher resolution, ADC conversion results at the same input sampling rate. 1st order modulators are rarely used in modern designs. 2nd order modulators are much more common, offering a good compromise between increased performance and ease of achieving unconditional modulator loop stability.

[0061] FIG. 6 illustrates the charging paths and change in charge through the input sampling capacitors in a 2-phase sampling network, as used in FIG. 5, with the clock phases as shown in FIG. 2. Unlike the circuit of FIG. 1 the circuit of FIG. 5 uses two input sampling capacitors. The capacitors are switched in anti-phase, such that during each phase of the clock signals, while one capacitor is charging from V.sub.N to V.sub.P the other is discharging from V.sub.P to V.sub.N. The result is that the observed input charge transferred and therefore the average current over a full clock period is doubled for FIG. 5 compared to FIG. 1.

[0062] Consider CLK A:

Q for C1P=QC1PA=C1P*(V.sub.PV.sub.CM)C1P*(V.sub.NV.sub.CM)=C1P*(V.sub.PV.sub.N)(Eq. 7A)

Q for C1N=QC1NA=C1N*(V.sub.NV.sub.CM)C1N*(V.sub.PV.sub.CM)=C1N*(V.sub.PV.sub.N)(Eq. 7B)

[0063] Consider CLK B:

Q for C1P=QC1PB=C1P*(V.sub.NV.sub.CM)C1P*(V.sub.PV.sub.CM)=C1P*(V.sub.PV.sub.N)(Eq. 7C)

Q for C1N=QC1NB=C1N*(V.sub.PV.sub.CM)C1N*(V.sub.NV.sub.CM)=C1N*(V.sub.PV.sub.N)(Eq. 7D)

[0064] Consider the total charge flowing from V.sub.P, from V.sub.N and from V.sub.CM over one clock period:

Total Q from V.sub.P=QC1PA+QC1NB=(C1P+C1N)*(V.sub.PV.sub.N)(Eq. 8A)

Total Q from V.sub.N=QC1NA+QC1PB=(C1N+CIP)*(V.sub.PV.sub.N)(Eq. 8B)

Total Q from V.sub.CM=(QC1PA+QC1NA)=(C1P*(V.sub.PV.sub.N)C1N*(V.sub.PV.sub.N))(Eq. 8C)

[0065] Since C1P=C1N=C1 Equations 8A through 8C simplify to:

Total Q from V.sub.P=2*C1*(V.sub.PV.sub.N)(Eq. 9A)

Total Q from V.sub.N=2*C1*(V.sub.PV.sub.N)(Eq. 9B)

Total Q from V.sub.CM=0(Eq. 9C)

[0066] Equivalent current=charge change/Time and F.sub.SAMPLE=1/T so:

[00007]$\begin{array}{cc}\mathrm{I\_}\left(V_P\right)=2*C1*\left(V_P-V_N\right)/T=2*C1*\left(V_P-V_N\right)*F_{\mathrm{SAMPLE}}=2*C1*V_{\mathrm{BAT}}*F_{\mathrm{SAMPLE}}& \left(\mathrm{Eq}.10B\right)\end{array}$$\begin{array}{cc}\mathrm{I\_}\left(V_N\right)=-2*C1*\left(V_P-V_N\right)/T=2*C1*\left(V_P-V_N\right)*F_{\mathrm{SAMPLE}}=2*C1*V_{\mathrm{BAT}}*F_{\mathrm{SAMPLE}}& \left(\mathrm{Eq}.10B\right)\end{array}$$\begin{array}{cc}\mathrm{I\_}\left(V_{\mathrm{CM}}\right)=0& \left(\mathrm{Eq}.10C\right)\end{array}$

[0067] The equivalent input resistance of the sampling network R.sub.IN is given by:

[00008]$\begin{array}{cc}{R}_{\mathrm{IN}}=V/I=V_{\mathrm{BAT}}/2^{*}C{1}^{*}{V}_{{\mathrm{BAT}}^{*}}{F}_{\mathrm{SAMPLE}}=1/\left(2^{*}C{1}^{*}{F}_{\mathrm{SAMPLE}}\right)& \left(\mathrm{Eq}.11\right)\end{array}$

[0068] FIG. 7 shows prior art with the introduction of a differential, RC, low-pass filter between the battery to be sensed and the switched-capacitor sampling input network. This filter may be desirable for many practical reasons. The battery cell to be measured may be part of a large stack of batteries connected to a load device that generates significant electrical noise. A common load device is a motor, which generates electrical noise as the motor current is switched either electronically or mechanically. The filter helps to reduce high-frequency components of the noise that may disturb the voltage sensing process and introduce an error in the measurement. The RC filter may also be used to help reduce the initial In-rush currents that flow into the semiconductor device pins when a charged or partially charged battery is initially connected to the measurement circuit. With the very high voltages present in a large battery array, these in-rush currents can be very large, even if the filter resistance is also relatively large. The RC filter now presents a significant source impedance to the sampling network

[0069] The finite input impedance of the voltage sensing circuit will now interact with the source impedance of the RC filter. The interaction is complex, especially so, in the common case that either the voltage sensing circuit is shared across a number of battery cells, in a time-interleaved fashion, using a multiplexing circuit or alternatively, when sensing the voltage of a single cell in an intermittent manner. In both cases there is a steady-state error and a shorter-term transient error when the sampling begins and ends.

[0070] In the particular cases to which this invention is applicable, we are concerned only with the steady-state error. The transient error will generally dissipate before the actual start of the voltage sensing process. We may further assume that for the filter to be effective the filter capacitor C.sub.FILT is large compared to the input sampling capacitor C1 and that the filter time constant R.sub.FILT*C.sub.FILT is large compared to the sampling period T=1/F.sub.SAMPLE. Under these conditions it is a reasonable simplification to treat the load of the sampling network as it's equivalent switched-capacitor resistance given by Equation 11.

[0071] The error in the measurement of V.sub.BAT is a direct result of the filtered switched-capacitor input current flowing through the filter resistances R.sub.FILT and may be shown to be:

[00009]$\begin{array}{cc}{V}_{\mathrm{ERROR}}=V_{\mathrm{BAT}}*\left(4*R_{\mathrm{FILT}}*C1*F_{\mathrm{SAMPLE}}\right)/\left(1+4*R_{\mathrm{FILT}}*C1*F_{\mathrm{SAMPLE}}\right)& \left(\mathrm{Eq}.12\right)\end{array}$

[0072] And if the error is small compared to V.sub.BAT then we may simplify this to:

[00010]$\begin{array}{cc}{V}_{\mathrm{ERROR}}=V_{\mathrm{BAT}}*\left(4*R_{\mathrm{FILT}}*C1*F_{\mathrm{SAMPLE}}\right)& \left(\mathrm{Eq}.13\right)\end{array}$

[0073] If we wish to minimize the error term we have three possibilities. Firstly, we might reduce the value of R.sub.FILT. However this would reduce the effectiveness of R.sub.FILT in providing in-rush current protection and would require the value of C.sub.FILT to increase commensurately to retain the same level of source electrical noise suppression. This could lead to possibly unrealistic and physically large values for C.sub.FILT. Secondly, we might reduce the value of C1. Those skilled in the art will realize this will cause higher input referred thermal noise to be captured in the modulator, reducing the available signal-to-noise ratio and degrading the measurement accuracy. Finally, we might reduce the sample frequency. This might require a lower frequency cut-off in the input filter, requiring a larger value for C.sub.FILT and will also reduce the oversampling factor available for a given measurement rate, causing an increase in quantization noise and rapid reduction in measurement accuracy. None of these options are attractive.

[0074] We can avoid all of these detrimental changes if we can create a current at the input filter's connection to the voltage sensing circuit that cancels the voltage sensing circuits dynamic input current. This compensating current must track and cancel the input current over the full input voltage operating range of the voltage sensing circuit. The prior art illustrated in FIG. 9 shows an example of how this can be achieved. Here, a switched capacitor charge injection circuit (as shown in the lower section of FIG. 8) is driven to create a parallel negative input current (I.sub.COMP) which cancels the total positive input current at the sensed nodes (I.sub.SAMP_TOT=I.sub.SAMP+I.sub.SAMPX). To allow this cancellation to be maintained over the desired operating input range, a secondary input is added that forms a switched capacitor level-translator and buffer. This presents the compensating charge injection circuit with a reference input (V.sub.BAT_REP) that tracks the original input voltage and modulates the charge injection and the resulting negative, canceling input current, appropriately.

[0075] A significant penalty of the method of FIG. 9 is that it adds a second input sampling path along with the original input sampling path. The cancellation circuit must now provide additional negative compensation to cancel the positive contributions of both the desired primary sampling network (I.sub.SAMP) and also that of the secondary sampling network (I.sub.SAMPX) used by the buffer in the compensation loop. The sampling capacitors in the secondary input network may be significantly smaller than those in the primary sampler so as to limit the necessary increase in total compensation. This and other circuit non idealities (component mismatch, buffer offsets etc) may impose some limitation in the final accuracy of the current cancellation. We may show that the compensating circuit produces a charge transfer over both phases (1 cycle of operation) given by:

[00011]$\begin{array}{cc}{Q}_{\mathrm{COMP}}=C_{\mathrm{COMP}}*\left(V_{\mathrm{BAT}}-2*V_{\mathrm{BAT\_REP}}\right)& \left(\mathrm{Eq}.14\right)\end{array}$$\begin{array}{cc}{I}_{\mathrm{COMP}}=F_{\mathrm{SAMPLE}}*C_{\mathrm{COMP}}*\left(V_{\mathrm{BAT}}*-2*V_{\mathrm{BAT\_REP}}\right)& \left(\mathrm{Eq}.15\right)\end{array}$

[0076] We may observe from Equation 15 that the compensating circuit also initially adds an additional positive input current of V.sub.BAT(C.sub.COMP)*F.sub.SAMPLE to the source and then subtracts a value which depends linearly on V.sub.BAT_REP and is 2*V.sub.BAT_REP*C.sub.COMP. If we arrange, (through the secondary sampling and buffer) for V.sub.BAT_REP=V.sub.BAT then Equation 15 becomes:

[00012]$\begin{array}{cc}{I}_{\mathrm{COMP}}=-F_{\mathrm{SAMPLE}}*V_{\mathrm{BAT}}*C_{\mathrm{COMP}}& \left(\mathrm{Eq}.17\right)\end{array}$

[0077] And if we wish to compensate just the original sampling current I.sub.SAMP=2*C1*V.sub.BAT*F.sub.SAMPLE then we need:

[00013]$\begin{array}{cc}{I}_{\mathrm{COMP}}=2*C1& \left(\mathrm{Eq}.17\right)\end{array}$

[0078] In practice we must also compensate for the secondary sampling network current driving the buffer (I.sub.SAMPX) and also for any additional stray capacitors on the switched capacitor plates connected to the high-voltage side of the isolation barrier. So, in practice we find C.sub.COMP>2*C1.

[0079] The nodes N1 and N2 experience a temporary disturbance, caused by the initial sampling charges. This disturbance is then canceled as the compensation network switches operate and as the buffer/level-shifter settles. When correctly optimized, the voltage will return to exactly match V.sub.BAT at the end of every individual sample period (T/2 for a 2-phase double-sampling design). The amplitude of the excursion from V.sub.BAT over the sample period will depend on the value of V.sub.BAT, increasing approximately proportionally, as V.sub.BAT increases. An example waveform is shown in FIG. 20.

[0080] When the primary sampling input also forms the input of a sigma-delta converter, then, under certain conditions it becomes possible to use the digital output of the modulator to control the negative current generating circuit. FIG. 10 and FIG. 11 show two prior art examples of this.

[0081] FIG. 10 is a diagram of a prior art circuit in which a switched capacitor network with switches operates at both the high and low voltage sides of the isolation barrier synchronously with the modulator so that the charge is capacitor coupled across the isolation barrier in a manner similar to that illustrated in FIG. 8 and FIG. 9.

[0082] FIG. 11 is a diagram of a prior art circuit in which the compensating charge is metered in the low-voltage domain and then mirrored through a series of high-voltage current mirrors to the original inputs. In this example, the isolation barrier is not contained to just capacitors. Additionally charge pumps may be required to ensure the circuit can operate successfully when the battery cell being measured is close to either the positive or negative supply of the sensing circuit. For both the circuits of FIG. 10 and FIG. 11 the compensation level may be adjusted by varying the values of V.sub.COMP and C.sub.COMP. FIG. 10 may be used to compensate a bipolar input, but FIG. 11 is limited to compensating a uni-polar input, unless significant complexity is added in the mirror circuitry at the high-voltage nodeswhich is undesirable. The circuit of FIG. 11 has an advantage that the compensating charge injection circuitry does not initially add an extra switched-capacitor load to the input as happens in FIG. 9 and FIG. 10 and so significantly smaller C.sub.COMP may be used for any given V.sub.COMP saving circuit area. This must be balanced against the larger area required by the additional high voltage current mirrors.

[0083] FIG. 12 is a diagram of part of a novel current canceling charge injection circuit. This circuit may use a fixed reference voltage for V.sub.COMP and a pulse-density modulated synchronous DATA stream to vary the time-averaged level of compensating charge injection in direct proportion to the pulse density of the signal DATA. FIG. 17 shows a more detailed implementation of FIG. 12, including the necessary switch control logic and data alignment for 2-phase operation. If we define a value D.sub.COMP (which is allowed to vary between 0 and 1) to represent the time-averaged pulse density of the input signal DATA where 1 represents a continuous stream of all ones and 0 represents a stream of all zeros. This circuit may be described as below:

[00014]$\begin{array}{cc}{Q}_{\mathrm{COMP}}=C_{\mathrm{COMP}}*\left(V_{\mathrm{BAT}}-2*V_{\mathrm{COMP}}*D_{\mathrm{COMP}}\right)& \left(\mathrm{Eq}.18\right)\end{array}$$\begin{array}{cc}{I}_{\mathrm{COMP}}=F_{\mathrm{SAMPLE}}*C_{\mathrm{COMP}}*\left(V_{\mathrm{BAT}}-2*V_{\mathrm{COMP}}*D_{\mathrm{COMP}}\right)& \left(\mathrm{Eq}.19\right)\end{array}$

[0084] Now, if the DATA pulse stream is sourced synchronously as the digital bit-stream of a delta-sigma modulator as illustrated in FIG. 13, D.sub.COMP will be linearly related to the voltage being sensed V.sub.BAT. We may define this linear relationship using an offset O.sub.M and a gain factor G.sub.M such that:

[00015]$\begin{array}{cc}{D}_{\mathrm{COMP}}=G_M*\left(V_{\mathrm{BAT}}\right)+O_M& \left(\mathrm{Eq}.20\right)\end{array}$

[0085] The factors O.sub.M and G.sub.M, are characteristic properties of the modulator structure and typically relate to the modulator gain and the minimum and maximum modulation density available for the digital data stream. These factors are usually tightly constrained by the modulator order and by its stability, noise and operating range requirements.

[0086] The total input current can be generalized as:

[00016]$\begin{array}{cc}{I}_{\mathrm{IN}}=F_{\mathrm{SAMPLE}}*\left[V_{\mathrm{BAT}}*\left(2*C1+C_{\mathrm{COMP}}\left[1-2*V_{\mathrm{COMP}}*G_M\right]\right)-2*V_{\mathrm{COMP}}*C_{\mathrm{COMP}}*O_M\right]& \left(\mathrm{Eq}.21\right)\end{array}$

[0087] Importantly, note that with V.sub.BAT=0, the input current is always overcompensated by the current component related to the minimum modulation value OM by a value of 2*F.sub.SAMPLE*V.sub.COMP*C.sub.COMP*O.sub.M.

[0088] For this to work we must make O.sub.M=0. This is not practical for any real modulator because at a modulation factor of 0 the modulator loop would breakdown. Also at modulation values anywhere close to 0 (or to 1) the frequency shaped quantization noise will move into a region in the frequency domain where the (post modulator) low-pass digital decimation filter can no longer reject it. To correct this, more circuitry may be added to introduce an additional fixed positive current to cancel the excess negative cancellation current. This is complex and counter productive.

[0089] A better solution is to find a way to transform the modulator's raw data stream into a second, related data stream, with minimal delay, which conveys the same information about the input signal (V.sub.BAT) but which is more completely (virtually 100%) modulated and therefore more suitable as a drive signal to the switched-capacitor charge cancellation circuit.

[0090] FIG. 14 is a diagram of a circuit including 1, a stack of eighteen batteries BAT1-BAT18 connected in series, a set of filter resistors R.sub.FILT and filter capacitors C.sub.FILT, an RC filter 2, and an analog-to-digital converter integrated circuit 3. The batteries may be rechargeable lithium-ion batteries, each of which has a nominal charged voltage of 3.6 volts, and a maximum charged voltage of about 4.2 volts. The resistors may, for example, each have a resistance R.sub.FILT that is more than 100 ohms, and each capacitor may have a capacitance C.sub.FILT that is greater than 10 nanofarads. The analog-to-digital integrated circuit 3 measures the voltage V.sub.BAT of each battery and stores the resulting 16-bit measurement value in a corresponding one of eighteen 16-bit registers 4. Reference numerals N0-N18, VDD, GND, SDO, SDI, SCK and CSB identify integrated circuit terminals. The analog-to-digital converter integrated circuit 3 is powered from the VDD terminal. The supply voltage on the VDD terminal can be as high as 90 volts.

[0091] The analog-to-digital converter integrated circuit 3 further includes a first analog-to-digital converter circuit 5 to measure the voltages on each of the upper six batteries, a second analog-to-digital converter circuit 6 to measure the voltages on the middle six batteries, and a third analog-to-digital converter circuit 7 to measure the voltages on the lower six batteries. Each of the analog-to-digital converter circuits 5-7 represented as a block in FIG. 14 includes a differential input voltage sensing circuit, a digital filter that outputs the D.sub.BAT value, and an input current cancellation circuit. In the case of the analog-to-digital converter circuit 5 that measures the voltages on the upper six batteries, there is a first six-to-one analog multiplexer 8 that couples a selected one of the voltage input terminals NO-N5 to the input voltage node IN1 of analog-to-digital converter 5, and there is a second six-to-one analog multiplexer 9 that couples another selected one of the voltage input terminals N1-N6 to the input voltage node IN2 of the analog-to-digital converter 5. These analog multiplexers are controlled so as to measure the voltage on the six batteries BAT1-BAT6, one at a time. The analog-to-digital converter circuit 5 can accurately measure the voltage across a battery when there is as much as 100 volts of common-mode voltage (with respect to the ground node at the bottom of the battery stack). Multiplexers 10 and 11 are the multiplexers for the analog-to-digital converter circuit 6. Multiplexers 12 and 13 are the multiplexers for the analog-to-digital converter circuit 7.

[0092] The integrated circuit 3 further includes an SPI bus input/output digital interface circuit 14. Circuitry outside the integrated circuit can load multi-bit digital values into the integrated circuit via the SPI bus digital interface 14 such that the corresponding nine values that are loaded into trim registers 16 are in turn supplied to each of the three A/D converters 5, 6 and 7. In this way, each of the three analog-to-digital converters 5, 6 and 7 receives its own set of three 10-bit digital trim values I/P_OFFSET, I/P_GAIN and F/B_GAIN from the digital control circuitry 15. Circuitry outside the integrated circuit can also use the SPI bus digital interface 14 to read the eighteen 16-bit measurement data values stored in the eighteen registers 4. The digital control circuitry 15 outputs multiplexer select control signals that are supplied onto the select input leads of the multiplexers 8-13. If during semiconductor manufacturing the semiconductor manufacturing process varies, then performance parameters of circuit components may vary so that circuit operation is affected and this in turn may result in incomplete cancellation and measurement errors. Advantageously, after integrated circuit manufacture, the analog-to-digital converters 5-7 are calibrated and trimmed, and the resulting digital trim values (I/P_OFFSET, I/P_GAIN, F/B_GAIN) are loaded into the nine trim value registers 16. When the integrated circuit 3 is properly trimmed, the trim values supplied to the analog-to-digital converter 5-7 are fixed by writing the trim values into OTP (one-time programmable) memory 17. The trimmability of the integrated circuit 3 makes the integrated circuit 3 more manufacturable and reduces manufacturing costs. The digital control circuitry 15 also generates and outputs two non-overlapping clock signals A and B.

[0093] A bandgap reference voltage circuit 24 supplies a bandgap reference voltage VBG to each of the three analog-to-digital converter circuit 5-7.

[0094] In addition to the trim functionality and circuitry described above, the integrated circuit 3 further includes additional trim functionality and circuitry for adjusting a V.sub.COMP reference voltage that is supplied to each of the three analog-to-digital converter circuits 5-7. The VCOMP1 reference voltage supplied to analog-to-digital converter circuit 5 is determined and adjusted by a corresponding first 5-bit digital value, the VCOMP2 reference voltage supplied to analog-to-digital converter circuit 6 is determined and adjusted by a corresponding second 5-bit digital value, and the VCOMP3 reference voltage supplied to analog-to-digital converter circuit 7 is determined and adjusted by a corresponding third 5-bit digital value. The three 5-bit values are in 2's compliment form. Circuitry outside the integrated circuit can use the SPI bus digital interface 14 to write these three 5-bit values that are stored in three corresponding addressable 5-bit registers 26 in the digital control circuitry 15. Once the desired 5-bit trim values have been determined and set, these values can then be fixed by writing the 5-bit trim values into fifteen associated bits of OTP memory 27. The three 5-bit trim values in registers 26 of digital control circuitry 15 are supplied by fifteen associated conductors 28 to a VCOMP generator circuit 25. For each 5-bit trim value, the VCOMP generator circuit 25 generates and outputs a corresponding V.sub.COMP reference voltage via a pair of conductors to input current cancellation circuitry in the associated one of the analog-to-digital converter circuits 5-7. Increasing the 5-bit trim value increases the voltage V.sub.COMP supplied and thereby increases the gain of the input current cancellation circuitry. The overall gain of the input current cancellation circuitry of a given analog-to-digital converter 5-7 is a function of both its associated multi-bit digital trim gain values stored in registers 16 and its associated multi-bit compensation voltage value stored in registers 26.

[0095] FIG. 15 is a simplified diagram of one example of the VCOMP generator 25 of FIG. 14. A 5-bit code of 01111 gives a maximum gain, a code of 10000 gives a minimum gain, and a code of 00000 gives a nominal gain. The corresponding voltages are approximately 4.537 volts, 4.255 volts, and 4.066 volts (given a 3.2768 input reference voltage VBG received from the bandgap circuit).

[0096] FIG. 16 is a diagram of the analog-to-digital converter 5 portion of the overall an analog-to-digital converter integrated circuit 3 in accordance with one embodiment of the invention. The analog-to-digital converter integrated circuit 3 includes two input voltage terminals and corresponding nodes N1 and N2, a voltage sensing circuit 18, a digital filter 19, and an input current cancellation circuit 20. The voltage sensing circuit 18 and the digital filter 19 together comprise a sigma-delta analog-to-digital converter circuit that outputs a multi-bit digital output value D.sub.BAT. The input current cancellation circuit 20 in the example of FIG. 16 includes a digitally-trimmable digital processing circuit (a digital sigma-delta modulator) 21 and an average current canceling circuit 22.

[0097] FIG. 17 is a simplified circuit diagram of an example of the average current canceling circuit 22 of FIG. 16. The circuit is a two-phase, switched capacitor, serial data modulated, variable charge injector. The appropriate one of the VCOMP voltage reference outputs of the VCOMP generator circuit 25 of FIG. 14 is coupled to the V.sub.COMPHI input conductor of FIG. 16. The V.sub.COMPLO input conductor is coupled to GND. The modulated single-bit digital signal DCOMP from the DMOD.sub.OUT output of the digital sigma-delta modulator 21 of FIG. 16 is supplied onto the DATA input lead of FIG. 17. The signals A and B are the non-overlapping clock signals A and B that are generated by the digital control circuitry 15 of FIG. 14.

[0098] FIG. 18 is a simplified circuit diagram of an example of the digitally-trimmable digital processing circuit 21 of FIG. 16. The single-bit digital signal DOUT is received from the voltage sensing circuit 18 of FIG. 16. The modulated single-bit digital signal DCOMP output by the circuit of FIG. 18 is supplied to the average current canceling circuit 22 of FIG. 16.

[0099] In the embodiment of FIG. 16, an arbitrary first or higher order analog modulator 23 is used as the primary sampling network (in voltage sensing circuit 18). The single-bit output data stream DOUT is transformed, efficiently, into a deeply pulse-density-modulated, synchronous signal, to drive the compensation network. The additional circuitry is all realized in the digital circuit domain and so, in modern processeswhere digital logic is very compactthis solution adds very little circuit area. Furthermore, the parameters determining the characteristics of this new circuit are precisely predictable and may be changed by simply changing coefficient values in the digital logic. This greatly simplifies the process of any necessary trimming that might be required to compensate for component variations in the analog domain.

[0100] In the presently described analog-to-digital integrated circuit of FIG. 14, the digital interface terminals include the SDO terminal, the SDI terminal, the SCK terminal, and the CSB terminal. The digital interface circuit 14 (see FIG. 14) that is coupled to these terminals implements an SPI serial bus interface. This SPI serial bus interface 14 is usable to load into the integrated circuit a 10-bit digital input offset (I/P_OFFSET) value, a 10-bit digital input gain (I/P_GAIN) value, and a 10-bit digital feedback gain (F/B_GAIN) value. When the analog-to-digital integrated circuit is being tested at the final test stage of integrated circuit production, a known input voltage is supplied onto the voltage input terminals and the error is observed. The values for I/P_OFFSET and I/P_GAIN are then adjusted by loading new I/P_OFFSET and I/P_GAIN values into the integrated circuit via the digital interface circuit so as to change the transfer function of the overall input current cancellation circuit. The new error is then observed. This sequence of adjusting the trim values and observing the resulting error is carried out multiple times in order to determine the desired trim values. Once the desired trim values have been determined and have been loaded into the integrated circuit, they are then programmed into the fuse-type OTP (One Time Programmable) memory 17 of the digital interface circuit 14.

[0101] In the presently described analog-to-digital integrated circuit of FIG. 16, the decimation digital filter may be a sinc filter. In one example in which the decimation digital filter is a third-order sinc filter, the sinc filter involves a cascade of three digital integrators, a digital sample and hold circuit, and a cascade of three digital differentiators. The digital integrators are clocked at the same data rate as the analog modulator, and the digital sample and hold circuit and the digital differentiators are clocked at the desired output data rate.

[0102] The analog-to-digital integrated circuit 3 of FIG. 16 differs from the circuits of FIG. 13, FIG. 10 and FIG. 11 because it includes a digital sigma-delta modulator in the input current compensation loop, and because the transfer function of the input current compensation circuit is digitally programmable.

[0103] To achieve high depths of modulation at its output, a first-order sigma-delta modulator is used and includes a digital integrator that has its output range limited. The limiting function serves to improve the transient settling and recovery times of the compensation loop and to allow it to rapidly respond to changes in the battery voltage V.sub.BAT or to the start of voltage sensing when initiated from an idle state. An optional RESET may be used to further improve transient settling of the loop when a measurement starts. The illustrated first-order digital modulator shown is not the only possible implementation. Other implementations may split the summation of the inputs and the integration function into multiple separate adders and might also use number representations other than the 2's compliment format illustrated. The blocks shown as MUXes may also be implemented as AND functions.

[0104] In the implementation of the digitally-trimmable digital processing circuit 21 of FIG. 18, the incoming signal DMOD.sub.IN is the single-bit input signal DOUT bit stream received from the voltage sensing circuit 18 of FIG. 16. The signal CLK may, for example, be the clock signal CLKA. Each of the two multiplexer symbols at the right of the diagram represents a 10-bit, two-to-one multiplexer. The bipolar limiter receives a 10-bit digital value and outputs that same 10-bit value to the register, unless the incoming value is greater (a larger positive number) than a predetermined maximum positive value, in which case the bipolar limiter outputs that predetermined maximum positive value. If the incoming value is more negative (a larger negative number) than a predetermined maximum negative value, then the bipolar limiter outputs the predetermined negative value. The register symbol represents a 10-bit register. The MSB of the 10-bit value as output from the register is a sign bit, indicating whether the value is a positive value or a negative value. The single-bit signal DMOD.sub.OUT is an inverted version of the sign bit.

[0105] When the last registered value of the integrator is a positive value, a feedback gain value of F/B_GAIN is subtracted on the next active clock edge so as to reduce the next value of the integrator. When the last value of the integrator is negative, a feedback value of 0 is added to the integrator instead. On each active clock edge, a value equal to the value of I/P_OFFSET is subtracted from the integrator. Finally on each active clock edge, a value of either I/P_GAIN or 0 is added to the integrator depending on the state of the input from the analog modulator DMOD.sub.IN. When DMOD.sub.IN is 1 then I/P_GAIN is added, whereas when DMOD.sub.IN is 0, then 0 is added. If I/P_GAIN has a value of eight, and if I/P_OFFSET has a value of 1, and if F/B_GAIN has a value of six, then the pulse-density transformation between DMOD.sub.IN and DMOD.sub.OUT, as illustrated by FIG. 19, is observed.

[0106] The negative feedback in the modulator attempts to maintain the integrator value at 0. In this example, the value of F/B_GAIN is less than that of I/P_GAIN. As a result, the pulse density of the signal DMOD.sub.OUT (D.sub.DMODOUT) will increase more rapidly as the pulse density of the signal DMOD.sub.IN (D.sub.DMODIN) increases. The pulse-density transfer function is given by:

[00017]$\begin{array}{cc}{D}_{\mathrm{DMPDOUT}}=\mathrm{limit}\left(1,0,\left[\left(I/\mathrm{P\_GAIN}*D_{\mathrm{DMODN}}+I/\mathrm{P\_OFFSET}\right)/F/\mathrm{B\_GAIN}\right]\right)& \left(\mathrm{Eq}.22\right)\end{array}$

[0107] Here the limit function constrains pulse density to a maximum of 1 (all ones) and a minimum of 0 (all zeros).

[0108] In the circuit of FIG. 18, when the value of the pulse density of DMOD.sub.IN (D.sub.DMODIN) is in the regions which cause the output pulse density of DMOD.sub.OUT (D.sub.DMODOUT) to become limited to either all ones or all zeros, the integrator would naturally drift to an unbounded value, and the modulator feedback loop is essentially opened. It is in this region that operation of the bipolar limiter becomes important and now operates to set well defined minimum and maximum integrator values. This prevents any problem that might be caused by the integrator's digital value wrapping due to a finite word-width limitation. The limiting of the integrator value also ensures that when the modulator input returns into a region that is no longer causing the modulator to saturate, the integrator value will return to a value close to zero withing a small number of clock cycles. This improves the transient setting of the modulator and allows the compensation loop to respond quickly to changes in input voltages and the corresponding current. A balance must be chosen between settling time and the normal range of operation of the modulator's integrator values.

[0109] The coefficients and transfer function of FIG. 19 are close to ideal when using a typical uni-polar input range, second order sigma-delta modulator, as the primary voltage sensing circuit. In this case the input range of the converter may be offset using a switched capacitor network such that with a 0V differential input voltage a pulse density of 12.5% (D.sub.DMODIN=0.125) is generated at the modulator digital output. The gain of the modulator is set such that at the desired full-scale input voltage a pulse density of 87.5% (D.sub.DMODIN=0.875) is returned. These minimum and maximum pulse densities ensure that the quantization noise remains in frequency regions that are adequately rejected by a simple third-order sinc decimation filter.

[0110] The digital modulator advantageously transforms the output digital data stream (DOUT in FIG. 16) of the original analog modulator 23 of the voltage sensing circuit 18 into a new compensation digital data stream (DCOMP in FIG. 16) which exhibits 100% pulse density at full-scale input (V.sub.BATMAX) and 0% pulse density at 0V. This action both removes the issue of excess input charge compensation at 0V (since the compensation data pulse-density is now zero at this input value) and also allows the minimum value of V.sub.COMP to be usedsince the compensation data pulse-density is now one at the full-scale input voltage. The digital modulator operates at the analog modulators sample rate, so there is very little delay in the current compensation path back to the input RC filter. The exact delay depends on the analog modulator coefficients, but is typically a few clock cycles at the analog modulator clock rate. This is very much faster than if the circuit were to have to wait for a fully decimated conversion in order to determine the value of V.sub.BAT. (involving a delay of perhaps several hundreds of analog modulator clock cycles).

[0111] Minimizing the necessary value of V.sub.COMP is important if V.sub.COMP must be generated in the low voltage circuitry. However, if V.sub.COMP can be generated in the high voltage domain then there is an additional freedom to reduce the value of C.sub.COMP and thereby reduce the circuit area. The reader will recall Equation 21 and with the digital modulator in the compensation loop and at the maximum input voltage V.sub.BATMAX where D.sub.DMODOUT=1, we may now set the values of O.sub.M to 0 and G.sub.M to 1/V.sub.BATMAX. This yields:

[00018]$\begin{array}{cc}\max \left(I_{\mathrm{IN}}\right)=F_{\mathrm{SAMPLE}}*V_{\mathrm{BATMAX}}*\left(2*C1+C_{\mathrm{COMP}}\left[1-2*V_{\mathrm{COMP}}/V_{\mathrm{BATMAX}}\right]\right)& \left(\mathrm{Eq}.23\right)\end{array}$

[0112] If we set I.sub.IN to 0 then we may solve either for C.sub.COMP with a given V.sub.COMP:

[00019]$\begin{array}{cc}{C}_{\mathrm{COMP}}=2C1/\left(2*V_{\mathrm{COMP}}/V_{\mathrm{BATMAX}}-1\right)& \left(\mathrm{Eq}.24\right)\end{array}$

[0113] Or for V.sub.COMP with a given C.sub.COMP:

[00020]$\begin{array}{cc}{V}_{\mathrm{COMP}}=V_{\mathrm{BATMAX}}*\left(2C1+C_{\mathrm{COMP}}\right)/\left(2*C_{\mathrm{COMP}}\right)& \left(\mathrm{Eq}.25\right)\end{array}$

[0114] Note that in both cases when we set V.sub.COMP=V.sub.BATMAX then C.sub.COMP=2*C1. This is the exact same result achieved in Equation 17 for the circuit of FIG. 9. However, here we have the flexibility to adjust V.sub.COMP to easily change the ratio of C.sub.COMP to C1 should we wish to do so. A higher V.sub.COMP may be used to enable a reduction in the size of C.sub.COMP perhaps necessary to save area. Alternatively, a lower V.sub.COMP may be used along with a higher C.sub.COMP wherever that may be more advantageous.

[0115] FIG. 21, FIG. 22 and FIG. 23 show how the voltage observed between nodes N1 and N2 is modulated by the input current compensation circuit 20 in response to the DCOMP control signal. It may be noted we remove the requirement that the value of V.sub.(N1,N2) be restored to V.sub.BAT in T/2. Now, only the average value of V.sub.(N1,N2) over a longer time period, matches the applied input voltage V.sub.BAT. Three cases are shown for circuit operation with an input operating range of 0V to 5V and at V.sub.BAT values of 1.6V, 2.7V and 4.4V. The peak-to-peak amplitude of this modulation is a function of the ratio of C.sub.COMP to C.sub.FILT. Larger C.sub.FILT will reduce the modulation signal amplitude. In the waveform diagrams of FIG. 21, FIG. 22 and FIG. 23, the signals A and B are the non-overlapping clock signals A and B generated by the digital control circuitry 15 of FIG. 14.

[0116] In one example, the analog-to-digital converter with the novel input current cancellation circuit is distinguished from prior art circuits in that there is a small voltage signal present on the input terminals (for example, N1 and N2 of FIG. 14), for example when a battery is being measured from these terminals. This voltage signal has a spectral component at a frequency lower than the frequency of the sample rate (the frequency of non-overlapping sample signals A and B), and that spectral component has an amplitude that is larger than the amplitude of any spectral component (of the voltage signal) of the sample rate frequency or higher. In prior art similar circuits of the type that generate signals of the type illustrated in FIG. 20, there is no substantial spectral component (of the voltage signal present on the input terminals) at a frequency lower than the sample rate frequency.

[0117] In summary, the introduction of the digital modulator into the compensation loop enables a sampling input current compensation circuit (FIG. 16) that is at least as effective as the, prior art, analog equivalents (FIG. 9 through FIG. 13) but which now has the significant advantages of: (1) No need for a parallel input sampling network or buffer structure in the compensation path. (2) A simple 2-phase switched-capacitor differential charge injection circuit with serial pulse-density modulation may be used. (3) May be used with any analog sigma-delta modulator, of any order, as the primary sensing circuit. (4) Has a low area overhead due to the digital implementation of the extra modulator. (5) May be easily trimmed in the digital domain by simply changing the digital coefficient values of the digital modulator. (6) Allows flexibility to reduce or increase the size of the compensation capacitors C.sub.COMP by means of a simple trade-off between a DC voltage, V.sub.COMP and the size of C.sub.COMP.

[0118] Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.