Abstract
Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.
Claims
1. A spin manipulation and readout circuit, comprising: a spin manipulation circuit comprising at least one input amplifier configured for 50 Ohm input matching and having a bandwidth configured for spin excitation frequency in the range of 60 to 160 Ghz.
2. The spin manipulation and readout circuit of claim 1, further comprising a readout amplifier connected to a drain of a qubit to drive 50 Ohm.
3. The spin manipulation and readout circuit of claim 1, wherein the spin excitation frequency is configured for on-off modulation by pulse widths of about 20 ps.
4. The spin manipulation and readout circuit of claim 2, wherein the spin excitation frequency is configured for on-off modulation by pulse widths of about 20 ps.
5. The spin manipulation and readout circuit of claim 1, further comprising a double quantum dot structure having a first gate, a second gate, and a third gate, the third gate configured as a barrier for a dot under the second gate.
6. The spin manipulation and readout circuit of claim 2, further comprising a double quantum dot structure having a first gate, a second gate, and a third gate, the third gate configured as a barrier for a dot under the second gate.
7. The spin manipulation and readout circuit of claim 3, further comprising a double quantum dot structure having a first gate, a second gate, and a third gate, the third gate configured as a barrier for a dot under the second gate.
8. The spin manipulation and readout circuit of claim 4, further comprising a double quantum dot structure having a first gate, a second gate, and a third gate, the third gate configured as a barrier for a dot under the second gate.
9. The spin manipulation and readout circuit of claim 1, wherein the circuit is fabricated in a production 22 nm Fully Depleted Silicon on Insulator (FDSOI) technology.
10. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 1.
11. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 2.
12. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 3.
13. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 4.
14. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 5.
15. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 6.
16. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 7.
17. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 8.
18. A monolithic processor architecture comprising the spin manipulation and readout circuit of claim 9.
Description
BRIEF DESCRIPTION OF THE FIGURES
[0023] The principles of the invention may better be understood with reference to the accompanying figures provided by way of illustration of an exemplary embodiment, or embodiments, incorporating principles and aspects of the present invention, and in which:
[0024] FIGS. 1(a) to 1(d) show an embodiment of an n-MOSFET cascode as two coupled quantum dot qubits along with its subbands, wave functions, and mode splitting energy;
[0025] FIGS. 2(a) to 2(b) show the simulated n-MOSFET conduction band profile of an embodiment;
[0026] FIGS. 3 (a) to 3(b) show coupled-QD simulations of an embodiment;
[0027] FIG. 4 shows a schematic diagram of an embodiment of a DQD qubit;
[0028] FIG. 5 shows a microphotograph of a qubit embodiment;
[0029] FIG. 6 shows a microphotograph of a qubit embodiment with readout TIA;
[0030] FIG. 7 shows the MOSFET transfer characteristics of an embodiment at V.sub.DS=50 mV;
[0031] FIGS. 8(a) to 8(b) show the measured transfer characteristics against back gate voltage and V.sub.DS at 2 K of n-MOSFET and p-MOSFET embodiments;
[0032] FIG. 9 shows the I.sub.DS-V.sub.GS across several temperatures for an n-MOSFET embodiment;
[0033] FIGS. 10(a) and 10(b) show the measured against simulated transfer characteristics for n-MOSFET and p-MOSFET embodiments;
[0034] FIGS. 11(a) and 11(b) show the transfer characteristics against V.sub.DS at V.sub.BG=0.5V and 2 K for DQD n-qubit and p-qubit embodiments;
[0035] FIG. 12 shows the n-MOSFET output characteristics of an embodiment;
[0036] FIG. 13 shows the peak linear g.sub.m against temperature data of an embodiment;
[0037] FIGS. 14(a) to 14(c) show saturation region data for various MOSFET embodiments at V.sub.DS=0.8 V;
[0038] FIGS. 15(a) to 15(d) show measured characteristics for a 4020 nm by 590 nm n-MOSFET embodiment at 300 K and 3.3 K;
[0039] FIG. 16 shows the MOM capacitance and Q of an embodiment;
[0040] FIG. 17 shows the resistance against frequency data for 1000 and 2000 polyresistors at 300 K and 3 K;
[0041] FIG. 18 shows the measured TIA of an embodiment at 300 K and 2 K;
[0042] FIG. 19 shows Z.sub.21, S.sub.21, and S.sub.22 data for an n-qubit embodiment with TIA readout at 300 K;
[0043] FIGS. 20(a) and 20(b) show direct-modulation monolithic quantum processor architecture and 2D tunnel-coupled qubit array layout scheme embodiments;
[0044] FIGS. 21(a) to 21(c) show schematic diagrams of electron-spin qubit-with-TIA circuit embodiments and measured against simulated S.sub.21 gain of electron-spin qubit plus TIA in 22 nm FDSOI embodiments;
[0045] FIG. 22 shows a microphotograph of a test chip embodiment;
[0046] FIG. 23 shows normalized transconductance and .sub.T /.sub.MAX against V.sub.GS measurements for 4020 nm by 590 nm MOSFET embodiments;
[0047] FIGS. 24(a) and 24(b) show measured .sub.T and .sub.MAX against current density for 4020 nm by 590 nm MOSFET embodiments;
[0048] FIGS. 25(a) and 25(b) show measured R.sub.G and R.sub.S for 4020 nm by 430 nm MOSFET embodiments;
[0049] FIGS. 26(a) to 26(d) show measured passives for an embodiment's 400 m long transmission line S.sub.11, 400 m long transmission line S.sub.21, 200 fF MOM capacitor, and 100 and 200 poly resistors;
[0050] FIG. 27 shows transfer characteristics for 120 nm by 80 nm n-MOSFET and p-MOSFET QD embodiments;
[0051] FIG. 28 shows a schematic diagram of an integrated DQD structure and readout circuit embodiment;
[0052] FIG. 29 shows measured output characteristics for a 120 nm by 80 nm n-MOSFET QD embodiment;
[0053] FIG. 30 shows measured output characteristics for a 120 nm by 80 nm p-MOSFET QD embodiment;
[0054] FIG. 31 shows a schematic diagram of an integrated qubit embodiment with ten cascodes connected in parallel;
[0055] FIG. 32 shows measured S-parameters and simulated data for integrated DQD-with-TIA embodiments;
[0056] FIG. 33 shows measured Z.sub.21 from 1 p-MOS DQD-with-amplifier embodiments;
[0057] FIG. 34 shows the measured output spectrum of 1 p-DQD with TIA;
[0058] FIG. 35 shows a table comparison of state-of-the-art qubit readout amplifiers;
[0059] FIGS. 36(a) to 36(c) show embodiments of a) p-MOSFET single-spin qubit, b) double-spin p-type cascode qubit, and c) triple-spin p-type cascode qubit;
[0060] FIGS. 37(a) and 37(b) show two embodiments of a two-qubit quantum processor with spin manipulation and readout circuits; and
[0061] FIG. 38 shows a schematic of a back gate biasing circuit to ensure constant current density biasing at all temperatures.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0062] The description that follows, and the embodiments described therein, are provided by way of illustration of an example, or examples, of particular embodiments of the principles of the present invention. These examples are provided for the purposes of explanation, and not of limitation, of those principles and of the invention. In the description, like parts are marked throughout the specification and the drawings with the same respective reference numerals. The drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly to depict certain features of the invention.
[0063] According to an embodiment, this description relates to monolithically integrated semiconductor quantum processors, such as per the characterizations in D1 (S. Bonen, et al. Cryogenic Characterization of 22-nm FDSOI CMOS Technology for Quantum Computing ICs. In IEEE, 2018) and the designs in D2 (M. Gong, et al. Design Considerations for Spin Readout Amplifiers in Monolithically Integrated Semiconductor Quantum Processors), the entirety of which is hereby incorporated by reference. In particular, it relates to the design of a monolithic qubit integrated circuit consisting of a qubit realized as the minimum size (Lmin, Wmin) undoped channel double-gate n- or p-channel MOSFET in an FDSOI process driving a readout circuit consisting of a chain of appropriately scaled gain stages consisting of alternating transimpedance amplifiers and CMOS inverters.
[0064] According to an embodiment, the present description relates to an output stage that is matched to 50 and is capable to drive off chip instruments or other circuits. A diode-connected MOSFET may be connected to the supply (in electron-spin qubits) or to ground (in hole-spin qubits) at the output of the qubit to ensure sinking. A capacitor may be placed between the qubit and the readout amplifier to avoid DC current interaction. In a further embodiment, the diode is absent.
[0065] According to an embodiment, the present description relates to an ultra-lower-power (<5 mW) qubit IC for reading Rabi oscillations in the DC-to-60 GHz range in 22 nm and 12 nm FDSOI, that was fabricated and measured in 22 nm FDSOI technology and simulated in 12 nm FDSOI technology.
[0066] According to embodiments of the invention, the present description relates to a qubit concept and qubit IC that may be scalable in future CMOS nodes down to 2 nm (or smaller) where, according to quantum simulation, the qubit can operate at room temperature.
[0067] According to an embodiment, the present description relates to monolithic quantum computing integrated circuits operating above 1 Kelvin in 22 nm FDSOI CMOS, at about 4-5 K in 12 nm FDSOI CMOS, and at about 77 K in 5 nm CMOS technology.
FDSOI N- and P-Type Qubits
[0068] According to an embodiment as shown in FIG. 1(a), an n-MOSFET cascode 1000 may be designed as two coupled quantum dot qubits 1100. The qubits are realized using series-stacked Si n-MOSFET and SiGe p-MOSFET minimum size cascodes with multiple gates. QDs are formed in undoped semiconductor film 1200 below each top gate 1300, while the tunneling barrier and, therefore, electron or hole entanglement and exchange interaction between QD.sub.S, is controlled by the back gate 1400 formed in the Si substrate below the buried oxide (BOX) layer 1500 or by top gates 1300. According to an embodiment, the physical gate length (L) and width (W.sub.f) may be within the range of about 12 to 20 nm and about 40 to 80 nm, respectively, while the gate pitch is within the range of about 50 to 100 nm. The subbands, wave functions, and mode splitting energy in a coupled quantum dot qubit are shown in FIG. 1(b).
[0069] According to the embodiments as shown in FIGS. 36(a) to 36(c), a p-MOSFET cascode may be designed as two coupled quantum dot qubits as shown for example in FIG. 36(b). The qubits are realized using series-stacked SiGe p-MOSFET cascades minimum size cascodes with multiple gates. QDs are formed in undoped SiGe semiconductor film below each top gate, while the tunneling barrier and, therefore, hole entanglement and exchange interaction between QDs, is controlled by the back gate formed in the Si substrate below the buried oxide (BOX) layer or by top gates. Si.sub.1-xGe.sub.x/Si.sub.1-yGe.sub.y heterojunctions are formed between the source and the channel and between the drain and the channel where y>x are the Ge mol fractions and both y and x are between 0 and 1. According to an embodiment, the physical gate length (L) and width (W.sub.f) may be within the range of about 12 to 20 nm and about 40 to 80 nm, respectively, while the gate pitch is within the range of about 50 to 100 nm. The subbands, wave functions, and mode splitting energy in a coupled quantum dot qubit are shown in FIG. 1(b).
[0070] The n-MOSFET and the p-MOSFET qubits are fabricated as standard transistors and cascodes in a commercial FDSOI CMOS process with several mask waivers as described in the following paragraphs.
[0071] In FIG. 1(c) and FIG. 1(d), a top-level layout view of an embodiment of a fabricated n-qubit is provided with two active gates 1310 and three dummy gates 1320 on each side of the qubit. According to an embodiment, a blocking mask 1600 is placed between the two gates of the coupled double-QD (DQD) qubit to prevent ion implantation and contact formation in the undoped channel.
[0072] FIG. 2(a) shows the TCAD-simulated conduction band profiles and energy levels along the z-direction (eigen-energy levels also shown), perpendicular to the gate-channel interface. The conduction band profile along the n-MOSFET channel (x-direction) is reproduced in FIG. 2(b) at 77 K for various V.sub.GS values and V.sub.DS of 1 mV. In these embodiments, it appears that the gate-source and gate-drain spacers are sufficient to form 10 meV parabolic potential barriers which confine the carriers between the source and drain in the x-direction. Confinement along the y-a nd z-directions is provided by the gate oxide, buried oxide (BOX), and shallow trench isolation (STI), which act as infinite potential barriers.
[0073] FIG. 3(a) shows the conduction band and Fermi-level profiles in a DQD qubit embodiment at 300 K, illustrating how the height of the potential barrier between the two QDs could be controlled by a n-well or p-well placed selectively only below the barrier region.
Simulations of coupled QD scaling in other embodiments are shown in FIG. 3(b), indicating that E>30 meV will be possible at 2 nm minimum feature size. This supports the feasibility of room temperature operation in some embodiments.
[0074] According to an embodiment, qubit strain uniformity and matching may be improved and quantum gate fidelity can be increased by connecting multiple qubits in parallel in the form of a multi-finger, minimum-size n- or p-type cascode layout. One such embodiment is shown in FIG. 4.
Cryogenic Measurements
[0075] According to an embodiment, transistors, qubits, TIAs, qubit-with-TIA circuits, and full quantum processors consisting of qubit-with-TIA and spin-manipulation circuits are fabricated in a production 22 nm FDSOI technology. On-die dc and S-parameter measurements are carried out on such embodiments at 300 K, 2 K, and 3.3 K using a Lake Shore CPX VLT system. A microphotograph of the embodiment tested is shown in FIG. 5 along with a detailed view of the n-qubit with TIA readout IC in FIG. 6.
[0076] Several notable features appear in the 3.3 K (shown in FIGS. 7) and 2 K (shown in FIGS. 8(a) and 8(b)) transfer characteristics of single- and 40 gate finger minimum-size 20 nm by 80 nm MOSFETS at V50 mV. First, current steps can be observed in the subthreshold region as the lowermost energy levels due to confinement in the z-direction are being sequentially occupied by electrons and holes, respectively. Second, by connecting 40 gate fingers together, the current steps are amplified in both n- and p-MOSFETs. This feature may be exploited to increase the manufacturability and fidelity of qubits at the hardware level, reducing demand on repeated logic operations for error correction. Third, the current steps transform into oscillations with large peak-to-trough ratios as the temperature is reduced to 2 K and V.sub.DS is reduced below 50 mV, as illustrated in FIGS. 8(a) and 8(b) for n- and p-MOSFETS, respectively. The oscillatory behavior is indicative of electron/hole resonant tunneling through the source and drain barriers along the x-direction (see also the inset in FIG. 2(b)). The separation between adjacent peaks, V.sub.GS, depends on the energy level in the channel QD and is inversely proportional to the capacitance between the top gate 1300 and the charge centroid in the channel, C.sub.gs+C.sub.gd. The latter can be tuned from the back gate 1400 and increases as the charge moves closer to the top gate 1300 oxide interface. A larger V.sub.GS is desirable to achieve better noise immunity and larger .sub.Rabi when applying the spin control mm-wave signal on the qubit gate as it improves qubit fidelity at higher temperatures and allows for faster quantum processors. According to an embodiment, the larger V.sub.GS of the p-MOSFET is due to the smaller hole effective mass and the additional heterojunction barriers in the valence band along the x-direction which are caused by a larger Ge mole fraction in the source/drain regions compared to in the channel.
[0077] The 20 nm by 80 nm n-MOSFET embodiment transfer characteristics shown in FIG. 9, which compares I.sub.DS-V.sub.GS against temperature, indicate that most of the V.sub.t shift occurs between 300 and 77 K.
[0078] FIGS. 10(a) and 10(b) reproduce the measured and simulated I.sub.DS against V.sub.GS characteristics of the n- and p-MOSFET QDs according to a 120 nm by 80 nm embodiment with ballistic transport and an NEGF formation, with assumed conduction/valence band profile and effective mass shown in the insets. The best fit conduction and valence band profiles are shown in the insets according to an embodiment with 20 nm thick, 6 meV and 40 me V barriers, respectively. The effective masses are chosen for best fit, but are approximately equal to 0.19 mo transverse electron mass in Si and within the 0.043 m.sub.0 to 0.15 m.sub.0 light-hole mass range in SiGe at 4.2 K.
[0079] FIGS. 11(a) and 11(b) reproduce the measured transfer characteristics (with V.sub.G1=V.sub.G2) of the electron- and hole-spin coupled double QB qubits, respectively, showing resonant tunneling through the three barriers and two wells. The V.sub.G1=V.sub.G2 location of the tunneling peaks in the electron- and hole-spin DQD device embodiments remains practically constant for |V.sub.DS|<5 mV, which is a V.sub.DS range large enough to support high-fidelity spin-readout circuit design and operation.
[0080] FIGS. 12 to 15 are a compilation of the measured output characteristics of various embodiments, with the small signal equivalent circuit parameters and high frequency figures of merit for several p- and n-channel MOSFETS showing 100% increase in linear region transconductance, 25-40% in the peak transconductance in saturation, C.sub.GS and .sub.T at 3.3 K, 5-10% in .sub.MAX, and less than 10% degradation in source resistance (R.sub.s), gate resistance (R.sub.g), and C.sub.gd. In particular, FIG. 12 shows n-MOSFET output characteristics for a 4020 nm by 590 nm MOSFET embodiment, whereas FIG. 13 shows the peak linear g.sub.m vs. temperature for a 4020 nm by 590 nm MOSFET embodiment. FIG. 14(a) shows the peak g.sub.m against temperature, FIG. 14(b) shows the peak .sub.T against temperature, and FIG. 14(c) shows the .sub.MAX against temperature, each in the saturation for various MOSFET embodiments at V.sub.DS=0.8V. The .sub.MAX against I.sub.DS, .sub.MAX against V.sub.GS, C.sub.gs, C.sub.gd against V.sub.GS, and extracted R.sub.GS, R.sub.S against frequency output data are shown for a 4020 nm by 590 nm embodiment in FIGS. 15(a), 15(b), 15(c), and 15(d) respectively.
[0081] Furthermore, the MOM capacitance data in FIG. 16 and the poly resistance data in FIG. 17 vary by less than 5% while the MOM capacitor Q improves at 3.3 K. FIG. 18 shows that the TIA gain improves at 2 K while S.sub.22 is unchanged. In an embodiment where the TIA is integrated with the n-qubit, FIG. 19 shows that at 300 K Z.sub.21 is preserved while the unity gain bandwidth exceeds 70 GHz.
Monolithic Qubit ICs
[0082] FIG. 20(a) shows an embodiment of a monolithic processor architecture 20000 integrating 80-240 GHz spin manipulation electronics with potentially billions of qubits and readout circuitry on the same die. According to an embodiment, this may allow for short, 20 ps spin control pulses, 1000 times faster than in the latest 53-qubit Google quantum processor, to compensate for the likely short spin phase coherence lifetimes, expected to be in the 100 ns to 1 s range. According to an embodiment, the quantum processor core consists of linear arrays of coupled QD spin qubits. Given the manufacturing constraints of nanoscale production CMOS technologies, 2D tunable coupling of these spin qubits, needed for a full 2D processor architecture, is a challenge. According to a further embodiment shown in FIG. 20(b), processes and mask waivers accommodate such a 2D array 20100 of tunnel-coupled QDs. According to an embodiment, other 2D arrays of tunnel-coupled QDs are explored through nanofabrication. According to an embodiment, qubits may be coupled in the second dimension through spin-to-mm-wave/THz/optical photon coupling.
[0083] According to an embodiment, the TIA 21000 is designed as shown in FIG. 21(a) with gain, bandwidth, and 50 output impedance that does not overload a 60 aF output capacitance of the DQD qubit. A further embodiment of an electron-spin qubit with a TIA embodiment layout in 22 nm FDSOI is shown in FIG. 21(b), with measured against simulated S.sub.21 gain of electron-spin qubit plus TIA in 22 nm FDSOI shown in FIG. 21(c).
[0084] Ideally, the 1 nA tunneling peaks in FIGS. 8, 10, and 11 require at least 140 dB of transimpedance gain for the readout TIA to reach 10 mV of amplitude in a 50 load. According to an embodiment, part of this gain is implemented off chip to avoid oscillation. According to an embodiment, a monolithic quantum processor may further be optimized for 80 dB gain at 2 K, as shown in the measurements of FIG. 18.
[0085] Collectively, the results and cryogenic measurements of transistors, polysilicon resistors, and MOM capacitors demonstrate that all components of the embodiment with production 22 nm FDSOI technology operate with better performance at 2 K than at 300 K, and that monolithic integration of quantum dot qubits and readout circuitry is possible at 2 K. It can also be seen in FIG. 18 and FIG. 19 that the S.sub.22 of the TIA and qubit-with-TIA remains better than 10 dB up to 70 GKz both at 300 K and 2 K.
Design Considerations for Spin Readout
Amplifiers Cryogenic Technology Characterization
[0086] According to an embodiment, a full set of MOSFETs, 4 m by 7.5 m MOM caps, 100 and 200 poly resistors, and the associated 6 m400 m de-embedding transmission line structures are designed and fabricated in two variants of the 22 nm FDSOI CMOS process with thin metal and thick metal BEOL, respectively. FIG. 22 shows a die microphotograph of a test chip embodiment with chip dimensions of 2.5 mm by 2.0 mm, including 1, 2, and 3 pitch transistor test structures, passive components, quantum dot structures, and double quantum dot with readout circuits.
[0087] FIGS. 23 to 25 compile the measured transconductance, .sub.T, .sub.MAX, R.sub.G, and R.sub.S for fully metallized, single-gate contact n- and p-channel MOSFET embodiments with 40 gate fingers, 20 nm gate length, 1 source/drain contact pitch, and gate finder widths of 430 m and 590 nm, at 3.3 K and 300 K. In particular, FIG. 23 shows the normalized transconductance and .sub.T/.sub.MAX against V.sub.GS measurements for 4020 nm by 590 nm MOSFET embodiments (V.sub.DS=0.8 V). FIGS. 24(a) and 24(b) show, respectively, the measured .sub.T and .sub.MAX against current density for 4020 nm by 590 nm embodiments. FIGS. 25(a) and 25(b) show the measured R.sub.G and R.sub.S, respectively, for 4020 nm by 430 nm MOSFET embodiments.
[0088] All transistor S-parameter measurements include parasitics of the wiring stack up to the top metal, the latter being designed in an embodiment to satisfy electromigration rules up to 110 C. (383.15 K). However, at 2-4 K, electromigration is not a problem and the wiring stack can be redesigned in other embodiments for significantly reduced parasitics, resulting in better circuit performance.
[0089] Compared to 300 K, at 3.3 K the peak transconductance increased by 34% and 25% for the n- and p-MOSFET embodiments, respectively. Peak .sub.T improves by 42% (to 373 GHZ) and 25% (to 226 GHz) for n- and p-MOSFET embodiments, respectively, while peak .sub.MAX improves by about 11% to 223 GHz and 163 GHZ, respectively. The peak-.sub.T, peak-.sub.MAX current densities remain nearly constant across temperature, simplifying the design of embodiments that must operate over a wide temperature range, even in the absence of transistor models valid at 2-4 K.
[0090] FIG. 26 shows the measured passives of the transmission line, MOM capacitor, and poly-Si resistor at 3.3 K and 300 K for an embodiment. In particular, FIGS. 26(a), 26(b), 26(c), and 26(d) show data for an embodiment's 400 m long transmission line S.sub.11, 400 m long transmission line S.sub.21, 200 fF MOM capacitor, and 100 and 200 poly resistors. The 50 transmission line retains its characteristic impedance from room temperature, as evidenced by its measured S.sub.11 in FIG. 26(a), and has lower loss at 3.3 K. The MOM capacitor Q improves at lower temperatures while the capacitance does not change. The poly-Si resistor retains the same resistance across temperature, which is useful in designing TIAs whose output impedance does not change across temperatures.
Readout Amplifier Design
[0091] According to an embodiment, fabricated qubit structures consist of minimum-size Si n-MOSFETs and SiGe p-MOSFETs and cascodes. QDs are formed in thin (<10 nm) undoped semiconductor film 1200 below each top gate 1300, which can be biased to control the confinement energies of each QD while the back gate 1400 formed in the Si substrate below the buried oxide layer 1500 controls the amount of coupling between the QDs in the cascode, which acts as a DQD. These QD structures are expected to behave as electron- and hole-spin qubits when a DC magnetic field is applied.
[0092] FIG. 27 compares the measured transfer characteristics of electron- and hole-spin single quantum-dots of a 120 nm by 80 nm n-MOSFET and p-MOSFET QD embodiment at 2 K and 300 K. At 2 K and low V.sub.DS bias (<50 mV), current oscillations are observed in the sub-threshold region, representative of electron/hole tunneling events through the discrete energy levels of the QD. According to an embodiment, the TIA must detect the fast electron or hole charge transfer events and amplify the resulting small tunneling current at the first peak, on the order of 10 pA to 10 nA, to a voltage swing of at least a few mV, which can be easily processed by off-chip test equipment of FPGAs. This requires a low-noise, high-bandwidth readout amplifier with a transimpedance gain of 100-140 dB, capable of driving 50 without significantly loading the minimum-size QDs which have less than 60 aF output capacitance.
[0093] According to an embodiment, the circuit schematic 28000 in FIG. 28 shows an integrated DQD structure 28100 and readout circuit 28200, where the DQD is representative of a coupled-spin qubit when a DC magnetic field is applied. Both the TIA and the DQD are optimally biased, allowing qubit V.sub.DS control through the V.sub.source terminal and through the V.sub.DD of the TIA. FIGS. 29 and 30 show the measured output characteristics of the n- and p-MOSFET QDs when V.sub.GS is set at the locations of the first peak and valley, respectively, as measured at 2 K in FIG. 27.
[0094] For high fidelity, a QD with a large peak-to-valley current ratio, like the p-MOSFET embodiment in the 22 nm FDSOI process described herein, is desirable. For the n-MOSFET embodiment, because of smaller source/drain barriers in the QD, the peaks and valley are observable in the transfer characteristics (shown in FIG. 27) but reduce to plateaus in the output characteristics (shown in FIG. 29). Both of these characteristics show evidence of Coloumb blockade where electrons/holes selectively tunnel out of the QD. In the readout phase, precise V.sub.DS values in the 0 mV to 5 mV range, are needed to scan for the first peak and valley in the output characteristics to ensure that the resulting drain tunneling current is from a single electron/hole.
[0095] In determining the behavior of both electron- and hole-spin qubits, three types of DQD embodiments are integrated with the same readout TIA (DQD-with-TIA embodiments). The first, DQD embodiment is a single finger p-MOSFET cascode (1-DQD hole-spin qubit). The second, an embodiment with ten p-MOSFET cascodes connected in parallel (10-DQD hole-spin qubit). The third, is a structure with ten n-MOSFET cascodes connected in parallel (10-DQD electron spin qubit). All such QD and TIA MOSFET embodiments have a physical gate length of 18 nm, with a QD finger width of 70 nm. FIG. 31 shows the layout for the QD embodiments with 10 gate fingers connected in parallel. The readout amplifier consists of three cascaded CMOS-inverter TIA stages with CMOS inverters placed in-between to maximize gain, the interstage fanout below three to maximize bandwidth, and the MOSFETs and feedback resistor in the output stage sized for 50 matching.
[0096] According to an embodiment, a large 30 k feedback resistor was used in the first TIA stage. According to an embodiment, the MOSFETs are biased at the peak-.sub.MAX current density (J.sub.pfMAX=0.25 mA/m) by adjusting back gate 1400 voltages, V.sub.bgn and V.sub.bgp, to reduce noise and maximize gain. The simulated transimpedance gain, bandwidth, and equivalent input noise current density at 2 GHz for the embodiment changes from 104 dB, 12 GHZ, 0.83 pA/Hz to 112 dB, 11 GHz, 0.19 pA/Hz, respectively, as the temperature decreases from 300 K to 12 K, the lowest at which the circuit simulator still works.
[0097] According to an embodiment, the bandwidth of the TIA, 12 GHZ, is designed to cover DC to 4 Rabi frequency when the DQD gate is excited with a mm-wave signal of up to 20 mV.sub.pp in the 60-220 GHz range.
Readout Amplifier Measurements
[0098] FIG. 32 shows the measured S.sub.21 and S.sub.22 of the three types of DQD-with-TIA embodiments at 300 K, along with simulated Z.sub.21, S.sub.22, and equivalent input noise current (I.sub.n) of the TIA at 300 K and 12 K. Although, because of their small size and g.sub.m, the standalone DQDs have an S.sub.21 of 20 dB or less, the 10 n-MOS DQD with TIA achieved a maximum S.sub.21 of 18.9 dB and a 3 dB bandwidth of 7.5 GHz. The equivalent 10 p-MOS DQD with TIA readout circuit has an S.sub.21 of 13.5 dB and 7.5 GHz bandwidth, while the 1 p-MOS DQD circuit reached a maximum S.sub.21 of 8.89 dB with a 3 dB bandwidth of 8.5 GHz. In all three embodiments, S.sub.22 is better than 10 db up to 60 GHz. As in the transistor measurements of FIG. 24 and previous 3-stage readout TIA, the gain and bandwidth will improve at 2 K, while the output will remain matched.
[0099] The transimpedance gain, Z.sub.21, of the readout amplifier itself was obtained by applying a variable DC current, I.sub.source, through the V.sub.source terminal and measuring the output voltage of the TIA, V.sub.out, and its derivative, as shown in FIG. 33. The peak Z.sub.21 is 108 dB (251 k) at a current density of 0.25 mA/m, corresponding to the J.sub.pfMAX, as illustrated in the inset of FIG. 31. The output spectrum of the 1 p-DQD-with-TIA embodiment was measured with variable-amplitude sinusoidal signals in the 1 to 8 GHz range applied to the gate of the DQD. FIG. 34 shows that even at 110 dBm output power, the 4 GHz sinusoidal signal is visible above the noise floor. Based on the 251 k TIA gain, this corresponds to 3 pA.sub.rms current at the input of the TIA. FIG. 35 shows a comparison of the performance of the DQD-with-TIA embodiments to other state-of-the-art qubit readout amplifiers intended to operate at cryogenic temperatures.
[0100] FIGS. 37(a) and 37(b) show two spin manipulation and readout circuit embodiments. FIG. 37(a) shows monolithically integrated spin manipulation and readout circuit for two capacitively-coupled single-spin qubits. Spin manipulation circuit consists of input amplifier with 50 Ohm input matching and a bandwidth sufficiently high to encompass the spin excitation frequency in the 60-160 GHz range. Excitation frequency signal is on-off modulated before being applied to the gate of the qubits. On-off pulse widths as short as 20 ps are needed to accommodate pi/2 spin rotations with a Rabi frequency as high as 12.5 GHz. Readout amplifiers are connected to the drains of the qubits and can drive 50 Ohm.
[0101] FIG. 37(b) shows a monolithically integrated spin manipulation and readout circuit for a group of a double quantum dot qubit capacitively-coupled to a single-spin qubit. The third gate in the double quantum dot structure (G3) is intended to act as a taller confining barrier for the dot under gate 2. Spin manipulation and readout circuits are identical to those described for FIG. 37(a).
[0102] FIG. 38 shows a schematic of a back gate biasing circuit according to an embodiment. It enables the CMOS amplifiers and logic to be appropriately biased for the fastest and/or lowest noise performance over temperature and process. The desired current density bias is set through ibias in the right branch and the NMOS back gate voltage (vnback) is adjusted until voutn is half of the supply voltage (0.4V since in this case supply is 0.8V). Next, the PMOS back gate is adjusted until voutp is also half of the supply voltage. The back gate voltages can now be used to bias all other CMOS amplifiers and logic in the monolithically integrated quantum processor.
[0103] Various embodiments of the invention have been described in detail. Since changes in and or additions to the above-described best mode may be made without departing from the nature, spirit or scope of the invention, the invention is not to be limited to those details but only by the appended claims. Section headings herein are provided as organizational cues. These headings shall not limit or characterize the invention set out in the appended claims.
