Semiconductor device and method of driving the same

Abstract

To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed.

Claims

1. An X-ray system comprising: an X-ray generator configured to irradiate an object with an X-ray; a sensor portion configured to sense light; and a computer configured to process a signal which is generated in response to the light sensed by the sensor portion, wherein the sensor portion comprises a circuit including a transistor, a photoelectric conversion element over the transistor, a resin film over the photoelectric conversion element, wherein a channel forming region of the transistor is overlapped by the photoelectric conversion element.

2. The X-ray system according to claim 1, wherein the transistor is a p-channel transistor.

3. The X-ray system according to claim 1, wherein the transistor has no LDD region.

4. The X-ray system according to claim 1, wherein the photoelectric conversion element comprises a cathode electrode, a photoelectric conversion layer over the cathode electrode, and an anode electrode over the photoelectric conversion layer.

5. The X-ray system according to claim 1, wherein the light is the X-ray through the object.

6. The X-ray system according to claim 1, wherein the X-ray through the object is converted into the light by using a fluorescent material or a scintillator.

7. The X-ray system according to claim 1, wherein the resin film comprises polyimide, polyamide, polyimide amide, or acrylic.

8. An X-ray system comprising: an X-ray generator configured to irradiate an object with an X-ray; a sensor portion configured to sense light; and a computer configured to process a signal which is generated in response to the light sensed by the sensor portion, wherein the sensor portion comprises a circuit including a transistor, an organic resin film over the transistor, a photoelectric conversion element over the organic resin film, a resin film over the photoelectric conversion element, wherein a channel forming region of the transistor is overlapped by the photoelectric conversion element.

9. The X-ray system according to claim 8, wherein the transistor is a p-channel transistor.

10. The X-ray system according to claim 8, wherein the transistor has no LDD region.

11. The X-ray system according to claim 8, wherein the photoelectric conversion element comprises a cathode electrode, a photoelectric conversion layer over the cathode electrode, and an anode electrode over the photoelectric conversion layer.

12. The X-ray system according to claim 8, wherein the light is the X-ray through the object.

13. The X-ray system according to claim 8, wherein the X-ray through the object is converted into the light by using a fluorescent material or a scintillator.

14. The X-ray system according to claim 8, wherein the resin film comprises polyimide, polyamide, polyimide amide, or acrylic.

15. The X-ray system according to claim 8, wherein the organic resin film comprises polyimide, polyamide, acryl, benzocyclobutene.

16. The X-ray system according to claim 8, wherein the thickness of the organic resin film is 1 to 5 m.

17. An X-ray system comprising: an X-ray generator configured to irradiate an object with an X-ray; a sensor portion configured to sense light; and a computer configured to process a signal which is generated in response to the light sensed by the sensor portion, wherein the sensor portion comprises a circuit including a transistor, a photoelectric conversion element over the transistor, a polyimide film over the photoelectric conversion element, wherein a channel forming region of the transistor is overlapped by the photoelectric conversion element.

18. The X-ray system according to claim 17, wherein the transistor is a p-channel transistor.

19. The X-ray system according to claim 17, wherein the transistor has no LDD region.

20. The X-ray system according to claim 17, wherein the photoelectric conversion element comprises a cathode electrode, a photoelectric conversion layer over the cathode electrode, and an anode electrode over the photoelectric conversion layer.

21. The X-ray system according to claim 17, wherein the light is the X-ray through the object.

22. The X-ray system according to claim 17, wherein the X-ray through the object is converted into the light by using a fluorescent material or a scintillator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings:

(2) FIGS. 1A and 1B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(3) FIG. 2 is a diagram showing a circuit configuration of a pixel of a conventional passive sensor;

(4) FIG. 3 is a diagram showing a circuit configuration of a pixel of a conventional active sensor;

(5) FIG. 4 is a diagram showing a circuit configuration of a conventional source follower circuit;

(6) FIG. 5 is a diagram showing an electric current characteristic of a source follower circuit;

(7) FIG. 6 is a diagram showing an electric current characteristic of a source follower circuit;

(8) FIG. 7 is a diagram showing an input/output characteristic of a source follower circuit;

(9) FIGS. 8A and 8B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit;

(10) FIGS. 9A and 9B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit;

(11) FIG. 10 is a diagram showing a timing chart of an active sensor;

(12) FIGS. 11A and 11B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(13) FIGS. 12A and 12B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(14) FIGS. 13A and 13B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(15) FIGS. 14A and 14B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(16) FIGS. 15A and 15B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(17) FIGS. 16A and 16B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(18) FIGS. 17A and 17B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(19) FIGS. 18A and 18B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(20) FIGS. 19A and 19B are diagrams showing a circuit configuration and a timing chart, respectively, of a source follower circuit of the present invention;

(21) FIG. 20 is a block diagram of an area sensor of the present invention;

(22) FIG. 21 is a diagram showing a circuit configuration of a pixel of an active sensor of the present invention;

(23) FIG. 22 is a diagram showing a circuit configuration of a pixel of an active sensor of the present invention;

(24) FIG. 23 is a diagram showing a circuit configuration of a signal processing circuit of the present invention;

(25) FIG. 24 is a diagram showing a circuit configuration of a final output amplifying circuit signal of the present invention;

(26) FIG. 25 is a diagram showing a circuit configuration of a final output amplifying circuit signal of the present invention;

(27) FIG. 26 is a diagram showing a timing chart of an area sensor of the present invention;

(28) FIG. 27 is a diagram showing a timing chart of an area sensor of the present invention;

(29) FIG. 28 is a diagram showing a timing chart of an area sensor of the present invention;

(30) FIG. 29 is a diagram showing a circuit configuration of a signal processing circuit of the present invention;

(31) FIGS. 30A to 30D are diagrams showing manufacturing processes of an image sensor of the present invention;

(32) FIGS. 31A to 31D are diagrams showing manufacturing processes of an image sensor of the present invention;

(33) FIGS. 32A to 32C are diagrams showing manufacturing processes of an image sensor of the present invention;

(34) FIGS. 33A and 33B are diagrams showing manufacturing processes of an image sensor of the present invention;

(35) FIGS. 34A and 34B are diagrams showing electronic equipments using the image sensor of the present invention;

(36) FIG. 35 is a diagram showing an electronic equipment using the image sensor of the present invention;

(37) FIG. 36 is a diagram showing an electronic equipment using the image sensor of the present invention; and

(38) FIG. 37 is a diagram showing an electronic equipment using the image sensor of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment Mode 1

(39) A typical embodiment mode of the present invention is shown in the following.

(40) Shown in FIGS. 11A and 11B is an example of a pre-discharge implementation method. FIG. 11A is a diagram showing a circuit configuration of the pre-discharge implementation method, and FIG. 11B is a diagram showing a signal timing chart thereof. In FIGS. 11A and 11B, pre-discharge is performed by arranging an exclusive electric discharging transistor 1108. FIGS. 11A and 11B are diagrams illustrating an example of a case in which an N channel transistor is used to construct the source follower circuit.

(41) An electric potential of a gate terminal of an amplifying transistor 1101 (input terminal 1105) becomes an input electric potential Vin. This input electric potential Vin corresponds to an electric potential of an N channel side terminal of a photo diode. A drain terminal of the amplifying transistor 1101 is connected to an amplifying side power source line 1103, and a source terminal thereof is connected to a drain terminal of a biasing transistor 1102. The source terminal of the amplifying transistor 1101 serves as an output terminal 1107 and an electric potential thereof becomes an output electric potential Vout. A bias electric potential Vb is applied to a gate terminal of the biasing transistor 1102. A source terminal of the biasing transistor 1102 is connected to a biasing side power source line 1104. A source terminal and a drain terminal of the electric discharging transistor 1108 are connected to the output terminal 1107 of the source follower circuit (source terminal of the amplifying transistor 1101) and an electric discharging power source line 1109.

(42) As shown in FIG. 11B, when the electric discharging transistor 1108 is in conductive, the electric potential of the output terminal 1107 becomes the electric potential of the electric discharging power source line 1109 to thereby carry out pre-discharge. During a pre-discharge period, a large electric current can be caused to flow to the electric discharging transistor 1108 because the gate electric potential of the electric discharging transistor 1108 is large. As a result, the output electric potential Vout can be rapidly lowered, whereby the pre-discharge period is shortened. In this method, the bias electric potential Vb may be equivalent to that of the prior art, or may be large.

(43) An actual signal is output after the pre-discharge. In that case, since the source follower circuit is in the Vout<VinVb state, a large electric current flows to the amplifying transistor 1101 as the voltage between the gate and the source thereof is large. Consequently, a signal writing-in can be done in a short time.

(44) Taking the input/output relationship of Vout=VinVb into consideration, it is appropriate to make the bias electric potential Vb as low as possible when outputting the output electric potential Vout in order to increase the output electric potential Vout. However, the biasing transistor 1102 must be in conductive. In other words, the biasing transistor 1102 must be operable in the saturated region and a value in which a fixed electric current can flow therein. Therefore, other than during the pre-discharge period, an optimum value of an absolute value of a bias signal electric potential (voltage between the gate and the source of the biasing transistor) is an electric potential that is slightly higher than an absolute value of a threshold voltage of the biasing transistor 1102.

(45) Further, when the bias electric potential Vb is low, the operating region in which the input/output relationship is linear can be widened because the biasing transistor 1102 can readily operate in the saturated region.

(46) Thus, from the above consequences, it is possible to prevent the signal writing-in time from becoming long, and enlarging the amplitude of the output electric potential and widening the operating region in which the input/output relationship is linear can be realized at the same time.

(47) With regard to the polarity of the electric discharging transistor 1108, the polarity thereof may be similar to those of the amplifying transistor 1101 and the biasing transistor 1102, that is, in FIGS. 11A and 11B, an N channel type. The reason for this resides in that when making the electric discharging transistor 1108 into a conductive, if an N channel type is used to form the electric discharging transistor 1108, then the voltage between the gate and the source thereof can large because the electric potential of the electric discharging power source line 1109 is low. If the polarity of the electric discharging transistor 1108 is different from that of the amplifying transistor 1101 and that of the biasing transistor 1102, that is, in FIGS. 11A and 11B, if a P channel type is used to form the electric discharging transistor 1108, it is necessary to apply an extremely low electric potential to the gate terminal of the electric discharging transistor 1108. In other words, it is necessary to apply an electric potential that is lower than the electric potential of the biasing side power source line 1104. Therefore, from the above explanation, it is desirable to make the polarity of the electric discharging transistor 1108 similar to that of the amplifying transistor 1101 and that of the biasing transistor 1102.

(48) Note that in FIGS. 11A and 11B, a plurality of electric discharging transistors 1108N may be used, in which case transistors of both polarities may be used.

(49) Next, the electric potential of the electric discharging power source line 1109 will be explained. To perform pre-discharge is to set the state of the circuit to Vout<VinVb. Therefore, the electric potential of the electric discharging power source line 1109 has to be set to a low electric potential. The electric potential thereof may be lower than the electric potential of the biasing side power source line 1104. However, since the electric potential operation range of the output terminal 1107 is between the electric potential of the amplifying side power source line 1103 and the electric potential of the biasing side power source line 1104. Even if the electric potential of the electric discharging power source line 1109 is made lower than the electric potential of the biasing side power source line 1104, no improvement is obtained. In the case where the electric potential of the electric discharging power source line 1109 is higher than the electric potential of the biasing side power source line 1104, the state of Vout<VinVb may not be attained if the electric potential of the electric discharging power source line 1109 is made higher than the electric potential of the bias signal line 1106. Thus, from the above explanation, it is necessary that the electric potential of the electric discharging power source line 1109 be set higher than the electric potential of the biasing side power source line 1104 but lower than the electric potential of the bias signal line 1106. Normally, the electric potential of the electric discharging power source line 1109 may be set equivalent to that of the biasing side power source line 1104. Therefore, the electric discharging power source line 1109 and the biasing side power source line 1104 may be connected.

(50) When employing the circuit of FIGS. 11A and 11B in practice, the load capacitance is often connected to the output terminal 1107 to thereby accumulate the signals therein. The diagram of a circuit configuration of a case in which the load capacitance is connected to the circuit illustrated in FIGS. 11A and 11B is shown in FIGS. 1A and 1B. One terminal of a load capacitance 110 is connected to an output terminal 107 whereas the other terminal thereof is connected to a load capacitance power source line 111. The electric potential value of the load capacitance power source line 111 may be an arbitrary value. Normally the electric potential value thereof is often set equivalent to the electric potential of a biasing side power source line 104. Therefore, the load capacitance power source line 111 and the biasing side power source line 104 may be connected. The load capacitance power source line 111 may also be connected with an amplifying side power source line 103. Thus, from the above explanation, 2 lines or more from among the load capacitance power source line 111, the biasing side power source line 104, and the electric discharging power source line 109 may be connected to each other. A circuit configuration and a timing chart of a situation where 3 lines are connected to each other is shown in FIGS. 12A and 12B.

(51) Explanation has been given so far for the case of using an N channel transistor to construct the source follower circuit. However, it is also possible to use a P channel transistor to construct the source follower circuit. Thus, a drawing of circuit configuration using the P channel transistor to construct the source follower circuit will be shown next. The case of using the P channel transistor in the circuit of FIGS. 11A and 11B will be shown in FIGS. 13A and 13B, and a case of using the P channel transistor in the circuit of FIGS. 1A and 1B will be shown in FIGS. 14A and 14B. Shown in FIGS. 15A and 15B is a case of using the P channel transistor in the circuit of FIGS. 12A and 12B. When the N channel transistor is used to construct the source follower circuit, the electric potential of the amplifying side power source line 1103 is higher than the biasing side power source line 1103. However, when the P channel transistor is used to construct the source follower circuit, the electric potential of an amplifying side power source line 1303 is lower than the electric potential of a biasing side power source line 1304.

(52) In some cases, a plurality of source follower circuits may be arranged and output terminals may be connected to each other and arranged therein. At that point, there is a necessity to output a signal only from one source follower circuit. Therefore, a switch may be provided to stop the flow of an electric current. The diagrams of a circuit configuration and a timing chart of a case where a transferring transistor 1612 is provided between an output terminal 1607 and a load capacitance 1610 in the circuit of FIGS. 1A and 1B is illustrated in FIGS. 16A and 16B. In the circuit of FIGS. 16A and 16B, a switching transistor 1713 is provided between an output terminal 1707 and an amplifying transistor 1701, and the circuit configuration and timing chart of this case is illustrated in FIGS. 17A and 17B. In FIGS. 16A and 16B or in FIGS. 17A and 17B, at least one element from the amplifying transistor, the biasing transistor, and the selecting switch may be used to construct a unit pixel.

(53) Note that the switch for stopping the flow of an electric current may be formed of either the N channel transistor or the P channel transistor. In addition, a plurality of switches may be provided and the connecting method thereof may be in series or in parallel.

Embodiment Mode 2

(54) Next, an embodiment mode of a case in which a method of performing the pre-discharge is different from that of Embodiment Mode 1 is shown in FIGS. 18A and 18B. FIG. 18A is a diagram showing a circuit configuration, and FIG. 18B is a diagram showing a signal timing chart. In FIGS. 18A and 18B, pre-discharge is performed by making the bias electric potential Vb large. Shown in FIGS. 18A and 18B is an example of a case using an N channel transistor to construct the source follower circuit.

(55) An electric potential of a gate terminal of an amplifying transistor 1801 becomes the input electric potential Vin. This input electric potential Vin corresponds to the electric potential of the N channel side terminal of the photo diode. A drain terminal of the amplifying transistor 1801 is connected to an amplifying side power source line 1803, and a source terminal thereof is connected to a drain terminal of a biasing transistor 1802. The source terminal of the amplifying transistor 1801 serves as an output terminal 1807 and an electric potential thereof becomes the output electric potential Vout. The bias electric potential Vb is applied to a gate terminal of the biasing transistor 1802. A source terminal of the biasing transistor 1802 is connected to a biasing side power source line 1804.

(56) The bias electric potential Vb is increased during the pre-discharge period. As a result, the electric potential of the output terminal 1807 becomes the electric potential of a biasing side power source line 1804 to thereby carry out pre-discharge. During the pre-discharge period, a large electric current can be caused to flow to the biasing transistor 1802 because the gate electric potential of the biasing transistor 1802, that is, the bias electric potential Vb is large. Consequently, the output electric potential Vout can be rapidly lowered, whereby the pre-discharge period is shortened.

(57) An actual signal is output after the pre-discharge. In that case, since the source follower circuit is in the Vout<VinVb state, a large electric current flows to the amplifying transistor 1801 because the electric potential between the gate and the source thereof is large. Consequently, the signal writing-in can be done in a short time.

(58) Taking the input/output relationship of Vout=VinVb into consideration, it is appropriate to make the bias electric potential Vb as low as possible when outputting the output electric potential Vout in order to increase the output electric potential Vout. However, the biasing transistor 1802 must be in conductive. In other words, the biasing transistor 1802 must be operable in the saturated region and set at a value in which a fixed electric current can flow therein. Therefore, other than during the pre-discharge period, an optimum value of an absolute value of a bias signal electric potential (voltage between the gate and the source of the biasing transistor) is an electric potential that is slightly higher than an absolute value of a threshold voltage of the biasing transistor 1802.

(59) Further, when the bias electric potential Vb is low, the operating region in which the input/output relationship is linear can be widened because the biasing transistor 1802 can readily operate in the saturated region.

(60) Thus, from the above consequences, it is possible to prevent the signal writing-in time from becoming long, and enlarging the amplitude of the output electric potential while widening the operating region in which the input/output relationship is linear can be realized at the same time.

(61) Regarding the electric potential value of the bias electric potential Vb during pre-discharge, it is preferable to make the electric potential value thereof as high as possible in order to perform discharge. Therefore, increasing the bias electric potential Vb until it is as high as the highest electric potential in the circuit, for example, the amplifying side power source line 1803, is appropriate.

(62) In the prior art, a fixed electric potential was applied to the bias signal line 1806. In Embodiment Mode 2, the bias electric potential Vb changes during pre-discharge. Therefore, a signal generating device for changing the bias electric potential Vb is connected to the bias signal line 1806.

(63) The explanation so far has been about the case of using an N channel transistor to construct the source follower circuit. However, it is also possible to use a P channel transistor to construct the source follower circuit. Thus, a drawing where the P channel transistor is used to construct the source follower circuit is shown in FIGS. 19A and 19B. Similar to Embodiment Mode 1, the relationship concerning the size of the electric potential of the amplifying side power source line and the electric potential of the biasing side power source line is different between the case of using the N channel transistor to construct the source follower circuit and the case of using the P channel transistor to construct the source follower circuit.

(64) Note that similar to Embodiment Mode 1, the provision of a load capacitance and a selecting switch is also possible in Embodiment Mode 2.

Embodiment 1

(65) An embodiment of a case in which pre-discharge is performed by employing an electric discharging transistor in an area sensor that has pixels arranged two-dimensional therein and incorporated with driver circuits in the periphery thereof will be explained next. The entire circuit configuration is illustrated in FIG. 20. First, there is provided a pixel arrangement portion 2005 having pixels arranged two-dimensional therein. Driver circuits for driving a gate signal line and a reset signal line of each of the pixels is provided on the left and right sides of the pixel arrangement portion 2005. In FIG. 20, a gate signal line driver circuit 2006 is provided on the left side and a reset signal line driver circuit 2007 is provided on the right side. Driver circuits such as a signal processing circuit are arranged above the pixel arrangement portion 2005. A biasing circuit 2003 is arranged above the pixel arrangement portion 2005 in FIG. 20. The biasing circuit 2003 and the amplifying transistors of the respective pixels form the source follower circuit. A sample hold and signal processing circuit 2002 are arranged above the biasing circuit 2003. Circuits for maintaining signals for a time, for performing analog/digital conversion, or for reducing noise are arranged here. A signal output line driver circuit 2001 is arranged above the sample hold and signal processing circuit 2002. The signal output line driver circuit 2001 outputs signals for outputting, in sequence, the signals that have been temporarily preserved. Then, before the signals are output to the outside, a final output amplifying circuit 2004 is arranged thereto. Before the signals, which are sequentially output hereto by the sample hold and the signal processing circuit 2002 and the signal output line driver circuit 2001, are output to the outside, the signals are amplified by the final output amplifying circuit 2004. Therefore, although unnecessary when the signals are not amplified, in practice it is often provided.

(66) Next, the circuit configuration of the respective portions is illustrated. First, taking an ith line jth row pixel portion circuit 2008 as an example from the interior of the pixel arrangement portion 2005 having pixels arranged in two-dimensional, the circuit configuration thereof is shown in FIG. 21. In FIG. 21, the ith line jth row pixel portion circuit 2008 is composed of a P channel resetting transistor 2107, a P channel switching transistor. 0.2101, an N channel amplifying transistor 2106, and a photoelectric conversion element (here, it is the most typical photo diode 2104). A P channel side terminal of the photo diode 2104 is connected to a power source standard line 2112, and an N channel side terminal thereof is connected to a gate terminal of the amplifying transistor 2106. An ith line resetting signal line 2105 is connected to a gate terminal of the resetting transistor 2107. A source terminal and a drain terminal of the resetting transistor 2107 are connected to a jth row power source line 2109 and to the gate terminal of the amplifying transistor 2106. A gate terminal of the switching transistor 2101 is connected to an ith line gate signal line 2102, and a source terminal and a drain terminal thereof are connected to the jth row power source line 2109 and to the gate terminal of the amplifying transistor 2106. A source terminal and a drain terminal of the amplifying transistor 2106 are connected to a jth row signal output line 2103 and to the switching transistor 2101. As in the prior art, the ith line gate signal line 2102 and the ith line resetting signal line 2105 have their wirings extended in the horizontal direction.

(67) If the wirings of this circuit configuration is made corresponding to the wirings of the source follower circuit, the jth row power source line 2109 corresponds to the amplifying side power source line 1103, the power source standard line 2112 corresponds to the biasing side power source line 1104, and the output terminal 1107 corresponds to the jth row signal output line 2103.

(68) In FIG. 21, the resetting transistor 2107 is formed of the P channel type. However, the resetting transistor 2107 may be formed of the N channel type. Note that, the voltage between the gate and the source of the resetting transistor 2107 cannot be large during the resetting operation in the case the N channel type is used to form the resetting transistor 2107. Accordingly, the resetting transistor will operate in the saturated region, whereby the photo diode 2104 cannot be charged sufficiently. As a result, though the resetting transistor 2107 will operate even if it is formed of the N channel type, it is desirable to use a P channel type.

(69) As for the switching transistor 2101, it is arranged between the ith line power source line 2109 and the amplifying transistor 2106, and is desirably formed of the P channel type as well. However, similar to the prior art, since the switching transistor can operate even if it is formed of N channel type, the N channel type may be used. The switching transistor 2101 may also be provided between the jth row signal output line 2103 and the amplifying transistor 2106. However, because there is difficulty in outputting a signal correctly, the switching transistor 2101 is arranged between the ith line power source line 2109 and the amplifying transistor 2106, and is desirably formed of the P channel type.

(70) As for the amplifying transistor 2106 in FIG. 21, the N channel type is used. Nonetheless, the P channel type may be used. However, in the case of using the P channel type, it is necessary to change the connection method of the circuit in order to combine the amplifying transistor with the biasing transistor to thereby operate as the source follower circuit. That is, in the circuit configuration of FIG. 21, the amplifying transistor 2106 will not operate by simply changing the polarity thereof.

(71) Then, an example of a circuit configuration when a P channel type of amplifying transistor is used is shown in FIG. 22. The differences between this circuit configuration and that of FIG. 21 is that the polarity of an amplifying transistor 2206 is the P channel type, the direction in which the photo diode faces is inverted, and the power source line and the power source standard line are changed. In the case of using the P channel type in the amplifying transistor, it is necessary to use the P channel type in the biasing transistor also. The reason for this resides in that there is a necessity to operate the biasing transistor as a fixed electric current source. Therefore, a description of a biasing transistor 2211 is also made in FIG. 22 for reference. The ith line jth row pixel portion circuit 2008 illustrated in FIG. 22 is composed of an N channel type resetting transistor 2207, an N channel type switching transistor 2201, a P channel type amplifying transistor 2206, and a photoelectric conversion element (here, it is the most typical photo diode 2204). An N channel side terminal of the photo diode 2204 is connected to a power source line 2209, and a P channel side terminal thereof is connected to agate terminal of an amplifying transistor 2206. An ith line resetting signal line 2205 is connected to a gate terminal of the resetting transistor 2207. A source terminal and a drain terminal of the resetting transistor 2207 are connected to a jth row power source standard line 2212 and to the gate terminal of the amplifying transistor 2206. A gate terminal of the switching transistor 2201 is connected to an ith line gate signal line 2202, and a source terminal and a drain terminal thereof are connected to the jth row power source standard line 2212 and the amplifying transistor 2206. A source terminal and a drain terminal of the amplifying transistor 2206 are connected to a jth row signal output line 2203 and to the switching transistor 2201. A biasing signal line 2210 is connected to a gate terminal of the biasing transistor 2211, and a source terminal and a gate terminal thereof are connected to the jth row signal output line 2203 and to the power source line 2209.

(72) When the wirings of this circuit configuration is made corresponding to the wirings of the source follower circuit, then the jth row power source standard line 2212 corresponds to the amplifying side power source line 1803, the power source line 2109 corresponds to the biasing side power source line 1804, and the output terminal 1807 corresponds to the jth row signal output line 2203.

(73) In FIG. 22, the N channel type is used for the resetting transistor 2207. However, the resetting transistor 2207 may also be formed of the P channel type. However, the voltage between the gate and the source of the resetting transistor 2207 cannot be large during the resetting operation in the case where the P channel type is used to form the resetting transistor 2207. Accordingly, the resetting transistor will operate in the saturated region, whereby the photo diode 2204 cannot be charged sufficiently. As a result, though the resetting transistor 2207 will operate even if the P channel type is used, it is desirable to use the N channel type.

(74) As for the switching transistor 2201 in FIG. 22, it is arranged between the jth row power source standard line 2212 and the amplifying transistor 2206, and desirably is formed of N channel type as well. However, since the switching transistor can operate even if it is formed of the P channel type, the P channel type may also be used. The switching transistor 2201 may also be provided between the jth row signal output line 2203 and the amplifying transistor 2206. However, because there is difficulty in outputting a signal correctly, the switching transistor 2201 is arranged between the jth row power source standard line 2212 and the amplifying transistor 2206, and is desirably formed by using the N channel type.

(75) Thus, as is apparent from the comparison between the circuit configurations of FIGS. 21 and 22, when the polarity of the amplifying transistors is different, the optimal transistor structure also differs.

(76) Next, the circuit configuration of a jth row peripheral portion circuit 2009 taken as an exemplary row of circuits from inside the biasing circuit 2003 and the sample hold and signal processing circuit 2002 is shown in FIG. 23. A biasing transistor 2311 is arranged in the biasing circuit 2003. The polarity thereof is the same as the polarity of the amplifying transistor of the respective pixels. Therefore, if the amplifying transistor of the pixel is the N channel type, the biasing transistor is also the N channel type. In FIG. 23, the biasing transistor 2311 is the N channel type. A gate terminal of the biasing transistor 2311 is connected to a biasing signal line 2310, and a source terminal and a drain terminal thereof are connected to a jth row signal output line 2303 and a power source standard line 2312 (when the biasing transistor is the P channel type, the power source line is used in place of the power source standard line). The biasing transistor 2311 and the amplifying transistors of the respective pixels, operates as the source follower circuit. A gate terminal of a transferring transistor 2313 is connected to a transfer signal line 2314, and a source terminal and a drain terminal thereof are connected to a jth row signal output line 2303 and a load capacitance 2315. The transferring transistor is operated when transferring the electric potential of the signal output line 2303 to the load capacitance 2315. Therefore, a P channel type transferring transistor may be added and connected in a row to an N channel type transferring transistor 2314. The load capacitance 2315 is connected to the transferring transistor 2313 and the power source standard line 2312. The role of the load capacitance 2315 is to temporarily accumulate therein the signals output from the signal output line 2303. A gate terminal of an electric discharging transistor 2316 is connected to a pre-discharge signal line 2317, and a source terminal and a drain terminal thereof are connected to the load capacitance 2315 and the power source standard line 2312. Prior to inputting the electric potential of the signal output line 2303 to the load capacitance 2315, the electric discharging transistor 2316 operates to discharge the electric charges that have temporarily accumulated in the load capacitance 2315.

(77) Note that the analog/digital signal conversion circuit, the noise reduction circuit, etc. may also be arranged therein.

(78) A final selecting transistor 2319 is connected between the load capacitance 2315 and a final output line 2320. A source terminal and a drain terminal of the final selecting transistor 2319 are connected to the load capacitance 2315 and the final output line 2320, and a gate terminal thereof is connected to a jth row final selecting line 2318. The final selecting line will be scanned from the first row in sequence. Then the jth row final selecting line 2318 is selected, and when the final selecting transistor 2319 is turned into conductive, the electric potential of the load capacitance 2315 and that of the final output line 2320 become equivalent. As a result, the signals that have accumulated in the load capacitance 2315 can be output to the final output line 2320. However, if electric charges are accumulated in the final output line 2320 before outputting the signals to the final output line 2320, the electric potential when outputting the signals to the final output line 2320 will be adversely influenced by those electric charges. Therefore, the electric potential of the final output line 2320 must be initialized to a certain electric potential value before the signals are output to the final output line 2320. In FIG. 23, a final resetting transistor 2322 is arranged between the final output line 2320 and the power source standard line 2312. A gate terminal of the final resetting transistor 2322 is connected to a jth row final resetting line 2321. Prior to selecting the jth row final selecting line 2318, the jth row final resetting line 2321 is selected to thereby initialize the electric potential of the final output line 2320 and that of the power source standard line 2312. Thereafter, the jth row final selecting line 2318 is selected, whereby the signals that have accumulated in the load capacitance 2315 are output to the final output line 2320.

(79) The signals that will be output to the final output line 2320 may be withdrawn to the outside. However, because the signals are faint, the signals are frequently amplified before being withdrawn to the outside. As a circuit for carrying out the amplification of the signals, the circuit configuration of the final portion circuit 2010 is shown in FIG. 24. There are various kinds of circuits for amplifying the signals, such as an arithmetic amplifier. Any kind of circuit that can amplify the signals may be used. As the most simple circuit configuration, the source follower circuit is shown here. In FIG. 24, the N channel type is illustrated. Signals that are input to the final output amplifying circuit 2004 will be input to a final output line 2402. Signals are output from the first row in sequence from the final output line 2402. The signals are amplified by the final output amplifying circuit 2004 and then output to the outside. The final output line 2402 is connected to a gate terminal of a final output amplifier-amplifying transistor 2404. A drain terminal of the final output amplifier-amplifying transistor 2404 is connected a power source line 2404, and a source terminal thereof serves as an output terminal. A gate terminal of a final output amplifier-biasing transistor 2403 is connected to a final output amplifying bias signal line 2405, and a source terminal and a drain terminal thereof are connected to a power source standard line 2407 and a source terminal of the final output amplifier-amplifying transistor 2404.

(80) Shown in FIG. 25 is a circuit configuration of the source follower circuit when the P channel type is used. The difference from the circuit configuration of FIG. 24 is that the power source line and the power source standard line are reversed. A final output line 2502 is connected to a gate terminal of a final output amplifier-amplifying transistor 2504. A drain terminal of the final output amplifier-amplifying transistor 2504 is connected to a power source standard line 2507, and a source terminal thereof serves as an output terminal. A gate terminal of a final output amplifier-biasing transistor 2503 is connected to a final output amplifying bias signal line 2505. A source terminal and a drain terminal of the final output amplifier-biasing transistor 2503 are connected to a power source line 2506 and a source terminal of the final output amplifier-amplifying transistor 2504. A value of the electric potential of the final output amplifying bias signal line 2505 is different from that of the final output amplifying bias signal line 2405 in the case where the N channel type is used.

(81) In FIGS. 24 and 25, the source follower circuit is constructed of only one level. However, it may also be constructed of plural levels. For example, in the case of constructing the source follower circuit in 2 levels, the output terminal of the first level may be connected to the input terminal of the second level. In addition, in each of the levels, either the N channel type or the P channel type may be used.

(82) The gate signal line and reset signal line driver circuit 2006, the power source line driver circuit 2207, and a signal output line driver circuit AZ01 are circuits which simply output pulse signals. Therefore, implementation thereof can be made by employing a known technique.

(83) A timing chart of a signal will be explained next. The timing chart of the circuit shown in FIG. 20 is illustrated in FIG. 26. The reset signal line is scanned sequentially from the first line. For example, first an (i1)th line is selected, followed by an ith line, and then an (i+1)th line is selected. A period until the same line is selected again corresponds to a frame period. Similarly, the gate signal line is sequentially scanned from the first line. However, the timing to start scanning the gate signal line is later than the timing to start scanning the reset signal line. For instance, directing the attention to a pixel of the ith line, the ith line reset signal line is selected, and thereafter the ith line gate signal line is selected. When the ith line gate signal line is selected, a signal is output from the pixel of the ith line. A period from the time the pixel is reset until the signal is output becomes an accumulation time. During the accumulation time, electric charges generated by light are being accumulated in the photo diode. The timing to reset and the timing to output a signal are different in each line. Therefore, although the accumulation time of the pixels in all the lines are equivalent, the time that signals are accumulated therein is different.

(84) Next, the timing chart of a signal of FIG. 23 is shown in FIG. 27. Because the operation is repetitious, the time that the ith line gate signal line is selected will be taken as an example and observed. First, after the ith line gate signal line 2102 is selected, the pre-discharge signal line 2317 is selected to thereby make the electric discharging transistor 2316 in conductive. Subsequently, the transfer signal line 2314 is selected, whereby the signal of each of the rows from the ith line pixel is output to the load capacitance 2315 of every row.

(85) After accumulating the signals of all the pixels of the ith line in the load capacitance 2315 of every row, the signals of every row are sequentially output to the final output line 2320. During the period from the time the transfer signal line 2314 has become non-selective to the time the gate signal line is selected, all the rows are scanned by the signal output line driver circuit 2001. First, the final reset line of the first row is selected to thereby make the final resetting transistor 2322 into conductive, whereby the electric potential of the final output line 2320 is initialized to that of the power source standard line 2312. Thereafter, the final selecting line 2318 of the first row is selected and the final selecting transistor 2319 is turned into conductive to thereby output the signal in the load capacitance 2315 of the first row to the final output line 2320. Next, the final reset line of the second row is selected to thereby make the final resetting transistor 2322 into conductive, whereby the electric potential of the final output line 2320 is initialized to that of the power source standard line 2312. Thereafter, the final selecting line 2318 of the second row is selected and the final selecting transistor 2319 is turned into conductive to thereby output the signal in the load capacitance 2315 of the second row to the final output line 2320. The operation is repeated thereafter. Similarly, in the case of the jth line, the final reset line of the jth row is selected to thereby make the final resetting transistor 2322 into conductive, whereby the electric potential of the final output line 2320 is initialized to that of the power source standard line 2312. Thereafter, the final selecting line 2318 of the jth row is selected and the final selecting transistor 2319 is turned into conductive to thereby output the signal in the load capacitance 2315 of the jth row to the final output line 2320. Next, the final reset line of the (j+1)th row is selected and the final resetting transistor 2322 is turned into conductive, whereby the electric potential of the final output line 2320 is initialized to that of the power source standard line 2312. Thereafter, the final selecting line 2318 of the (j+1)th row is selected and the final selecting transistor 2319 is turned into conductive to thereby output the signal in the load capacitance 2315 of the (j+1)th row to the final output line 2320. The same operation is repeated thereafter to sequentially output all the signals to the final output line. During this operation, the bias signal line 2310 is fixed. The signals output to the final output line 2320 are amplified by the final output amplifying circuit 2004 and then output to the outside.

(86) Next, the (i+1)th line gate signal line is selected. The same operation as performed when the ith line gate signal line was selected will be performed. Then, the gate signal line of the next line will be selected further and the same operation will be repeated.

(87) The electric potential of the bias signal line 2310 will be explained here. In FIG. 23, a plural number of the biasing transistor 2311 is provided. Therefore, even if there is a fluctuation in the threshold voltages of the plural number of the biasing transistor 2311, all the biasing transistors 2311 must be in conductive. As a result, it is necessary to make the absolute value of the voltage between the gate and the source of the biasing transistor equivalent to the minimum value of the absolute value of the voltage between the gate and the source thereof in order to turn all the biasing transistors into conductive.

(88) Note that as for the sensor portion in which photoelectric conversion is performed, other than the usual PN type of photo diode, a PIN type diode, an avalanche diode, an NPN incorporated diode, a Schottky diode, an X-ray photo conductor, and a sensor for infrared rays or the like may be used. In addition, X-rays may be converted into light by using a fluorescent material or a scintillator and thereafter read the light that has been converted.

(89) As explained so far, the photoelectric conversion element is often connected to the input terminal of the source follower circuit. However, a switch may be sandwiched therebetween like a photo gate type, or the signal, after it has been processed so that it is a logarithmic value of light density, may be input to the input terminal, like a logarithm conversion type.

(90) Although the area sensor having pixels arranged in two-dimensional therein was explained in Embodiment 1, a line sensor having pixels arrange in one-dimensional can also be realized.

Embodiment 2

(91) In Embodiment 2, a case in which pre-discharge is performed by controlling a bias signal line in an area sensor that has pixels arranged in two-dimensional therein and incorporated with driver circuits in the periphery thereof will be explained next. The Embodiment 2 is different from Embodiment 1 only with respect to a portion of the circuit configuration (FIG. 23) and a portion of the signal timing chart (FIG. 27). Therefore, a circuit configuration thereof corresponding to that of FIG. 23 is shown in FIG. 29, and a timing chart of a signal thereof corresponding to that of FIG. 27 is shown in FIG. 28.

(92) The circuit configuration of FIG. 29 is one in which the electric discharging transistor 2316 and the pre-discharge signal line 2317 are removed from the circuit configuration of FIG. 23.

(93) Next, the timing chart of a signal in FIG. 29 is shown in FIG. 28. Because the operation is repetitious, the case in which the ith line gate signal line is selected will be taken as an example and observed. First, after the ith line gate signal line 2102 is selected, the electric potential of a bias signal line 2910 and that of a transferring transistor 2913 are raised to thereby perform pre-discharge. Then the electric potential of the bias signal line 2910 is returned to its original value, whereby the signal of each of the rows from the ith line pixels is output to a load capacitance 2915 of every row. The signal of each of the rows is sequentially output to a final output line 2920 after the signals of all the ith line pixels have accumulated in the load capacitance 2915 of every row.

(94) Note that in Embodiment 2, the bias electric potential Vb changes during pre-discharge. Therefore, a signal generating device for changing the bias electric potential Vb may be connected to the bias signal line 2910.

Embodiment 3

(95) A method of manufacturing a sensor portion using TFT on the glass of this invention is explained using FIGS. 30 to 33.

(96) First, as shown in FIG. 30A, a base film 201 is formed to a thickness of 300 nm on a glass substrate 200. A silicon oxinitride film is laminated as the base film 201 in Embodiment 3. At this point, it is appropriate to set the nitrogen concentration to between 10 and 25 wt % in the film contacting the glass substrate 200. In addition, it is effective that the base film 201 has a thermal radiation effect, and a DLC (diamond-like carbon) film may also be provided.

(97) Next, an amorphous silicon film (not shown in the figure) is formed with a thickness of 50 nm on the base film 201 by a known deposition method. Note that it is not necessary to limit to the amorphous silicon film, and a semiconductor film containing an amorphous structure (including a microcrystalline semiconductor film) may be used. In addition, a compound semiconductor film containing an amorphous structure, such as an amorphous silicon germanium film, may also be used. Further, the film thickness may be made from 20 to 100 nm.

(98) The amorphous silicon film is then crystallized by a known technique, forming a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 202. There are thermal crystallization using an electric furnace, laser annealing crystallization using a laser light, and lamp annealing crystallization using an infrared light as known crystallization methods. Crystallization is performed in Embodiment 3 using an excimer laser light, which uses XeCl gas.

(99) Note that pulse emission excimer laser light formed into a linear shape is used in Embodiment 3, but a rectangular shape may also be used. Continuous emission type argon laser light and continuous emission type excimer laser light can also be used.

(100) In this embodiment, although the crystalline silicon film is used as the active layer of the TFT, it is also possible to use an amorphous silicon film as the active layer.

(101) Note that it is effective to form the active layer of the transistor for reset, in which there is a necessity to reduce the off current, by the amorphous silicon film, and to form the active layer of the transistor for amplification by the crystalline silicon film. Electric current flows with difficulty in the amorphous silicon film because the carrier mobility is low, and the off current does not easily flow. In other words, the most can be made of the advantages of both the amorphous silicon film, through which current does not flow easily, and the crystalline silicon film, through which current easily flows.

(102) Next, as shown in FIG. 30B, a protective film 203 is formed on the crystalline silicon film 202 with a silicon oxide film having a thickness of 130 nm. This thickness may be chosen within the range of 100 to 200 nm (preferably between 130 and 170 nm). Furthermore, another films such as insulating films containing silicon may also be used. The protective film 203 is formed so that the crystalline silicon film is not directly exposed to plasma during addition of an impurity, and so that it is possible to have delicate concentration control of the impurity.

(103) Resist masks 204a, 204b, and 204c are then formed on the protective film 203, and an impurity element, which imparts n-type conductivity (hereafter referred to as an n-type impurity element), is added through the protective film 203. Note that elements residing in periodic table group 15 are generally used as the n-type impurity element, and typically phosphorous or arsenic can be used. Note that a plasma doping method is used, in which phosphine (PH.sub.3) is plasma-excited without separation of mass, and phosphorous is added at a concentration of 110.sup.18 atoms/cm.sup.3 in Embodiment 3. An ion implantation method, in which separation of mass is performed, may also be used, of course.

(104) The dose amount is regulated such that the n-type impurity element is contained in n-type impurity regions (b) 205a, 205b thus formed by this process, at a concentration of 210.sup.16 to 510.sup.19 atoms/cm.sup.3 (typically between 510.sup.17 and 510.sup.18 atoms/cm.sup.3).

(105) Next, as shown in FIG. 30C, the protective film 203 and the resist masks 204a, 204b, and 204c are removed, and an activation of the added n-type impurity elements is performed. A known technique of activation may be used as the means of activation, but activation is done in Embodiment 3 by irradiation of excimer laser light (laser annealing). Of course, a pulse emission excimer laser and a continuous emission excimer laser may both, be used, and it is not necessary to place any limits on the use of excimer laser light. The goal is the activation of the added impurity element, and it is preferable that irradiation is performed at an energy level at which the crystalline silicon film does not melt. Note that the laser irradiation may also be performed with the protective film 203 in place.

(106) The activation of impurity elements by heat treatment (furnace annealing) may also be performed along with activation of the impurity element by laser light. When activation is performed by heat treatment, considering the heat resistance of the substrate, it is good to perform heat treatment at about 450 to 550 C.

(107) A boundary portion (connecting portion) with end portions of the n-type impurity regions (b) 205a, 205b, namely regions, in which the n-type impurity element is not added, on the periphery of the n-type impurity regions (b) 205a, 205b, is delineated by this process. This means that, at the point when the TFTs are later completed, extremely good connecting portion can be formed between LDD regions and channel forming regions.

(108) Unnecessary portions of the crystalline silicon film are removed next, as shown in FIG. 30D, and island-shape semiconductor films (hereinafter referred to as active layers) 206 to 210 are formed.

(109) Then, as shown in FIG. 31A, a gate insulating film 211 is formed, covering the active layers 206 to 210. An insulating film containing silicon and with a thickness of 10 to 200 nm, preferably between 50 and 150 nm, may be used as the gate insulating film 211. A single layer structure or a lamination structure may be used. A 110 nm thick silicon oxinitride film is used in Embodiment 3.

(110) Thereafter, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 212 to 216. In Embodiment 3, the gate electrodes and wirings (hereinafter referred to as gate wirings) electrically connected to the gate electrodes for providing conductive paths are formed of the same materials. Of course, the gate electrode and the gate wiring may be formed of different materials from each other. More specifically, the gate wirings are made of a material having a lower resistivity than the gate electrodes. This is because a material enabling fine processing is used for the gate electrodes, while the gate wirings are formed of a material that can provide a smaller wiring resistance but is not suitable for fine processing. The wiring resistance of the gate wiring can be made extremely small by using this type of structure, and therefore a sensor portion having a large surface area can be formed. Namely, the above described pixel structure is extremely effective when an area sensor with a sensor portion having a screen size of a 10 inch diagonal or larger (in addition, a 30 inch or larger diagonal) is realized.

(111) Although the gate electrode can be made of a single-layered conductive film, it is preferable to form a lamination film with two layers or three layers, if necessary. Any known conductive films can be used for the gate electrodes 212 to 216.

(112) Typically, it is possible to use a film made of an element selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), a film of nitride of the above element (typically a tantalum nitride film, tungsten nitride film, or titanium nitride film), an alloy film of combination of the above elements (typically MoW alloy or MoTa alloy), or a silicide film of the above element (typically a tungsten silicide film or titanium silicide film). Of course, the films may be used as a single layer or a laminate layer.

(113) In Embodiment 3, a laminate film of a tungsten nitride (WN) film having a thickness of 30 nm and a tungsten (W) film having a thickness of 370 nm is used. This may be formed by sputtering. When an inert gas such as Xe or Ne is added as a sputtering gas, film peeling due to stress can be prevented.

(114) The gate electrodes 213 and 216 are respectively formed at this time so as to overlap a portion of the n-type impurity regions (b) 205a and 205b through the gate insulating film 211. This overlapping portion later becomes an LDD region overlapping the gate electrode.

(115) Next, an n-type impurity element (phosphorous is used in Embodiment 3) is added in a self-aligning manner with the gate electrodes 212 to 216 as masks, as shown in FIG. 31B. The addition is regulated such that phosphorous is added to n-type impurity regions (c) 217 to 224 thus formed at a concentration of 1/10 to that of the n-type impurity regions (b) 205a and 205b (typically between and ). Specifically, a concentration of 110.sup.16 to 510.sup.18 atoms/cm.sup.3 (typically 310.sup.17 to 310.sup.18 atoms/cm.sup.3) is preferable.

(116) Resist masks 225a to 225c are formed next, with a shape covering the gate electrodes 212, 214 and 215, as shown in FIG. 31C, and an n-type impurity element (phosphorous is used in Embodiment 3) is added, forming impurity regions (a) 226 to 233 containing phosphorous at high concentration. Ion doping using phosphine (PH.sub.3) is also performed here, and the phosphorous concentration of these regions is regulated so as to be set to from 110.sup.20 to 110.sup.21 atoms/cm.sup.3 (typically between 210.sup.20 and 510.sup.21 atoms/cm.sup.3).

(117) A source region or a drain region of the n-channel TFT is formed by this process, and in the n-channel TFT, a portion of the n-type impurity regions (c) 217, 218, 222, and 223 formed by the process of FIG. 31B is remained. These remaining regions correspond to LDD regions.

(118) Next, as shown in FIG. 31D, the resist masks 225a to 225c are removed, and new resist masks 234a and 234b are formed. A p-type impurity element (boron is used in Embodiment 3) is then added, forming p-type impurity regions 235 and 236 containing boron at high concentration. Boron is added here at a concentration of 310.sup.20 to 310.sup.21 atoms/cm.sup.3 (typically between 510.sup.20 and 110.sup.21 atoms/cm.sup.3) by ion doping using diborane (B.sub.2H.sub.6).

(119) Note that phosphorous has already been added to the impurity regions 235 and 236 at a concentration of 110.sup.20 to 110.sup.21 atoms/cm.sup.3, but boron is added here at a concentration of at least 3 times or more that of the phosphorous. Therefore, the n-type impurity regions already formed completely invert to p-type, and function as p-type impurity regions.

(120) Next, after removing the resist masks 234a and 234b, the n-type or p-type impurity elements added to the active layer at respective concentrations are activated. Furnace annealing, laser annealing or lamp annealing can be used as a means of activation. In Embodiment 3, heat treatment is performed for 4 hours at 550 C. in a nitrogen atmosphere in an electric furnace.

(121) At this time, it is important to eliminate oxygen from the surrounding atmosphere as much as possible. This is because an exposed surface of the gate electrode is oxidized, which results in an increased resistance if only a small amount of oxygen exists. Accordingly, the oxygen concentration in the surrounding atmosphere for the activation process is set at 1 ppm or less, preferably at 0.1 ppm or less.

(122) A first interlayer insulating film 237 is formed next, as shown in FIG. 32A. A single layer insulating film containing silicon is used as the first interlayer insulating film 237, or a lamination film may be used. Further, a film thickness of between 400 nm and 1.5 m may be used. A lamination structure of a silicon oxide film having a thickness of 800 nm on a silicon oxinitride film having a thickness of 200 nm thick is used in Embodiment 3.

(123) In addition, heat treatment is performed for 1 to 12 hours at 300 to 450 C. in an atmosphere containing between 3 and 100% hydrogen, performing hydrogenation. This process is one of hydrogen termination of dangling bonds in the semiconductor film by hydrogen, which is thermally excited. Plasma hydrogenation (using hydrogen excited by plasma) may also be performed as another means of hydrogenation.

(124) Note that the hydrogenation processing may also be inserted during the formation of the first interlayer insulating film 237. Namely, hydrogen processing may be performed as above after forming the 200 nm thick silicon oxinitride film, and then the remaining 800 nm thick silicon oxide film may be formed.

(125) Next, a contact hole is formed in the gate insulating film 211 and the first interlayer insulating film 237, and source wirings 238 to 242 and drain wirings 243 to 247 are formed. In this embodiment, this electrode is made of a laminate film of three-layer structure in which a titanium film having a thickness of 100 nm, an aluminum film containing titanium and having a thickness of 300 nm, and a titanium film having a thickness of 150 nm are continuously formed by sputtering. Of course, other conductive films may be used.

(126) A first passivation film 248 is formed next with a thickness of 50 to 500 nm (typically between 200 and 300 nm). A 300 nm thick silicon oxinitride film is used as the first passivation film 248 in Embodiment 3. This may also be substituted by a silicon nitride film. Note that it is effective to perform plasma processing using a gas containing hydrogen such as H.sub.2 or NH.sub.3 before the formation of the silicon oxinitride film. Hydrogen activated by this preprocess is supplied to the first interlayer insulating film 237, and the film quality of the first passivation film 248 is improved by performing heat treatment. At the same time, the hydrogen added to the first interlayer insulating film 237 diffuses to the lower side, and the active layers can be hydrogenated effectively.

(127) Next, a second interlayer insulating film 249 made of organic resin is formed as shown in FIG. 32B. As the organic resin, it is possible to use polyimide, polyamide, acryl, BCB (benzocyclobutene) or the like. Especially, since the second interlayer insulating film 249 is primarily used for leveling, acryl excellent in leveling properties is preferable. In this embodiment, an acrylic film is formed to a thickness sufficient to level a stepped portion formed by TFTs. It is appropriate that the thickness is made 1 to 5 m (more preferably, 2 to 4 W.

(128) Next, a contact hole is formed in the second interlayer insulating film 249 and the first passivation film 248 so as to reach the drain wiring 245, and a cathode electrode 250 of a photodiode is formed so as to contact the drain wiring 245. In embodiment 3, an aluminum film formed by sputtering is used as the cathode electrode 250, but other metals, for example titanium, tantalum, tungsten, and copper can also be used. Further, a lamination film made from titanium, aluminum, and titanium may also be used.

(129) Patterning is next performed after depositing an amorphous silicon film containing hydrogen over the entire surface of the substrate, and a photoelectric conversion layer 251 is formed. Then, a transparent conductive film is formed on the entire surface of the substrate. A 200 nm thick ITO film is deposited by sputtering as the transparent conductive film in Embodiment 3. The transparent conductive film is patterned, forming an anode electrode 252. (FIG. 32C.)

(130) A third interlayer insulating film 253 is then formed, as shown in FIG. 33A. A level surface can be obtained by using a resin such as polyimide, polyamide, polyimide amide, or acrylic as the third interlayer insulating film 253. A polyimide film having a thickness of 0.7 m is formed over the entire surface of the substrate as the third interlayer insulating film 253 in Embodiment 3.

(131) A contact hole is next formed in the third interlayer insulating film 253 so as to reach the anode electrode 252, and a sensor wiring 254 is formed. A 300 nm thick aluminum alloy film (an aluminum film comprising titanium of 1 wt %) is formed in Embodiment 3.

(132) The sensor substrate is formed which has the structure as shown in FIG. 33B.

(133) Reference numeral 270 shows an amplifier TFT, 271 shows a switching TFT, 272 shows reset TFT, 273 shows a bias TFT, and 274 shows discharge TFT.

(134) In embodiment 3, the amplifier TFT 270 and the bias TFT 273 are an n-channel TFT, and both of source region side and drain region side have LDD regions 281-282 and 284-285. Note that the LDD regions 281-282 and 284-285 do not overlap with the gate electrodes 212 and 215 through the gate insulating film 211. The above constitution of the amplifier TFT 270 and the bias TFT 273 can reduce the hot carrier injection as much as possible.

(135) Further in Embodiment 3, the switching TFT 271 and the discharge TFT 274 is a n-channel TFT, each TFTs has LDD regions 283 and 286 on only the drain region side. The LDD region 283 and 286 are overlapped to the gate electrode 213 and 216 interposing the gate insulating film 211.

(136) The formation of the LDD regions 283 and 286 on only the drain region side is in consideration of reducing the hot carrier injection and not causing the operating speed to drop. Further, it is not necessary to be too concerned with the value of the off current for the switching TFT 271 and the discharge TFT 274, and more importance may be placed on the operating speed. It is therefore preferable for the LDD regions 283 and 286 to completely overlap with the gate electrodes 213 and 216, and to reduce resistive components as much as possible. Namely, the so-called offset should be eliminated. In particular, when the source signal line driver circuit or the gate signal line driving circuit is driven at 15V to 20V, the above constitution of the discharge TFT 274 of Embodiment 3 is effective to reduce the hot carrier injection and also not to drop the operation speed.

(137) Furthermore, in Embodiment 3, a reset TFT 272 is p-channel TFT and has no LDD region. Degradation due to hot carrier injection is almost of no concern for the p-channel TFTs, and therefore LDD regions do not have to be formed in particular. It is also possible, of course, to form an LDD region similar to that of an n-channel TFT to take action against hot carriers. Further, the reset TFT 272 may be an n-channel type TFT.

(138) The device is completed as a manufactured product by attaching a connector (flexible printed circuit, FPC) for connecting terminals pulled around from the elements or circuits formed on the substrate with external signal terminals.

(139) The sensor is formed by using a TFT on the glass or the photodiode in this embodiment, the transistor on the single crystalline silicon substrate can also be used.

Embodiment 4

(140) The sensor manufactured by implementing the present invention can be used for various kinds of electronic equipments. The following can be given as such electronic equipment according to the present invention: a scanner; a digital still camera; an x-ray camera; a portable information terminal (a mobile computer, a portable telephone, and a portable game machine); a notebook type personal computer; a game apparatus; a video telephone, etc.

(141) FIG. 34A is a scanner, and contains a reading region 3402, a sensor portion 3401, a reading operation start switch 3404 and the like. The present invention can be used as the sensor portion 3401.

(142) FIG. 34B is a digital still camera, and contains a finder 3405, a sensor portion 3404, a shutter button 3406 and the like. The present invention can be used as the sensor portion 3404.

(143) FIG. 35 is an x-ray camera, and contains an x-ray generator 3501, a sensor portion 3503, a computer 3054 for signal processing and the like. An object 3502 to be examined stands between the x-ray generator 3501 and the sensor portion 3503, and the x-ray photograph is taken. The present invention can be used as the sensor portion 3503.

(144) FIG. 36 is a personal computer, and contains a main body 3601, a casing 3602, a display 3603, a keyboard 3604, a sensor portion 3605 and the like. The present invention can be used as the display 3603 and the sensor portion 3605.

(145) Here, FIG. 37 shows a portable telephone, and contains a main body 3701, a sound output portion 3702, a sound input portion 3703, a display 3704, operation switches 3705, an antenna 3706 and a sensor portion 3707. The present invention can be used as the sensor portion 3707.

(146) The present invention enables enlarging of the amplitude of the output while preventing the writing-in time of the output electric potential of the source follower circuit from becoming long. Further, at the same time, the present invention can widen the operating region in which the input/output relationship of the source follower circuit is linear. Consequently, an area sensor having a high image quality is realized.