Photodiode and method for producing the same, photodiode array, spectrophotometer and solid-state imaging device
09568364 ยท 2017-02-14
Assignee
Inventors
Cpc classification
H10F39/107
ELECTRICITY
H10F77/703
ELECTRICITY
Y02P70/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y02E10/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H10F39/803
ELECTRICITY
H10F71/00
ELECTRICITY
H10F39/18
ELECTRICITY
International classification
H01L21/00
ELECTRICITY
H01L31/18
ELECTRICITY
H01L31/103
ELECTRICITY
Abstract
Provided is a photodiode having a high-concentration layer on its surface, in which the high-concentration layer is formed so that the thickness of a non-depleted region is larger than the roughness of an interface between silicon and an insulation film layer, and is smaller than a penetration depth of ultraviolet light.
Claims
1. A signal processing method for performing a signal processing based on a signal output from a photodiode depending on photocharges generated in the photodiode by a light illumination, comprising: performing a signal processing using a photodiode based on a signal output from the photodiode, wherein the photodiode includes a semiconductor layer made of silicon and an insulator layer in contact with the semiconductor layer, wherein the semiconductor layer is provided with a first-conduction-type region and a second-conduction-type region located between the first-conduction-type region and an interface between the semiconductor layer and the insulator layer, the second-conduction-type region having a polarity opposite to the first-conduction-type region, and wherein a thickness of a non-depleted region of the second-conduction-type region is larger than roughness of the interface, and is smaller than a penetration depth of ultraviolet light at which an intensity of the ultraviolet light in a wavelength range of 200-320 nm entering the semiconductor layer is equal to 1/e times the intensity of the same ultraviolet light at an outermost surface of the semiconductor layer.
2. The signal processing method according to claim 1, wherein the signal processing is performed by a signal processing apparatus comprising: a photodiode array comprising a plurality of pixels arranged in the form of a one-dimensional array or a two-dimensional array, one of the plurality of pixels including the photodiode; and a means for scanning a signal from each of the plurality of pixels by predetermined procedures.
3. The signal processing method according to claim 2, wherein the signal is an image signal.
4. The signal processing method according to claim 2, wherein a light entering the photodiode array is dispersed in advance by a means for dispersing.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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BEST MODE FOR CARRYING OUT THE INVENTION
(11) Embodiments of the solid-state imaging system of the present invention are hereinafter described with reference to the attached drawings.
First Embodiment
(12)
(13) In the present embodiment, a silicon wafer 100 with the (100) oriented plane produced by the Czochralski (Cz) method is used. This silicon wafer is an n-type wafer, with an impurity concentration of 110.sup.15 cm.sup.3. A p-type silicon wafer may also be used. The surface region of the silicon wafer may be formed by epitaxial growth. The plane orientation of the silicon wafer is not limited to the (100) oriented plane.
(14) Preferably, a surface-smoothing process for making the roughness on the surface of the silicon wafer correspond to the minimal level difference on the (100) oriented plane of the silicon is initially performed. In the present embodiment, the silicon surface is smoothed by removing a natural oxide film from the surface by using a chemical solution of diluted hydrofluoric acid and then performing a heat treatment in a high-cleanness argon atmosphere at atmospheric pressure. The heat treatment is performed at 900 C. for one hour. H.sub.2 or Ar/H.sub.2 may also be used as the atmosphere in the heat treatment for the smoothing process. The pressure in the heat treatment may be lower than the atmospheric pressure. By this smoothing process, the surface of the silicon wafer 100 is smoothed on the atomic level.
(15) A portion of the smoothing process may be performed by using the method of forming an oxide film with a thickness of 100 nm or larger by wet oxidation at 1000 C. or higher temperatures and then peeling off the formed oxide film.
(16) A portion of the smoothing process may also be performed by using the method of immersing the silicon wafer in a chemical solution of diluted hydrofluoric acid under a light-blocked environment with the concentration of dissolved oxygen in the chemical solution being 1 ppb or lower.
(17) Subsequently, an insulator layer 5 is formed. Preferably, this layer is created by an oxidizing, oxynitriding or nitriding method in which the created interface between the silicon and the insulator layer 5 has roughness that corresponds to the minimal level difference of the atoms in the plane orientation of the silicon if the roughness of the silicon before the formation of the insulator layer 5 corresponds to the minimal level difference of the atoms in the plane orientation of the silicon. In the present embodiment, an oxide film is formed by an oxidizing method using a microwave-excited high-density plasma system. The film thickness of the formed insulator layer 5 in the present embodiment is 7 nm. Another possible method is an isotropic oxidation method using an oxygen radical as the oxidizing species in which the film-forming rate is independent of the plane orientation of the silicon. It has been confirmed that, in the case where the oxygen radical is used to form the insulator layer 5, the surface of the silicon wafer 100 which has been smoothed on the atomic level is completely maintained, and the interface between the silicon wafer 100 and the insulator layer 5 is also as smooth as the atomic level.
(18) After that, the p-type region 1 shown in
(19) Next, the n.sup.+-type region 2 is formed. In the present embodiment, this is achieved by injecting As.sup.+ ions with an injection energy of 10 keV and at a dose of 3.410.sup.13 cm.sup.2. As shown in
(20) In addition to reducing the thickness of the n.sup.+-type region 2 in the previously described manner, it is preferable to distribute the main impurity in the n.sup.+-type region 2 in such a manner that its concentration profile is highest at the interface and gradually decreases as it goes deeper in the silicon. This can be achieved by regulating the thickness of the insulator layer 5 and the injection energy in the ion-injection process for creating the n.sup.+-type region 2 so that the region where the concentration profile of the main impurity in the n.sup.+-type region 2 after the ion injection is maximized is formed within the insulator layer 5. In the present embodiment, the thickness of the n+-type region 2 is 25 nm.
(21) Even if the region where the concentration profile of the main impurity in the n.sup.+-type region 2 after the ion injection is maximized is located within the silicon wafer 100, the region where the concentration profile of the impurity is maximized can eventually be formed within the insulator layer 5 by further oxidizing the silicon after the ion injection.
(22) The ion species to be injected in the previously described processes may be As.sup.+, P.sup.+, Ab.sup.+, a cluster ion of one of these elements, or a fluoride ion or hydride ion of one of these elements, so that As, P or Sb will be the main impurity of the n.sup.+-type region 2.
(23) Subsequently, as shown in
(24) After that, a portion of the insulation film layer 6 and the insulator layer 5 is etched so as to bore a contact hole.
(25) Subsequently, a p.sup.+-type region 4 is created in the etched region. In the present embodiment, this is achieved by injecting ions with an injection energy of 10 keV and at a dose of 210.sup.15 cm.sup.2, using BF.sub.2.sup.+ as the injection species.
(26) Then, the injected impurity is activated. In the present embodiment, this is achieved by a lamp-type heating treatment with the temperature reaching up to 950 C. In order to prevent the impurity concentration profile created by the ion injection from changing due to the diffusion of the impurity which occurs during the heat treatment, this heat treatment should preferably be performed for a short period of time and at a maximum temperature at which the defect density will be suppressed to low levels.
(27) After that, the natural oxide film of the silicon at the contact-hole area is peeled off, and an electrode 7 is created by forming a metal film and patterning it. In the present embodiment, an aluminum layer is formed by vapor deposition as the metal layer.
(28) Then, after the natural oxide film on the reverse side of the silicon is peeled off, aluminum is vapor-deposited on the reverse side of the wafer to form an aluminum electrode 8 as shown in
(29) The region 2 in the present embodiment shown in
(30) As shown in
(31) In the present embodiment, the thickness 10 of the non-depleted region 9 (
(32) As shown in
(33) The reason why the thickness 10 of the non-depleted region 9 in the region 2 can be controlled according to the penetration depth 12 of the ultraviolet light and the roughness of the interface, as in the present invention, is because the interface between the region 2 and the insulator layer 5 is smoothed on the atomic level.
Second Embodiment
(34)
(35) Each of the regions 1, 2, 4, 5, 6 and 7 is identical to the region denoted by the same reference number in the first embodiment.
(36) The second embodiment differs from the first embodiment in that, before the region 1 is formed, a p-type silicon wafer 100 is used and an n-type region 3 is created in the p-type silicon wafer 100. The n-type region 3 is formed by injecting P.sup.+ ions with an energy of 250 keV and at a dose of 1.510.sup.12 cm.sup.2. The n-type region 3 and the p-type region 1 may be created in reverse order.
(37) In the present embodiment, the electrode 108 connected to the n-type region 3 via the n.sup.+-type region 2 is formed by a method equivalent to the method used for forming the electrode 7.
(38) The photodiode according to the present embodiment has the same effects as the first embodiment in terms of the sensitivity to ultraviolet light as well as the stability of the dark current and the sensitivity against long-term irradiation with the ultraviolet light.
(39) In the present embodiment, each of the regions 2 and 3 forms a PN junction with the region 1. These PN junctions create such a wide depletion layer that can entirely deplete the p-type region 1 within a voltage range in which the photodiode is operated, so that the photocharges accumulated in the p-type region 1 can be completely transferred. Thus, an effective transfer of the photocharges is achieved.
(40) As stated earlier, the polarity of the silicon wafer 100 in the present embodiment is p-type. Therefore, electric charges which have overflowed from the photodiode can be discharged by controlling the potential of the silicon wafer 100. For this purpose, a control electrode 101 is provided on the bottom side of the wafer 100. However, the polarity of the silicon wafer may be n-type.
(41) Although the region 2 in the present embodiment is n.sup.+-type, it is also possible to create a photodiode in which each of the polarities of the silicon wafer 100 and the regions 1 and 2 is reversed.
Third Embodiment
(42)
(43) The photodiode array includes pixels 13 arranged in the form of an array, with each pixel including at least one photodiode described in the first or second embodiment. In the present embodiment, the region 2 of the photodiode is n.sup.+-type, and a p-channel transfer transistor connected to a portion of the photodiode is created in each of the pixels.
(44) In the present embodiment, the pitch of the pixels 13 is 20 m. The total number of the pixels 13 is 1024.
(45) As shown, a shift register 14 is provided as a scan circuit for sequentially reading a signal from each of the pixels.
(46) In the present embodiment, positive holes are read out as the photocharges. A device which reads out electrons as the photocharges can also be created, in which case the photodiode has a p.sup.+-type region as the region 2 and an n-channel transistor is created as the transfer transistor.
(47) In the photodiode array according to the present embodiment, the photodiode section for generating and accumulating photocharges in each pixel has the characteristics described in the first and second embodiments. Therefore, a high level of sensitivity to the light in a wavelength range of 200-1100 nm, including ultraviolet light, is obtained in any of the pixels, without increasing the dark current. Furthermore, a signal originating from light impinging on each pixel can be individually read out.
(48) Since no local area in which the non-depleted region of the region 2 is thinner than the roughness of the interface is created by the fixed charges generated in the oxide film by a long-term irradiation with the ultraviolet light, both the dark current and the sensitivity are highly stable against the long-term irradiation with the ultraviolet light in any of the pixels.
Fourth Embodiment
(49)
(50) The spectrophotometer includes a light source 15, a first lens 16, a second lens 17, a diffraction grating 18 and a photodiode array 19. It is used for performing a measurement on an object 20 to be measured. Specifically, a light source consisting of a tungsten lamp and a deuterium lamp for generating light in a wavelength range of 200-1100 nm is used as the light source 15. A light source which generates light in a wavelength range of 200-320 nm may also be used.
(51) The first lens 16 is arranged so that the light generated by the light source 15 is focused on the measurement object 20. The light which has passed through the measurement object 20 is focused on the diffraction grating 18 via the second lens 17.
(52) A photodiode array 19 having a structure described in the third embodiment is located at a distance from the diffraction grating 18. The photodiode array 19 is placed at such a location where the diffracted light with the wavelength range of 200-1100 nm forms a 2-cm-wide spectral image. It has a wavelength-resolving power of approximately 1 nm for the light in the wavelength range of 200-1100 nm.
(53) In the present embodiment, the photodiode array 19 for generating and accumulating photocharges in each pixel has the characteristics described in the first and second embodiments. Therefore, a high level of sensitivity to the light in a wavelength range of 200-1100 nm, including ultraviolet light, is obtained without increasing the dark current. Furthermore, since no local area in which the non-depleted region of the region 2 is thinner than the roughness of the interface is created by the fixed charges generated in the oxide film by a long-term irradiation with the ultraviolet light, both the dark current and the sensitivity are highly stable against the long-term irradiation with the ultraviolet light.
(54) The spectrophotometer in the present embodiment has a basic configuration. A spectrophotometer having a different configuration will also exhibit the previously described effects if the photodiode array 19 described in the third embodiment is used in the photodetector section of the spectrophotometer.
(55)
(56) The solid-state image sensor includes pixels 13 arranged in the form of a two-dimensional array, with each pixel including at least one photodiode described in the first or second embodiment. In the present embodiment, it is assumed that the region 2 of the photodiode is n.sup.+-type, although the region 2 of the photodiode may be p.sup.+-type.
(57) Each of the pixels constituting the solid-state image sensor includes a transfer transistor connected to a portion of the photodiode, a floating diffusion for converting the transferred photodiodes into voltage, a source follower transistor for amplifying a voltage signal produced by the floating diffusion, a reset transistor for resetting the voltages of the floating diffusion and the photodiode, as well as a selection-switching transistor for selecting a pixel. Furthermore, as shown in
(58) The device described in the present embodiment is a CMOS image sensor. However, it may be configured as a CCD image sensor.
(59) In the present embodiment, the photodiode section for generating and accumulating photocharges in each pixel has the characteristics described in the first and second embodiments. Therefore, a high level of sensitivity to the light in a wavelength range of 200-1100 nm, including ultraviolet light, is obtained in any of the pixels, without increasing the dark current. Furthermore, a signal originating from light impinging on each of the pixels arranged in the form of a two-dimensional array can be individually read out, and an image can be captured.
(60) Since no local area in which the non-depleted region of the region 2 is thinner than the roughness of the interface is created by the fixed charges generated in the oxide film by a long-term irradiation with ultraviolet light, both the dark current and the sensitivity are highly stable against the long-term irradiation with the ultraviolet light in any of the pixels.
INDUSTRIAL APPLICABILITY
(61) The present invention is applicable to a photodiode, a photodiode array and a method for producing a photodiode, as well as a spectrophotometer or solid-state imaging system using a photodiode array. It can also be applied in an ultraviolet meter for monitoring the intensity of an ultraviolet light used in a stepper motor or scanner or that of an ultraviolet light for a high-performance liquid chromatograph, an ICP emission spectrophotometer, a Raman spectrophotometer, an in-vivo optical imaging system, a high-speed video camera, or other types of optical sensors which should desirably have high sensitivity to light including ultraviolet.
EXPLANATION OF NUMERALS
(62) 1 . . . p-Type Region 2 . . . n.sup.+-Type Region 3 . . . n-Type Region 4 . . . p.sup.+-Type Region 5 . . . Insulator Layer 6 . . . Insulation Film Layer 7 . . . Aluminum Electrode for p.sup.+-Type Region 8 . . . Aluminum Electrode for n.sup.+-Type Region 9 . . . Non-Depleted Region in n.sup.+-Type Region 10 . . . Thickness of Non-Depleted Region in n.sup.+-Type Region 11 . . . Roughness of Interface Between Silicon and Insulator Layer 12 . . . Penetration Depth of Ultraviolet Light in Silicon 13 . . . Pixel 14 . . . Shift Register 15 . . . Light Source 16 . . . First Lens 17 . . . Second Lens 18 . . . Diffraction Grating 19 . . . Photodiode Array 20 . . . Measurement Object 21 . . . Horizontal Shift Register 22 . . . Vertical Shift Register 100, 100 . . . Silicon Wafer 101 . . . Control Electrode 108 . . . Electrode