Frequency synthesizer circuit

Abstract

The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.

Claims

1. A frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module configured to delay an input reference signal to generate a delayed reference signal; a duty cycle module configured to generate the oscillator enable signal based on a period of the input reference signal and the delay of the delayed reference signal such that a ratio between the output frequency and a frequency of the input reference signal is a non-integer; wherein the delay module comprises: a time delay oscillator driven by an oscillator control voltage and configured to delay the delay module input reference signal by an amount based on a number of stages of the time delay oscillator: and wherein the delay module further comprises; a multiplexer with a selectable channel input; and a copy time delay oscillator configured to be controlled by said oscillator control voltage and operable to delay the input reference signal to generate the delayed reference signal.

2. The circuit according to claim 1, wherein the delay module is provided with a feedback loop to regulate the respective generated delayed reference signal.

3. The circuit according to claim 1, wherein the duty cycle module comprises a timing unit configured to generate the oscillator enable signal by combining both the input reference signal and the delayed reference signal.

4. The circuit according to claim 1, wherein the delay applied to the input reference signal by the delay module can be varied to generate a range of output frequencies of the output signal such that each output frequency within the range differs by a selected fractional channel spacing.

5. The circuit according to claim 1, further including a divider configured to reduce a frequency of operation of the delay module by an integer value such that the frequency of operation of the delay module is an integer division of the output frequency.

6. The circuit of claim 1, wherein the delay of the delayed reference signal corresponds to a frequency channel spacing selected by modifying either the channel input or the integer.

7. The circuit according to claim 1, wherein the copy time delay oscillator is a copy ring oscillator with a number of copy ring oscillator stages, wherein the number of active copy ring oscillator stages is controlled by the channel input of the multiplexer.

8. The circuit of according to claim 1, wherein the delay module is a phase locked loop.

9. The circuit according to claim 1, wherein the time delay oscillator is a delay line and wherein the stages are delay stages.

10. The circuit according to claim 5, wherein the divider is configured to provide a delay module input signal to the delay module at a frequency an integer division lower than the frequency of the output signal.

11. The circuit of claim 9, wherein the copy time delay oscillator is a copy delay line with a number of copy delay stages, wherein the number of active delay stages is controlled by the channel input of the multiplexer.

12. The circuit according to claim 10, wherein the time delay oscillator is a ring oscillator and the stages are ring stages.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The invention is described in further detail in the following by way of exemplary embodiments with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic block diagram of an integer duty cycled all digital phase locked loop circuit (DC-ADPLL);

(3) FIG. 2 illustrates the waveform of the reference signal and the digitally controlled oscillator signal;

(4) FIG. 3 is a schematic block diagram of a fractional duty cycled all digital phase locked loop circuit according to an embodiment;

(5) FIG. 4 is a schematic block diagram of a fractional duty cycled all digital phase locked loop circuit according to another embodiment; and

(6) FIG. 5 illustrates the output signal of a fractional duty cycled all digital phase locked loop circuit according to FIGS. 3 and 4 with varying selected delays.

DETAILED DESCRIPTION

(7) An example of an integer duty cycled all-digital phase locked loop (DC-ADPLL) circuit block diagram 10 is shown in FIG. 1. The DC-ADPLL consists of phase detector (PD) 12, coarse and fine tuning modules 14, 16, a Digitally Controlled Oscillator (DCO) 18, a Finite State Machine (FSM) 20 and a counter 22. In operation the FSM 20 duty-cycles the DCO 18 in small bursts by providing an oscillator enable signal 26 to enable and disable operation of the DCO 18. The output signal 28 of the DCO 18 is divided between the output of the circuit and the counter 22. The counter 22 measures the number of DCO 18 oscillations (i.e. the frequency of the output signal 28) within one single burst period. The counter output 29 is compared with the Frequency Control Word (FCW) 24 for differences in the phases of the two signals. Coarse 14 and fine 16 tuning can then be applied to the DCO 18 via inputs 25a, 25b to alter the phase of the output signal 28 using a DCO control word. Additionally, the DCO control word is stored into a memory to save its state between two consecutive burst generations. These elements 22, 12, 14, 16 together form a feedback loop 30 that acts to regulate the frequency of the output signal 28.

(8) Additionally, the FSM 20 is supplied with an input reference signal 42 with a fixed frequency that may be supplied by an oscillator source, such as a crystal oscillator 44. Based on the frequency of the input reference signal, the FSM 20 generates duty cycled oscillator enable signal 26. Once the frequency loop 30 is locked onto the required frequency, the frequency of the output signal 40 (f.sub.DCO) outputted by the DCO 18 will be equal to the FCW 24 multiplied by the frequency of the input reference signal 42 (f.sub.REF). Duty-cycling ensures that the most power hungry blocks are only enabled during one reference clock period and disabled during the remaining N1 clock reference periods, enabling highly energy efficient systems.

(9) Such DC-ADPLLs 10 can be used only in integer mode, i.e. the ratio between the frequency of the output signal (f.sub.DCO) 28 and the input reference signal 42 is an integer value. Since the frequency of the input reference signal 42 is in the MHz range, such DC-ADPLLs 10 can be used only for radios compliant with standards with relative large channel spacing.

(10) FIG. 2 outlines the waveforms of the input reference signal 42 and the oscillator enable signal 26 provided by the FSM 20. The period 46 of the input reference signal 42 is shown.

(11) In general, the output of an integer-N DC-ADPLL is equal to the FCW/T.sub.REF. For a fractional-N DC-ADPLL the period 46 of the reference signal 42 (T.sub.REF) is increased by a well-defined delay value (d), leading to an output centre frequency equal to FCW/(T.sub.REF+d).

(12) The generation of this time delay can be implemented in several ways, some examples of which are described below.

(13) FIG. 3 is a schematic block diagram of an exemplary frequency synthesiser circuit in the form of a fractional DC-ADPLL circuit 100. The circuit 100 comprises a duty cycled all digital phase locked loop (DC-ADPLL1) 110 comprising some of the same components and arrangements to that shown in FIG. 1. In particular, a phase detector 112, coarse and fine tuning modules 114, 116, a digitally controlled oscillator 118, with inputs 125a, 125b, a counter 122 and an input 124 for a frequency control word are employed.

(14) The DC-ADPLL1 110 is configured to provide a output signal 128 (having a frequency f.sub.wanted) and is further configured to be duty cycled by an oscillator enable signal 126 for a set period of an input reference signal 142 and a delayed reference signal 144 supplied by a timing unit 150. The output signal may also be fed back into the phase locked loop 127. The timing unit 150 comprises a series of flip-flops 152 coupled to an XOR gate 154. The timing unit 150 is configured to apply an oscillator enable signal for the period of the input reference signal 142 and a delay to actively control operation of the DC-ADPLL1 110, thereby duty cycling the DC-ADPLL1. The timing unit 150 can be considered a duty cycle module.

(15) The delayed reference signal 144 is provided by a delay module 160. In the example shown, the delay module 160 comprises a second duty cycled all digital phase locked loop (DC-ADPLL2) comprising a phase difference module 162, coarse and fine tuning modules 164, 166, supplying inputs 170, a time delay oscillator 168, a counter 172 and an input 174 for a frequency control word. These components can be broadly considered to be a delay module feedback loop 162, 164, 166, 172, 174, connected between an output, being a delay module output signal 194 and a ring oscillator input 170 of a signal generator 168.

(16) The delay module 160 additionally comprises a multiplexer 180 with a channel input 182. The multiplexer 180 is configured to provide the delayed reference signal 144 to the timing unit 150.

(17) In the example shown in FIG. 3, a divider is used to step down the frequency of the delay module input signal 169 when compared to the oscillator enable signal 128.

(18) The divider is intended to reduce the frequency at which the delay module operates. Typically, the frequency at which the delay module operates is dependent upon the delay module input signal 169 and a frequency control word input 174 to the delay module 160. The divider reduces the frequency of operation of the delay module 160 by an integer value. Accordingly, the frequency of operation of the delay module 160 (the frequency of a delay module output signal 194) is then an integer division of the output frequency of the output signal 128. The frequency of the delay module output signal 194 is based on the delay module input signal 169. In the example shown, the delay module input signal 169 is the oscillator enable signal 126.

(19) In this embodiment, the divider is operable to alter a frequency control word input to the delay module 160 to be an integer division of a frequency control word input to the digitally controlled oscillator 118. For example, the frequency control word input to the delay module 160 may be four times lower than the frequency control word applied to the digitally controlled oscillator 118.

(20) In operation, the time delay oscillator 168, which in the embodiment shown is a ring oscillator 168, is supplied with a delay module input signal 169 supplied by the timing unit 150. As described above, the ring oscillator 168 produces a delay module output signal 194 at a frequency an integer division of the frequency of the output signal 128.

(21) The delay module output signal 194 may then be fed back to the ring oscillator 168 via the delay module feedback loop 162, 164, 166, 172, 174, that monitor and adjust the ring oscillator 168 using fine 166 and coarse 164 tuning controls.

(22) Once the frequency of the delay module output signal 194 is settled, the range of incremental delays capable of being output by the delay module 160 can be seen to correspond to a channel spacing proportional to the integer supplied by the divider.

(23) Furthermore, the ring oscillator 168 is driven by a line control voltage 190 and comprises a series of N ring stages 192 that are a series of NOT gates. As noted above, the frequency of the delay module output signal 194 generated by the ring oscillator 168 is considered to be the frequency of operation of the delay module 160 and is selected to be equal to the frequency of the output signal 128 divided by the integer such that the frequency of the delay module output signal 194 is an integer division of the frequency of the output signal 128.

(24) The delay module 160 additionally comprises a copy time delay oscillator 196, in this example a copy ring oscillator 196, driven by the line control voltage 190 via a digital to analogue converter 188 and also comprising a series of N.sub.D copy ring stages 198 that are a series of NOT gates. The number of ring stages of the copy ring oscillator 196 is selectable in a number of channels (CH) and dependent on the wanted or selected channel. Accordingly, the number of delay stages (N.sub.D) in the delay line can be selected or scaled.

(25) The copy ring oscillator 196 is configured to provide the delayed reference signal 144. The copy ring oscillator 196 is coupled to the multiplexer 180 and the channel 182. Accordingly, by selecting a channel of the multiplexer 180 the number of copy ring stages 198 of the delay line (copy ring oscillator) 196 can be varied or chosen to vary the number of active copy ring stages and therefore also to select the output of the copy ring oscillator 196 that corresponds with the selected or wanted delay (i.e. wanted fractional channel spacing) and therefore the delay of the reference signal 142, that depending on the channel selected will be delayed by a known amount, resulting in delayed reference signal 144.

(26) The frequency of the input reference signal 142 is not changed by the copy ring oscillator 196. However, the input reference signal 142 is delayed by the copy ring oscillator 196 (the frequency stays the same). The amount of delay applied depends where the input reference signal 142 is tapped off (with the multiplexer 180). For example, if the input reference signal 142 is tapped off at the first NOT gate, this corresponds with a delay of d (if the ADPLL is locked). The delayed reference signal 144 signal is therefore the input reference signal 142, delayed by d. As noted above, by configuring the delay enable signal 169 accordingly, the delay can correspond with an integer [MHz] channel spacing at the wanted output signal 128 and a 1 MHz spacing (integer/integer) at the delay module output signal 194, where the integer is the value selected and applied by the divider.

(27) Again, if instead the input reference signal 142 is muxed at the third NOT gate, this corresponds with a delay equal to 3d. The delayed reference signal 144 signal is then the input reference signal 142 delayed by 3d (it is the same signal only delayed). This again corresponds to a channel spacing of 3*integer [MHz] at the wanted output signal 124 and 3 MHz at the delay module output signal 198.

(28) Once the delayed reference signal 144 is generated it is fed, together with the input reference signal 142, into the timing unit 150. The timing unit 150 combines the input reference signal 142 with the delayed reference signal 144 (a delayed version of the input reference signal 142), to generate a period of the oscillator enable signal 126 equal to T.sub.ref+CH*d. The timing unit 150 provides the oscillator enable signal 126 to both DC-ADPLLs 110, 160. The oscillator enable signal 126 serves two purposes and acts both as a reference signal for obtaining the required or wanted fractional channel spacing and also to duty cycle the ADPLLs.

(29) If the introduced delay d is generated through an ADPLL employing a N ring stages (N.sub.ring) ring oscillator oscillating at a frequency equal to the output frequency, (f.sub.DCO), then the delay of one single stage of the ring oscillator is equal to 1/(f.sub.DCO*2*N.sub.ring) and the fractional frequency can be as low as f.sub.REF/2*N.sub.ring.

(30) As an example, if N.sub.ring=8 and f.sub.REF=16 MHz, a channel spacing of 1 MHz can be obtained which is 16 times smaller than the channel spacing obtained by an integer DC-ADPLL employing the same 16 MHz clock reference. An important point is that delay value (d) is based on the ring oscillator that is within the ADPLL, meaning that once the loop is settled the delay is exactly 1/(f.sub.DCO*2*N.sub.ring). If this delay is now added to enable signal of the PLL (through copy ring oscillator, multiplexer and timing unit) the f.sub.REF/2*N.sub.ring holds.

(31) Since the output introduced delay d should be accurate and robust to Process-Voltage-Temperature (PVT) variations, the multi-stages ring oscillator needs to be embedded into a PLL. Moreover the delay value, d, should be small compared to the reference period resulting in a high number of stages N.sub.ring and in a high ring oscillator frequency f.sub.DCO. Additionally, the thermal noise of the ring oscillator 18 should be minimised to mitigate its effect on the inaccuracy of the output delay d. All these considerations result into a large power dissipation.

(32) A lower power implementation can be obtained when the target standard has a coarse frequency channel spacing. If d is based on f.sub.dco/Integer with an N.sub.ring stage ring oscillator, the fractional frequency step will be f.sub.REF*Integer/(2*N.sub.ring). For example, the IEEE standard 802.15.4 protocol defines a frequency range for output signals from 2.4 GHz to 2.48 GHz with a channel spacing for each output signal of 5 MHz. This can be easily addressed by employing f.sub.REF=16 MHz. N.sub.ring=8 and Integer=5. The introduction of a factor Integer in the equations results in a ring oscillator operating at a 5 times lower frequency with lower power consumption.

(33) Since the oscillator enable signal 128 is applied for the period of the input reference signal plus the delay (that represents a fractional channel spacing) then both DC-APLL1 and DC-APLL 2 will settle to a fractional channel, namely to (FCW.sub.DC-ADPLL 1*f.sub.REF-CH*f.sub.REF*(Integer/N.sub.D)). Based on the example above, it may be noted that the fractional channel spacing is obtained by adding a controlled delay (in this case obtained from an All Digital PLL) to the reference period. Low power implementation is obtained by introducing an integer division factor corresponding to a particular output channel spacing as specified by the target standard.

(34) In this manner, a Fractional-N DC-ADPLL may be considered to comprise of an integer-N DC-ADPLL combined with a secondary loop which generates a well-controlled time delay. This secondary loop output frequency is in fixed relation to the main integer-N DC-ADPLL. Because of this fixed relation the time delay will result in an exact fractional relationship once the secondary loop is settled.

(35) The right combination of copy ring stages 198 (N.sub.ring) and the Integer allows the circuit 100 to address a given delay which in turns enables the generation of the channel spacing specified by the target standard. As an example, for the 2.4 GHz 802.15.4 IEEE standard the channel spacing should be 5 MHz. If f.sub.REF=16 MHz, N.sub.ring=8 stages (N.sub.D=2*N.sub.ring) and Integer=5 can be used leading to a smaller overhead in power, to enable the use of the DC-ADPLL for this standard.

(36) For conventional digitally controlled oscillators, the frequency of an output signal of, for example a phase locked loop, is equal to the product of the input reference frequency and the frequency control word,
f.sub.DCO=FCW.Math.f.sub.REF.

(37) For the embodiments described with reference to FIGS. 3 and 4, a fixed given delay is added to the period of the reference frequency by the copy ring oscillator. This alters the output frequency 128 of the digitally controlled oscillator 118. The output frequency 128 is therefore given by,

(38) $f_{\mathrm{DCO}}=\frac{FCW}{T_{\mathrm{REF}}+d}.$

(39) A fractional channel spacing may be obtained by using the delay introduced by the multi-stage ring oscillator. For a multi-stage ring oscillator, the delay is given by,

(40) $d=\frac{1}{f_{\mathrm{DCO},\mathrm{ring}}.Math.2.Math.N_{\mathrm{ring}}}$

(41) The frequency of the multi-stage ring oscillator can be considered using the above theory because the ring oscillator is within a phase locked loop. The phase locked loop controls the output frequency of the multi-stage ring oscillator to the frequency of the digitally controlled oscillator and also the delay of the ring oscillator stages. If this delay is then used to increase the reference period of the input reference signal, then the phase locked loop is also controlled to the frequency of the input reference signal. In this way, the phase locked loop acts as a feedback between the output signal 128 of the digitally controlled oscillator and the oscillator enable signal 126. Applying this delay to the output frequency, and by assuming that f.sub.DCO,ring=f.sub.DCO

(42) $f_{\mathrm{DCO}}=FCW.Math.f_{\mathrm{REF}}-\frac{f_{\mathrm{REF}}}{2.Math.N_{\mathrm{ring}}},$

(43) and assuming that the multi-stage ring oscillator is run at 2.4 GHz and N.sub.ring=8, results in a 1 MHz frequency resolution or channel spacing. The assumption that f.sub.DCO,ring=f.sub.DCO holds in the present examples where the ring oscillator is within a phase locked loop. In such examples, the phase locked loop controls f.sub.DCO,ring to equal f.sub.DCO and also controls the delay of the ring oscillator stages. Additionally, if the delay is used to increase the period of the input reference signal, the phase locked loop is also controlled to the frequency of the input reference signal. Accordingly, the feedback generated by the phase locked loop is based on the input reference signal of the phase locked loop.

(44) However, such a solution tends to have a high power consumption. This can be addressed by introducing a division factor as described with reference to the embodiments above. In this instance, the delay d of the ring oscillator is given by,

(45) $d=\frac{1}{\frac{f_{\mathrm{DCO}}}{\mathrm{DIV}}.Math.2.Math.N_{\mathrm{ring}}},$

(46) because the ring oscillator frequency is an integer (DIV) times lower than the digitally controlled output frequency. Generating f.sub.DCO/DIV could be achieved by another phase locked loop operating at an integer (in the equations above and below, DIV) times lower frequency (i.e. at a lower power). The output frequency is then given by,

(47) $f_{\mathrm{DCO}}=FCW.Math.f_{\mathrm{REF}}-f_{\mathrm{REF}}.Math.\frac{\mathrm{DIV}}{2.Math.N_{\mathrm{ring}}}.$

(48) Applying a DIV (or integer) of 5 for the above N.sub.ring and driving frequency results in a 5 MHz channel spacing, but with a lower power consumption due to the reduced frequency of the ring oscillators.

(49) Applying the analysis above allows for a relationship between the output frequency and the selected channel to be determined,

(50) $f_{\mathrm{DCO}}=FCW.Math.f_{\mathrm{REF}}-\mathrm{CH}.Math.f_{\mathrm{REF}}.Math.\frac{\mathrm{DIV}}{N_D},$

(51) where N.sub.D=2*N.sub.ring and the period of the oscillator enable signal is equal to the period of the input reference signal plus the sum of the number of channel delays.

(52) An alternative embodiment is shown in FIG. 4. FIG. 4 shows the use of an alternative delay module 210 that may be considered to be a Delay Locked Loop (DLL). The delay module 210 comprises a phase difference module 212, a digital to analog converter (DAC) 216, a digitally controlled time delay oscillator in the form of a delay line 220 with N.sub.D delay line stages 222 and a copy time delay oscillator in the form of a copy delay line 230 with N.sub.D copy delay line stages. The delay line has an input 219 and an output 218. In this example, the phase difference module 212 and DAC 216 act as a delay module feedback loop to regulate a delay module input signal 228 by altering a line control voltage 268.

(53) As noted, this circuit 200 has a DC-ADPLL 110 and a delay module 210 based on an N.sub.D stage delay line 220. The DC-ADPLL 110 generates the output signal 128 operating at the output frequency (f.sub.output) while the delay module 210 operates at a frequency of a delay module input signal 228, the frequency of which is an integer division lower. The delay module enable (or input) signal 228 is generated by supplying the output signal 128 to a divider 226 that divides the frequency of the output signal 128 by an integer and outputs the delay module input signal 228 to an input of the delay module 210.

(54) The duty cycled all digital phase locked loop 110 and the timing unit 150 are as described with reference to FIG. 3. Similarly to the previous architecture described with reference to FIG. 3, the delay module 210 is used to generate a delayed reference signal 244 with an associated delay value which exactly matches the needed delay to address the output channel spacing. In order to couple the DC-ADPPL 110 and the delay module 210, and to use this delay, a replica or copy of the delay line 220 is employed. The copy delay line 230 has the same amount of stages 232 N.sub.D and it is controlled by the same line control voltage 268 as the delay line 220. As described before, by using a multiplexer (MUX) 180 and Timing Unit 150, it is possible to add the generated delay d to the reference clock T.sub.ref that is used as the input reference signal or oscillator enable signal 126 for the first PLL 110.

(55) The number of copy delay line stages 232 of the copy delay line 230 can be selected to provide the required phase shift or delay of the delayed reference signal 244. The value of the channel input 182 can determine the number of active copy delay lines 232. In this instance, the degree of delay depends on the number of active copy delay lines 232.

(56) The delayed reference signal 244 is generated by a providing the delay module input signal 228 as an input to the delay line 220. The delay line 220 outputs a delay module output signal 218. Because the delay line 220 has a set number of delay line stages 222, the output delay (i.e. the phase shift of the delay module output signal 218) is dependent on the input delay (i.e. the phase of the delay module input signal 228). Because the copy delay line 230 is driven by the same line control voltage 268 as the delay line 220, by selecting the number of copy delay line stages 232 of the copy delay line 230, the output delay of the copy ring oscillator 230 (the phase of the delayed reference signal 244) can be controlled or selected. In this manner, the delay of the delayed reference signal 244 can be varied in steps corresponding to the output channel spacing in a similar manner to the embodiments described with reference to FIG. 3.

(57) Accordingly, the value of the channel input 182 can determine the number of active copy delay line stages 232. This allows the channel spacing between the frequencies of the output signal 128 for different channel inputs 182 to be controlled by controlling the selected channel and/or the value of the integer.

(58) The delay module input signal 169 may be the output frequency.

(59) As noted above, in embodiments, altering the number of copy delay stages 232 of the copy delay line 230 may alter the phase of the delay reference signal 244 relative to the input reference signal 128. In this example, the spacing between the copy delay stages 232 corresponds to a frequency or delay channel spacing selected by the channel input 182. When a delay line is employed, the delay module may be considered to be a delay locked loop.

(60) FIG. 5 shows the output oscillator enable signal 126 (f.sub.dco) for the embodiments shown in FIGS. 3 and 4 for three differing delay channels where a 5 MHz channel spacing has been chosen. As noted, when there is no delay the frequency of the output signal 410 is equal to the frequency of the input reference signal, in this instance 2.4 GHz. For a single channel delay 420, the frequency of this signal increases to 2.405 GHz. A similar increase is observed for a 2 channel delay 430, with frequency 2.41 GHz. It is noted that the signals demonstrate chatter or noise about the desired values, although this is within expected limits. This noise is typically differential nonlinearity noise and the resulting least significant bit step of the control voltage 168, 268 can be reduced by design to accommodate application accuracy specifications. Accordingly, by varying the channel 182 the delay introduced can likewise be increased, which alters the output frequency of the circuits output signal. It can be noted that the output frequency is a fraction of the reference frequency, rather than an integer. As noted above, known DC-ADPLLs only support an integer channel spacing where the ratio between the output frequency f.sub.DCO and the reference is an integer value.

(61) In summary, a fractional ratio between the frequency of an output signal 128 f.sub.DCO and the frequency of the reference signal 144 is introduced. This is achieved by introducing a controlled delay that addresses desired channel spacing. An integer mode DC-ADPLL is transformed into a fractional-N DC-ADPLL by introducing a well-controlled delay element in the loop. This controlled delay is derived directly from a DC-ADPLL ring oscillator or delay line. The number of stages of the ring oscillator or delay line determines the minimal achievable delay and hence the minimal frequency step. For very small frequency steps a ring oscillator or delay line with a higher number of stages is required. This requirement can be relaxed in particular situations by introducing a divider to step down the operating frequency of the delay module leading to lower power implementations of the fractional DC-ADPLL.

(62) Coarse control of this delay will result in coarse channel spacing and also into a low power implementation of fractional-N DC-ADPLL. It is envisaged that such fractional-N Duty Cycled ADPLLs can be used as local oscillators in low power receivers and may be implemented in low power listening modes in the context of ultra low power wireless sensor networks (WSN) and wearable devices.

(63) Other embodiments are within the scope of the invention, which is defined by the appended claims.