Reference voltage generation and calibration for single-ended signaling

Abstract

A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Claims

1. A signaling system, comprising: an integrated circuit transmitter; an integrated circuit receiver; and a conductive signal path coupling the integrated circuit transmitter and the integrated circuit receiver, the conductive signal path to convey a signal from the integrated circuit transmitter to the integrated circuit receiver, wherein bits of the signal are conveyed as a function of signal levels in the signal; wherein the integrated circuit transmitter is to convey a first one of the signal levels by coupling a transmitter power supply voltage to the conductive signal path and is to convey a second one of the signal levels by coupling a ground plane to the conductive signal path, the integrated circuit transmitter further to capacitively-couple the first one of the signal levels to the ground plane, such that ground plane noise is coupled to the conductive signal path irrespective of whether the first or second one of the signal levels is to be transmitted, and the integrated circuit receiver is to discriminate between the first and second ones of the signal levels by comparing the signal to a reference voltage and, further, is to capacitively-couple the reference voltage to the ground plane in a manner such that a ground plane noise profile associated with transmission of the signal by the transmitter integrated circuit is mimicked in the reference voltage at the receiver integrated circuit.

2. The signaling system of claim 1, wherein the transmitter integrated circuit further comprises circuitry that is to isolate the transmitter power supply voltage from power supply noise below a first frequency, and short to the ground plane power supply noise above the first frequency.

3. The signaling system of claim 1, wherein the receiver integrated circuit further comprises circuitry that is to establish a direct current (DC) offset for the reference voltage during a calibration mode and is to generate the reference voltage during a normal operating mode in a manner that is dependent on the DC offset.

4. The signaling system of claim 3, wherein: the transmitter integrated circuit is further to transmit a data pattern to the receiver integrated circuit in the calibration mode; and circuitry in the receiver integrated circuit is to interpolate between alternative values of the reference voltage and is to select a value of the reference voltage for use in the normal operating mode dependent on a balance between high and low logic states which corresponds to the data pattern as transmitted by the transmitter integrated circuit.

5. The signaling system of claim 1, wherein: the transmitter integrated circuit is to transmit a data pattern to the receiver integrated circuit in a calibration mode; and circuitry in the receiver integrated circuit is to interpolate between alternative values of the reference voltage and is to select a value of the reference voltage for use in a normal operating mode dependent on a balance between high and low logic states which corresponds to the data pattern as transmitted by the transmitter integrated circuit.

6. The signaling system of claim 1, wherein the data pattern comprises an equal number of the high and the low logic states, and wherein the circuitry in the integrated circuit receiver is to select the value of the reference voltage for use in the normal operating mode according to which of the alternate values of the reference voltage yields and equal number of the high and low logic states.

7. The signaling system of claim 1, wherein: the transmitter integrated circuit is one of a memory controller integrated circuit or a memory device; and the receiver integrated circuit is the other of the memory controller integrated circuit or the memory device.

8. The signaling system of claim 1, wherein the receiver integrated circuit comprises circuitry to establish the reference voltage at the voltage midpoint of the signal as received by the receiver integrated circuit from the conductive signal path.

9. The signaling system of claim 1, wherein the receiver integrated circuit further comprises a differential amplifier that is to amplify a difference between the signal received by the received integrated circuit from the conductive signal path and the reference voltage as capacitively-coupled to the ground plane by the receiver integrated circuit.

10. The signaling system of claim 1, wherein the signal is a single-ended signal.

11. A signaling system, comprising a first integrated circuit and a second integrated circuit, and conductive signal paths coupling the first integrated circuit and the second integrated circuit, wherein: the first integrated circuit comprises for each of the conductive signal paths, a transmitter; the second integrated circuit comprises for each of the conductive signal paths, a receiver; and each conductive signal path is to convey a respective signal from the first integrated circuit to the second integrated circuit, wherein bits of the respective signal are conveyed as a function of signal levels in the respective signal; wherein further, for each of the conductive signal paths, the transmitter is to convey a first one of the signal levels by coupling a transmitter power supply voltage to the respective conductive signal path and is to convey a second one of the signal levels by coupling a ground plane to the respective conductive signal path, the transmitter to capacitively-couple the first one of the signal levels to the ground plane, such that ground plane noise is coupled to the respective conductive signal path irrespective of whether the first or second one of the signal levels is to be transmitted on the respective conductive signal path, and the receiver is to discriminate between the first and second ones of the signal levels by comparing the respective signal to a reference voltage and, further, is to capacitively-couple the reference voltage for the receiver to the ground plane in a manner such that a ground plane noise profile associated with transmission of the respective signal by the corresponding transmitter is mimicked in the reference voltage for the receiver at the receiver integrated circuit.

12. The signaling system of claim 11, wherein each transmitter further comprises circuitry that is to isolate the transmitter power supply voltage for the transmitter from power supply noise below a first frequency, and short to the ground plane power supply noise for the transmitter above the first frequency.

13. The signaling system of claim 11, wherein each receiver further comprises circuitry that is to, during a calibration mode, establish a direct current (DC) offset for the reference voltage used by the receiver, and is to, during the normal operating mode, generate the reference voltage for the receiver in a manner that is dependent on the DC offset for the reference voltage used by the receiver.

14. The signaling system of claim 13, wherein: each transmitter is further to transmit a data pattern to the corresponding receiver in the calibration mode; and circuitry in each receiver in the calibration mode is to interpolate between alternative values of the reference voltage for the receiver and is to select a value of the reference voltage for the receiver for use in the normal operating mode dependent on a balance between high and low logic states which corresponds to the data pattern transmitted by the corresponding transmitter.

15. The signaling system of claim 11, wherein: each transmitter is to transmit a data pattern to the corresponding receiver in a calibration mode; and circuitry in each receiver in the calibration mode is to interpolate between alternative values of the reference voltage for the receiver and is to select a value of the reference voltage for the receiver for use in a normal operating mode dependent on a balance between high and low logic states which corresponds to the data pattern transmitted by the corresponding transmitter.

16. The signaling system of claim 11, wherein the data pattern comprises an equal number of the high and the low logic states, and wherein the circuitry in each receiver is to select the value of the reference voltage for use in the normal operating mode by the receiver according to which of the alternate values of the reference voltage for the receiver yields and equal number of the high and low logic states.

17. The signaling system of claim 11, wherein: the first integrated circuit is one of a memory controller integrated circuit or a memory device; and the second integrated circuit is the other of the memory controller integrated circuit or the memory device.

18. The signaling system of claim 11, wherein each receiver comprises circuitry to establish the reference voltage at the voltage midpoint of the signal as received by the receiver from the corresponding conductive signal path.

19. The signaling system of claim 11, wherein each receiver further comprises a differential amplifier that is to amplify a difference between the respective signal received by the receiver from the respective conductive signal path and the reference voltage for the receiver as capacitively-coupled to the ground plane.

20. A signaling system, comprising a first integrated circuit and a second integrated circuit, and conductive signal paths coupling the first integrated circuit and the second integrated circuit, wherein one of the first integrated circuit and the second integrated circuit is a memory controller integrated circuit and the other of the first integrated circuit and the second integrated circuit is a memory device, and wherein: the first integrated circuit comprises for each of the conductive signal paths, a transmitter; the second integrated circuit comprises for each of the conductive signal paths, a receiver; and each conductive signal path is to convey a respective single-ended signal from the first integrated circuit to the second integrated circuit, wherein bits of the respective single-ended signal are conveyed as a function of signal levels in the respective single-ended signal; wherein further, for each of the conductive signal paths, the transmitter is to convey a first one of the signal levels by coupling a transmitter power supply voltage to the respective conductive signal path and is to convey a second one of the signal levels by coupling a ground plane to the respective conductive signal path, the transmitter to capacitively-couple the first one of the signal levels to the ground plane, such that ground plane noise is coupled to the respective conductive signal path irrespective of whether the first or second one of the signal levels is to be transmitted on the respective conductive signal path, and the receiver is to discriminate between the first and second ones of the signal levels by comparing the respective single-ended signal to a reference voltage and, further, is to capacitively-couple the reference voltage for the receiver to the ground plane in a manner such that a ground plane noise profile associated with transmission of the respective signal by the corresponding transmitter is mimicked in the reference voltage for the receiver at the receiver integrated circuit.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 presents a high-level block diagram illustrating a single-ended communication system which uses a receiver-side reference voltage to compare against a received voltage signal.

(2) FIG. 2 illustrates a single-ended memory system which provides circuits for tracking noise in a reference voltage generated on the receiver side of the memory system.

(3) FIG. 3 illustrates a single-ended memory system which includes circuits for calibrating a DC level for a reference voltage generated on the receiver side of the memory system.

(4) FIG. 4 illustrates an interpolation technique for calibrating a V.sub.ref DC level based on a residual ripple pattern.

(5) FIG. 5 presents a flowchart illustrating an exemplary process for calibrating the DC level of the reference voltage in a single-ended signaling system comprising a transmitter and a receiver.

DETAILED DESCRIPTION

(6) The disclosed embodiments relate to techniques for generating a high-quality reference voltage on a receiver of a single-ended signaling system, wherein the reference voltage is compared against a signal received from a transmitter of the single-ended signaling system.

(7) In some embodiments, techniques for reducing noise effects on a reference voltage generated on the receiver are described. In one embodiment, a signal which is generated on the transmitter is coupled to a ground node of a power supply on the transmitter so that the signal tracks a noise associated with the ground node. This signal is also decoupled from a positive node of the power supply on the transmitter so that the signal is isolated from a noise associated with the positive node. The signal is transmitted from the transmitter to the receiver, wherein the received signal is isolated from noise on the positive nodes of power supplies on both the transmitter and the receiver. Moreover, a reference voltage is generated on the receiver such that the reference voltage also tracks the noise on the ground node of the power supply while isolated from the noise on the positive node of the power supply on the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when the two signals are compared on the receiver.

(8) In further embodiments, techniques for calibrating a DC value (also referred to as a DC level in this disclosure) of a reference voltage generated on the receiver are described. In a specific embodiment, a calibration process uses only receiver-side circuits to calibrate the reference voltage in a number of steps. More specifically, the reference voltage is compared against a received signal comprising a predetermined calibration pattern on the receiver. A sampler samples the difference between the reference voltage and the received signal, and a calibration controller generates an error signal based on the sampler output and the predetermined calibration pattern. In one calibration step, the error signal is used to adjust a set of offset bits to compensate for DC offsets in the sampler. In another calibration step, the error signal is used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

(9) In the discussion below, the term noise refers to AC noise at frequencies that are above DC level. Moreover, the terms DC level and DC value are used interchangeably to refer to the DC component in the reference voltage.

(10) FIG. 1 presents a high-level block diagram illustrating a single-ended communication system 100 which uses a receiver-side reference voltage to compare against a received voltage signal. As illustrated in FIG. 1, communication system 100 includes a transmitter 102 (such as a memory controller), a receiver 104 (such as a memory device), and an interface 101 coupled between transmitter 102 and receiver 104, wherein interface 101 further includes a signal channel 106. Moreover, transmitter 102 can further include a signal-generating circuit 108, while receiver 104 can further include a reference voltage generator 114 and an amplifier/sampler 116.

(11) During data signaling on communication system 100, signal-generating circuit 108 in transmitter 102 generates a signal 118, which is then transmitted over signal channel 106. Signal 118 is received by receiver 104 as a received signal 118. In particular embodiments, signal 118 (and hence signal 118) is a single-ended voltage signal which is referenced to a ground level. For example, this ground level can be a ground node of a power supply, illustrated as V.sub.ss in FIG. 1.

(12) In some embodiments, transmitter 102 is configured in a way so that signal 118 will include the noise in V.sub.ss (referred to as V.sub.ss noise) but is lack of the noise in a positive node V.sub.dd of the power supply on transmitter 102 (referred to as V.sub.dd noise). As a result, received signal 118 also includes V.sub.ss noise but lack of transmitter V.sub.dd noise. To resolve/recover original signal 118 on receiver 104, signal 118 is compared against a reference voltage 120 generated by reference voltage generator 114, as illustrated in FIG. 1, and the difference between the two signals is sampled by amplifier+sampler 116. In some embodiments, both signal 118 and reference voltage 120 are referenced to a ground node of a power supply, illustrated as V.sub.ss in FIG. 1. While ground node V.sub.ss on transmitter 102 and ground node V.sub.ss on receiver 104 may not necessarily be the same node, they can be made to have substantially the same DC level and substantially the same noise characteristics. This can be achieved by a well-established electrical connection between the two nodes. In some embodiments, ground node V.sub.ss on transmitter 102 and ground node V.sub.ss on receiver 104 can be the same node. Ideally, amplifier+sampler 116 outputs signal 118 which is an exact copy of signal 118. However, the quality of reference voltage 120 can directly affect the accuracy of signal 118, which can be affected by various noises associated with receiver signal 118 and reference voltage 120, as well as various DC offsets associated with amplifier/sampler 116.

(13) Note that transmitter 102 also includes a coupling circuit 122 between signal 118 and V.sub.ss for coupling signal 118 to V.sub.ss, so that signal 118 tracks the V.sub.ss noise. Moreover, transmitter 102 includes a decoupling circuit 124 between signal-generating circuit 108 and V.sub.dd for decoupling signal 118 from V.sub.dd, so that signal 118 is isolated from the V.sub.dd noise. In some embodiments, decoupling circuit 124 is an on-chip voltage regulator which is configured to generate a regulated voltage for signal-generating circuit 108, and to decouple signal-generating circuit 108, and hence signal 118 from V.sub.dd noise. More detail of circuits 122 and 124 is provided below.

(14) Additionally, receiver 104 includes a coupling circuit 126 between reference voltage 120 and the ground node V.sub.ss for coupling reference voltage 120 to V.sub.ss, so that reference voltage 120 tracks the noise associated with V.sub.ss (referred to as V.sub.ss noise). Also note that reference voltage generator 114 is coupled between reference voltage 120 and a positive node of the power supply V.sub.dd to decouple reference voltage 120 from V.sub.dd, so that reference voltage 120 is also isolated from the noise associated with V.sub.dd (referred to as V.sub.dd noise). More detail of these circuits is provided below.

(15) Note that in addition to the components illustrated in FIG. 1, transmitter 102 and receiver 104 may also include other components related to other functions. In some embodiments, receiver 104 further includes circuitries for initializing and calibrating amplifier/sampler 116, and for calibrating the DC level of reference voltage 120, which are described in more detail below. Moreover, although only a single signal 118 is shown being transmitted from transmitter 102 to receiver 104, in many cases there may be multiple signals transmitted from transmitter 102 to receiver 104, and communication system 100 may have multiple amplifiers/samplers for handling such multiple signals. Additionally, one or more signals may be transmitted from receiver 104 to transmitter 102, as indicated by the dashed arrow representing optional signal(s) 130.

(16) Transmitter 102 and receiver 104 may be located on the same integrated circuit, or they can be located on different integrated circuits. In other embodiments, transmitter 102 and receiver 104 may be located on separate modules (e.g., separate cards) coupled by one or more buses.

(17) Note that signal 118 may be a digital or analog signal, or any general signal capable of communicating information. In some embodiments, signal 118 is a digital signal associated with memory operations. In these embodiments, signal 118 can include read/write data, a control signal, an address signal, and a clock signal. In specific embodiments, this digital signal is a binary signal comprising 1's and 0's.

(18) Tracking Noise in the Reference Voltage

(19) FIG. 2 illustrates a single-ended memory system 200 which provides circuits for tracking noise in a reference voltage generated on the receiver side of memory system 200. Note that single-ended memory system 200 is an exemplary embodiment of single-ended communication system 100. However, any circuit and technique described in conjunction with memory system 200 is applicable to both memory system implementations and non-memory system implementations of communication system 100, and not limited to the specific embodiment of FIG. 2.

(20) More specifically, memory system 200 includes a memory controller 202, a memory device 204, and a link 206 which act as transmitter 102, receiver 104, and signal channel 106, respectively. In some embodiments, memory device 204 is a dynamic random-access memory (DRAM) device. However, memory device 204 can include other types of memory devices. Note that circuit components in memory controller 202 receive power from a power supply having a positive node denoted as V.sub.dd.sub._Ctrl. Moreover, some or all signals in memory controller 202, including the power supply, are referenced to the same ground node, denoted as V.sub.ss.sub._Ctrl. We refer to such a signal configuration as ground signaling.

(21) Further referring to FIG. 2, resistance R.sub.u, resistance R.sub.d, and a switch 208 on memory controller 202 constitute a signal-generating circuit, such as signal-generating circuit 108 in FIG. 1. In the embodiment shown, a single-ended signal Vc is generated at node 210 which has a value determined by the position of switch 208. More specifically, when switch 208 is connected to the upper resistance R.sub.u, signal Vc has a value substantially equal to Vs/2, wherein Vs is an on-chip generated voltage at node 212. On the other hand, when switch 208 is connected to the lower resistance R.sub.d, signal Vc has a value substantially equal to the ground reference V.sub.ss.sub._Ctrl. Hence, signal Vc at node 210 can switch between V.sub.ss.sub._Ctrl, which represents 0 or LOW, and Vs/2, which represents 1 or HIGH. Note that a circuit for generating the single-ended signal Vc on controller 202 is not limited to the particular embodiment shown and many modifications and variations to the described circuit will be apparent to one of ordinary skill in the art.

(22) In one embodiment, Vs is generated based on V.sub.dd.sub._Ctrl by a voltage regulator 214 which is coupled between V.sub.dd.sub._Ctrl and node 212. Voltage regulator 214 may be used to isolate Vs from noise associated with V.sub.dd.sub._Ctrl (or V.sub.dd.sub._Ctrl noise), thus acting as decoupling circuit 124 in FIG. 1. More detail of voltage regulator 214 is provided below. However, in some embodiments, Vs is generated externally to memory controller 202 and supplied to memory system 200.

(23) As illustrated in FIG. 2, signal Vc is transmitted by a transmitting circuit 216 over channel 206, and received by a receiving circuit 218 on memory device 204 as a received signal V.sub.LINE at node 220, which is an input to an amplifier+sampler 222. In one embodiment, the path between nodes 210 and 220 is an absolutely transparent signal path, e.g., a wire, so that signal V.sub.LINE is substantially identical to signal Vc from DC to high frequencies. In this embodiment, signal V.sub.LINE and signal Vc have the same AC noise characteristics.

(24) Also in memory device 204, an adjustable current source I.sub.bias and an adjustable resistance R.sub.ref, which are coupled in series between a positive power supply node V.sub.dd.sub._Dram and a ground node V.sub.ss.sub._Dram, constitute a reference voltage generating circuit, such as reference voltage generator 114 in FIG. 1. In the embodiment shown, a reference voltage V.sub.ref is generated at node 224 between current source I.sub.bias and resistance R.sub.ref, wherein node 224 is a second input to amplifier+sampler 222. Hence, reference voltage V.sub.ref has a DC value determined by V.sub.dd.sub._Dram, I.sub.bias, and R.sub.ref, and can be controlled by adjusting I.sub.bias. For example, V.sub.ref increases when I.sub.bias is increased, and decreases when I.sub.bias is decreased (assume R.sub.ref is unchanged). Note that the reference voltage generating circuit in memory device 204 is not limited to the particular embodiment shown, and many modifications and variations to the illustrated embodiment will be apparent to one of ordinary skill in the art.

(25) Note that because node 224 is coupled between V.sub.dd.sub._Dram and V.sub.ss.sub._Dram, V.sub.ref can be corrupted by noises associated with both V.sub.dd.sub._Dram and V.sub.ss.sub._Dram (referred to as V.sub.dd.sub._Dram noise and V.sub.ss.sub._Dram noise). In one embodiment, current source I.sub.bias by design (which is partly due to its high impedance) decouples node 224 and hence V.sub.ref from V.sub.dd.sub._Dram noise at substantially all frequencies, thereby achieving noise isolation from V.sub.dd.sub._Dram in V.sub.ref. Moreover, by providing a coupling capacitance C.sub.1 between node 224 and V.sub.ss.sub._Dram, the embodiment of FIG. 2 allows V.sub.ref to exclusively track V.sub.ss.sub._Dram noise in the high-frequency range. For the low- to mid-frequency range, current source I.sub.bias has particularly high impedance by design which forces node 224 to strongly couple to V.sub.ss.sub._Dram (i.e., the ground). Consequently, node 224, and hence V.sub.ref, can track V.sub.ss.sub._Dram noise in a full frequency range.

(26) Ideally, V.sub.LINE and V.sub.ref have substantially the same noise characteristics; thus, the noises in both signals become common mode noise at the inputs of a differential amplifier in amplifier+sampler 222. This can be achieved in the embodiment of FIG. 2 if V.sub.LINE is also isolated from V.sub.dd.sub._Dram noise while exclusively tracking V.sub.ss.sub._Dram noise. In the embodiment illustrated in FIG. 2, V.sub.LINE can track V.sub.ss.sub._Dram noise through a coupling capacitance C.sub.2 between node 220 and V.sub.ss.sub._Dram. However, V.sub.LINE is a received copy of Vc generated at node 210 in memory controller 202; therefore, any noise present in Vc can be copied into V.sub.LINE. Consequently, to ensure that V.sub.LINE and V.sub.ref have the same noise characteristics, it is necessary to ensure that Vc also exclusively tracks noise in V.sub.ss.sub._Ctrl while being isolated from noise in V.sub.dd.sub._Ctrl.

(27) Note that the above statement assumes that the noise spectra in V.sub.ss.sub._Ctrl and V.sub.ss.sub._Dram are identical. This result, however, is not automatic because V.sub.ss.sub._Ctrl noise and V.sub.ss.sub._Dram noise can be different. To ensure that they have the same noise characteristics, some embodiments provide low impedance coupling between V.sub.ss.sub._Ctrl and V.sub.ss.sub._Dram so that V.sub.ss.sub._Ctrl noise is substantially identical to V.sub.ss.sub._Dram noise. In one embodiment, V.sub.ss.sub._Ctrl and V.sub.ss.sub._Dram are directly coupled by a wire.

(28) However, embodiments of this disclosure generally do not require the noise spectra in V.sub.dd.sub._Ctrl and V.sub.dd.sub._Dram to be identical, because the described embodiments ensure that signals Vc, V.sub.LINE and V.sub.ref are all decoupled from V.sub.dd noises. Generally, memory controller 202 and memory device 204 may work at different supply voltages (when ground referencing is assumed). In other words, V.sub.dd.sub._Ctrl and V.sub.dd.sub._Dram may be different in both DC values and noise characteristics. Note that because the design of memory system 200 has a high tolerance to power supply noise, a designer may take advantage of such a design to save system costs by allowing more supply noise.

(29) We now describe techniques for making Vc track V.sub.ss.sub._Ctrl noise while being isolated from V.sub.dd.sub._Ctrl noise on memory controller 202. By design, when switch 208 is connected to R.sub.d (i.e., when Vc is LOW), tracking V.sub.ss.sub._Ctrl noise and isolation from V.sub.dd.sub._Ctrl noise can be simultaneously achieved in Vc at node 210. However, when switch 208 is connected to R.sub.u (i.e., when Vc is HIGH), additional features in the embodiment of FIG. 2 ensure that Vc tracks V.sub.ss.sub._Ctrl noise while isolated from V.sub.dd.sub._Ctrl noise. More specifically, V.sub.dd.sub._Ctrl noise can be represented as a noise current I.sub.1 flowing from V.sub.dd.sub._Ctrl to V.sub.ss.sub._Ctrl (from a small signal perspective). Typically, a bypass circuit, such as a bypass capacitor C.sub.3 coupled in parallel with noise current I.sub.1, can reduce the V.sub.dd.sub._Ctrl noise generated due to noise current I.sub.1 at high-frequency by coupling V.sub.dd.sub._Ctrl and V.sub.ss.sub._Ctrl. However, this bypass circuit becomes insufficient to reduce V.sub.dd.sub._Ctrl noise at a low- to mid-frequency range, in particular when near a DC level.

(30) In one embodiment, voltage regulator 214 is configured to generate Vs as a low noise, regulated version of V.sub.dd.sub._Ctrl. In particular, voltage regulator 214 may employ a noise filter which specifically blocks V.sub.dd.sub._Ctrl noise in the low- to mid-frequency range. More details of voltage regulator 214 are provided in U.S. Patent Application No. 61/530,775, entitled On-chip Regulator with Variable Load Compensation, by inventors Brian Leibowitz, Michael Bucher, Lei Luo, Charles Huang, Amir Amirkhany, and Huy Nguyen, filed on 2 Sep. 2011, which is hereby incorporated by reference. By combining bypass capacitor C.sub.3 and voltage regulator 214, memory controller 202 generates Vs which is isolated from V.sub.dd.sub._Ctrl noise in a full frequency range. This ensures that Vc is isolated from V.sub.dd.sub._Ctrl noise when switch 208 is connected to R.sub.u,

(31) To ensure that Vs tracks V.sub.ss.sub._Ctrl noise when switch 208 is connected to R.sub.u, an embodiment of memory controller 202 provides a coupling capacitor C.sub.4 between node 212 and V.sub.ss.sub._Ctrl. Note that C.sub.4 provides a low impedance path for high-frequency V.sub.ss.sub._Ctrl noise to be coupled into Vs, and thereby into Vc when Vc is HIGH.

(32) Calibrating a DC Level for a Reference Voltage

(33) FIG. 3 illustrates a single-ended memory system 300 which includes circuits for calibrating a DC level for a reference voltage generated on the receiver side of memory system 300. Note that single-ended memory system 300 is an exemplary embodiment of single-ended communication system 100. However, any circuit and technique described in conjunction with memory system 300 is applicable to both memory system implementations and non-memory system implementations of communication system 100, but is not limited to the specific embodiment of FIG. 3.

(34) As is illustrated in FIG. 3, a memory controller 302 in memory system 300 may be similar to memory controller 202 in FIG. 2, but only a circuit that generates signal Vc is shown within memory controller 302. Signal Vc is transmitted from memory controller 302 over channel 305, and received by a memory device 304 in memory system 300 as signal V.sub.mid at node 306.

(35) Memory device 304 is similar to memory device 204 in FIG. 2, but includes additional circuits for calibrating a reference voltage generated on memory device 304. More specifically, memory device 304 includes a reference voltage generator 307 comprising a high-impedance current source I.sub.bias with a variable current and a resistance R.sub.ref coupled between V.sub.dd.sub._Dram and V.sub.ss.sub._Dram, wherein a reference voltage V.sub.ref is produced at node 308 between I.sub.bias and R.sub.ref. A differential amplifier (diff amp) 310 compares a first input coupled to V.sub.ref against a second input coupled to signal V.sub.rxi at node 312, and generates differential outputs which are fed into a sampler 314. Hence, differential amplifier 310 and sampler 314 form a data recovery circuit which may act as the amplifier+sampler 222 in FIG. 2. Note that while FIG. 3 illustrates a differential output scheme for differential amplifier 310, other embodiments can also use a single-ended output scheme.

(36) Moreover, memory device 304 includes calibration circuits for calibrating a DC level for reference voltage V.sub.ref. In one embodiment, these calibration circuits include a set of switches: switch 316 coupled between nodes 308 and 312, switch 318 coupled between nodes 306 and 312 in a first path, and switch 320 coupled between nodes 306 and 312 in a second path. The calibration circuits also include a calibration controller 322 which can control the states of the set of switches by selectively opening or closing each of the switches (the coupling between calibration controller 322 and the set of switches is not explicitly shown but is assumed). In one embodiment, switches 316, 318 and 320 are implemented as parallel PMOS/NMOS switches. For example, a parallel PMOS/NMOS switch controlled by a control bit linen and a parallel PMOS/NMOS switch controlled by a control bit calen are shown in FIG. 3 as implementations for switches 318 and 320, respectively. In this embodiment, calibration controller 322 can control the states of the switches by controlling the respective control bits. Note that other embodiments can use different switch types from the parallel PMOS/NMOS switches.

(37) We now describe a calibration process which includes a sequence of calibration steps that are controlled by calibration controller 322. More specifically, calibration controller 322 controls the calibration process by controlling the states of the set of switches, wherein each switch is configured to be open or closed at a given step of the calibration process.

(38) The calibration process begins by performing an initial calibration of sampler 314 when switch 316 is closed while switches 318 and 320 are open. Note that by opening switches 318 and 320, sampler 314 is isolated from input signal V.sub.mid. Moreover, closing switch 316 shorts nodes 308 and 312 so that both inputs to differential amplifier 310 become V.sub.ref. As a result, the output of sampler 314 depends on DC offsets intrinsic to differential amplifier 310 and sampler 314, but not on either V.sub.mid or V.sub.ref. Hence, during the first calibration step, sampler 314 is calibrated to compensate for such offsets. In one embodiment, sampler 314 can be calibrated by adjusting a string of offset bits 324. A particular setting of offset bits 324 can be used as a correction input to compensate for the offsets associated with sampler 314. This calibration step can be controlled by calibration controller 322 in a control loop comprising sampler 314, calibration controller 322, and adjustable offset bits 324. During calibration, calibration controller 322 receives sampler output 326 and generates an error signal 328 based on output 326. In one embodiment, error signal 328 is generated by comparing output 326 against a predetermined pattern which contains substantially equal numbers of 1's and 0's, for example, a 101010 pattern. The calibration can be iterative until calibration controller 322 determines that error signal 328 is below a predetermined threshold. Note that the calibration resolution may be affected by the number of bits in offset bits 324, and typically the higher the number of offset bits, the more accurate the calibration result becomes. At the end of the calibration, a significant portion of the offsets due to amplifier 310 and sampler 314 are compensated for.

(39) After the initial sampler calibration, the calibration process proceeds to calibrate the DC level of V.sub.ref when switch 320 is closed while switches 316 and 318 are open. During this calibration step, a predetermined calibration pattern 329 is generated on controller 302 and transmitted to device 304. In one embodiment, calibration pattern 329 comprises substantially equal and even numbers of 1's and 0's. Such a calibration pattern has the advantage of minimizing duty-cycle effects during calibration, and enables using an interpolation technique for DC level calibration while avoiding the ripple effect within the pattern. This interpolation technique is described in more detail in conjunction with FIG. 4. In one embodiment, calibration pattern 329 comprises a 1100 pattern.

(40) As illustrated in FIG. 3, calibration pattern 329 becomes calibration pattern 330 or V.sub.mid at node 306, and subsequently passes through a low pass filter (LPF) 332 and becomes V.sub.rxi at node 312. Because LPF 332 attenuates high frequency ripple in calibration pattern 330, the signal received at node 312 comprises primarily a DC level (e.g., Vs/2) and a low amplitude ripple (or a residual ripple 331) of calibration pattern 330. Next, V.sub.rxi comprising the calibration pattern in the form of the residual ripple is compared against V.sub.ref by differential amplifier 310 and sampler 314. The V.sub.ref DC level calibration can also be controlled by calibration controller 322 in a control loop comprising reference voltage generator 307, differential amplifier 310, sampler 314, and calibration controller 322. During calibration, calibration controller 322 receives sampler output 326 and generates an error signal 334 based on output 326. Calibration controller 322 then uses error signal 334 to adjust V.sub.ref by varying I.sub.bias in reference voltage generator 307. The calibration can be iterative until calibration controller 322 determines that error signal 334 is below a predetermined threshold.

(41) FIG. 4 illustrates an interpolation technique for calibrating a V.sub.ref DC level based on residual ripple 331 at node 312. Note that FIG. 4 is described in the scope of memory device 304 in FIG. 3. We start at the upper part of FIG. 4, which illustrates an exemplary residual ripple 331 in a full period. Note that an ideal DC value of V.sub.ref is at midway between the maximum value (denoted as V.sub.ref.sub._max) and the minimum value (denoted as V.sub.ref.sub._min) of residual ripple 331. Hence, a target value of V.sub.ref, denoted as V.sub.ref.sub._tar, can be computed as (V.sub.ref.sub._max+V.sub.ref.sub._min)/2. Therefore, calibration of V.sub.ref can be converted into calibrations of V.sub.ref.sub._max and V.sub.ref.sub._min. Note that these two calibrations can be performed in any order. Note that when a signal HIGH is represented by Vs/2 on memory controller 302, V.sub.ref.sub._tar may be substantially equal to Vs/4.

(42) Referring back to FIG. 3, note that the value of V.sub.ref at node 308 is adjusted by varying I.sub.bias, such that decreasing I.sub.bias decreases the V.sub.ref value and increasing I.sub.bias increases the V.sub.ref value. Based on these notions, we refer back to FIG. 4.

(43) In one embodiment, the calibration of V.sub.ref.sub._max first initializes V.sub.ref to be greater than the expected V.sub.ref.sub._max value, for example, as V.sub.ref.sub._init1. Because the residual ripple is sufficiently reduced by the LPF 332, V.sub.ref.sub._max is typically only slightly greater than the value of Vs/2. Hence, V.sub.ref.sub._init1 can be set to be reasonably higher than Vs/2. Based on the configuration of differential amplifier 310, this initial value of V.sub.ref would cause sampler 314 to output predominantly 0's.

(44) Next, the calibration of V.sub.ref.sub._max begins to decrease V.sub.ref value from V.sub.ref.sub._init1 by decreasing I.sub.bias, which causes V.sub.ref to be lowered toward V.sub.ref.sub._max. While doing so, the calibration process continues to monitor the sampler output pattern. Note that as long as V.sub.ref is greater than V.sub.ref.sub._max, the sampler output pattern will not change significantly. However, when V.sub.ref is decreased to substantially equal V.sub.ref.sub._max, the sampler output pattern may start to change. We look at two scenarios when V.sub.ref is decreased to V.sub.ref.sub._max.

(45) In the first scenario, the sampling times of sampler 314 are indicated in the upper part of FIG. 4 by arrows 402 and 404. Note that these sampling times almost coincide with the maximum and minimum locations of residual ripple 331. Hence, as soon as V.sub.ref is decreased to V.sub.ref.sub._max, the sampler output pattern begins to change and any further decrease of V.sub.ref (i.e., by one uptick of I.sub.bias) will cause the sampler output to reverse from predominantly 0's to predominantly 1's. At this point, the calibration process can record the I.sub.bias value and/or corresponding V.sub.ref as the determined V.sub.ref.sub._max.

(46) The second scenario is illustrated in the lower part of FIG. 4 which is a copy of the upper part of FIG. 4 but with different sampling positions indicated by arrows 406 and 408. In this scenario, the sampling positions are offset to the left of the maximum and minimum locations of residual ripple 331, wherein the value of V.sub.ref at which the sampling takes place is denoted as V.sub.ref.sub._max. Note that when V.sub.ref is first decreased to V.sub.ref.sub._max, the sampler output pattern does not change as in the first scenario. Instead, V.sub.ref has to be further decreased until V.sub.ref substantially equals V.sub.ref.sub._max when the sampler output begins to change. Similarly to the first scenario, any further decrease of V.sub.ref beyond V.sub.ref.sub._max will cause the sampler output to reverse from predominantly 0's to predominantly 1's. At this point, the calibration process can record the I.sub.bias value and/or corresponding V.sub.ref as the determined V.sub.ref.sub._max.

(47) Note that the calibration of V.sub.ref.sub._min may be performed in a substantially similar manner to the calibration of V.sub.ref.sub._max but in the reverse direction. More specifically, the calibration of V.sub.ref.sub._min can first initialize V.sub.ref to be less than the expected V.sub.ref.sub._min value. Referring back to the upper part of FIG. 4, note that the initial value of V.sub.ref is set to be V.sub.ref.sub._init2. Based on the configuration of differential amplifier 310, this initial value of V.sub.ref would cause sampler 314 to output predominantly 1's.

(48) Next, the calibration of V.sub.ref.sub._min begins to increase V.sub.ref value from V.sub.ref.sub._init2 by increasing I.sub.bias, which causes V.sub.ref to be raised toward V.sub.ref.sub._min. While doing so, the calibration process continues to monitor the sampler output pattern. Note that as long as V.sub.ref is less than V.sub.ref.sub._min, the sampler output pattern will not change significantly. However, when V.sub.ref is increased to substantially equal V.sub.ref.sub._min, the sampler output pattern may start to change.

(49) In the first scenario, the sampling positions of sampler 314 are indicated by arrows 410 and 412. Hence, as soon as V.sub.ref is increased to V.sub.ref.sub._min, the sampler output pattern begins to change and any further increase of V.sub.ref (i.e., by one uptick of I.sub.bias) will cause the sampler output to reverse from predominantly 1's to predominantly 0's. At this point, the calibration process can record the I.sub.bias value and/or corresponding V.sub.ref as the determined V.sub.ref.sub._min.

(50) The second scenario is again illustrated in the lower part of FIG. 4 which has sampling positions indicated by arrows 414 and 416. In this scenario, the sampling positions are again offset to the left of the maximum and minimum locations of residual ripple 331, wherein the value of V.sub.ref at which the sampling takes place is denoted as V.sub.ref.sub._min. Hence, V.sub.ref has to be increased beyond V.sub.ref.sub._min until V.sub.ref substantially equals V.sub.ref.sub._min when the sampler output begins to change. Any further increase of V.sub.ref beyond V.sub.ref.sub._min will cause the sampler output to reverse from predominantly 1's to predominantly 0's. At this point, the calibration process can record the I.sub.bias value and/or corresponding V.sub.ref as the determined V.sub.ref.sub._min.

(51) Once V.sub.ref.sub._max (or V.sub.ref.sub._max) and V.sub.ref.sub._min (or V.sub.ref.sub._min) are calibrated, V.sub.ref.sub._tar (V.sub.ref.sub._tar) can be computed as the average of the two values. Note that the first and second scenarios of the sampling clock demonstrate that if the residual ripple pattern has a good linearity, then the final computed V.sub.ref DC level is always positioned in the middle of the residual ripple pattern with substantially the same value (i.e., V.sub.ref.sub._tar=V.sub.ref.sub._tar), regardless of where the pattern is sampled. Furthermore, it is assumed that the original calibration pattern 329 comprises substantially equal and even numbers of 1's and 0's. Note that this interpolation technique of FIG. 4 has high tolerance to the residual ripple, which allows smaller capacitance and resistance to be used in LPF 332 to save chip real-estate.

(52) Referring back to FIG. 3, after calibrating the V.sub.ref DC level, the calibration process performs a final calibration of sampler 314 using the calibrated V.sub.ref value at node 308 and the same switch configurations as the V.sub.ref calibration. This calibration step can also be controlled by calibration controller 322 which receives sampler output 326 and generates an error signal 328 based on output 326. In one embodiment, error signal 328 is generated by comparing output 326 against the predetermined calibration pattern. Error signal 328 is then used to adjust offset bits 324 in fine granularity (e.g., by only adjusting the least significant bits) to compensate for residual offsets associated with differential amplifier 310, sampler 314, and any other self-generated offset error. This calibration can be iterative until calibration controller 322 determines that error signal 328 is below a predetermined threshold. At the end of this calibration step, an even higher resolution of sampler 314 is obtained and the calibration process is complete.

(53) Note that the above described calibration technique can be carried out exclusively on the receiver side of system 300, without collaboration from the transmitter side of system 300 (e.g., no need to send information back to the transmitter side). Moreover, the calibration technique improves the calibration range and resolution by using both the receiver front-end amplifier and samplers to calibrate the V.sub.ref DC level. More specifically, differential amplifier 310 and reference voltage generator 307 are initially used to correct the large V.sub.ref DC offset, and sampler 314 is then calibrated to correct the residual V.sub.ref DC offset in fine granularity and to correct the individual sampler's self-generated offset error. Note that although only one sampler is shown in system 300, the described technique is applicable to systems comprising multiple samplers.

(54) Upon completing the calibration process, the system can enter the normal operation mode by closing switch 318 and opening switches 316 and 320. In one embodiment, calibration controller 322 can be deactivated during normal operation. Note that calibration controller 322 can activate a new calibration process periodically or under specific circumstances. In one embodiment, a calibration process is performed during system initialization.

(55) FIG. 5 presents a flowchart illustrating an exemplary process for calibrating the DC level of the reference voltage in a single-ended signaling system comprising a transmitter and a receiver. The process begins by performing an initial calibration of a sampler on the receiver used to sample the difference between a received signal and the reference voltage being calibrated while isolating the reference voltage from the sampler (step 502). In one embodiment, this calibration step involves adjusting a string of offset bits associated with the sampler as described above. Note that if there are multiple samplers, step 502 can be repeated for each of the samplers. Next, the calibration process calibrates the DC level of the reference voltage using the calibrated sampler and a predetermined calibration pattern comprising balanced 1's and 0's (step 504). In one embodiment, this calibration step involves using the interpolation technique as described above. The calibration process then performs a final calibration of the sampler using the calibrated reference voltage and the same predetermined calibration pattern as in step 504 (step 506). In one embodiment, this calibration step involves fine-tuning the same string of offset bits associated with the sampler as described above.

(56) Although the noise-tracking technique for a reference voltage and the DC level calibration technique for a reference voltage are described separately in conjunction with FIG. 3 and FIG. 4, these techniques and associated circuits can be combined into the same single-ended signaling system, such as a single-ended memory system. Such a system is capable of generating an accuracy reference voltage which is also immune to supply noise.

(57) The above-described embodiments are applicable to different types of memory devices, for example, memory devices adhering to double data rate (DDR) standards, such as DDR2, DDR3, and DDR4, and future generations of memory devices, such as GDDR5, XDR, Mobile XDR, LPDDR, LPDDR2 and LPDDR3. However, these embodiments may differ in a number of respects, such as in the structure of the interface logic, the number of bank groups, and the number of memory banks within each bank group in a given memory device.

(58) The preceding description was presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Thus, the disclosed embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present description. The scope of the present description is defined by the appended claims.

(59) Also, some of the above-described methods and processes can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium. Furthermore, the methods and apparatus described can be included in, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices.