Amplifier circuit with improved accuracy

Abstract

An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.

Claims

1. An amplifier circuit, comprising: a cascade of amplifier stages, providing an RSSI-sum as a measure for the level of a signal at the input of the cascade, the cascade of amplifier stages having a large signal behavior defined by a difference between a maximum contribution defined by a clipping level of one of the amplifier stages and a minimum contribution corresponding to an output voltage of one of the amplifier stages absent an input voltage, each of the amplifier stages of the cascade of amplifier stages having a small signal gain and a gain control input; a control line configured to provide a control signal to the gain control input of each of the amplifier stages; a feedback circuit having an input port for a reference signal, the feedback circuit configured to generate the control signal in response to the reference signal and an output of the cascade of amplifier stages; and a feedback loop connecting the feedback circuit to the control line, the feedback loop configured to fix the large signal behavior of the cascade of amplifier stages and control the small signal gain of each of the amplifier stages in response to the control signal.

2. The amplifier circuit of claim 1, wherein: each amplifier stage provides a contribution to the RSSI-sum; and at least one amplifier stage is a clipping amplifier and provides the maximum contribution to the RSSI-sum.

3. The amplifier circuit of claim 1, wherein the amplifier stages: are bipolar differential stages each having a tail current; and are controlled by adjusting their tail currents.

4. The amplifier circuit of claim 1, wherein: the first amplifier stage of the cascade or a further amplifier stage not being an element of the cascade provides the minimum contribution.

5. The amplifier circuit of claim 1, wherein: an amplifier stage provides the minimum contribution and another amplifier stage provides the maximum contribution; and the difference between the maximum contribution and the minimum contribution equals the reference signal.

6. The amplifier circuit of claim 1, wherein the reference signal has a temperature dependency chosen to eliminate the temperature dependency of the amplifier circuit.

7. The amplifier circuit of claim 6, wherein the reference signal is a PTAT signal.

8. The amplifier circuit of claim 1, wherein the reference signal is a reference voltage.

9. The amplifier circuit of claim 1, wherein the amplifier circuit is: an RSSI-system or a temperature compensation circuit for another amplifier circuit.

10. The amplifier circuit of claim 1, further comprising: two or more amplifiers, where the minimum contribution and/or the maximum contribution are generated by the two or more amplifier stages to increase accuracy.

11. The amplifier circuit of claim 1, further comprising a summing circuit with one resistor per amplifier stage, where a resistor is connected between a respective output port of the amplifier stage and a common node.

Description

SHORT DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows an embodiment of an amplifier circuit AC comprising a chain of amplifier stages A.sub.1, A.sub.2, . . . A.sub.n.

(2) FIG. 2 shows an amplifier circuit with an additional amplifier stage A.sub.0.

(3) FIG. 3 shows an an amplifier circuit where the first amplifier stage A.sub.1 is utilized for obtaining VS.sub.0.

(4) FIG. 4 shows an amplifier circuit where two amplifier stages contribute to the determination of an average value for VS.sub.clip.

(5) FIG. 5 shows an amplifier stage.

(6) FIG. 6 shows the dependency of VS.sub.i.

DETAILED DESCRIPTION

(7) FIG. 1 shows an embodiment of an amplifier circuit AC comprising a cascade CAS of amplifier stages A.sub.1, A.sub.2, . . . A.sub.n. Each amplifier stage A.sub.i contributes to the total RSSI-sum VS.sub.i. To obtain the total RSSI-sum VS.sub.i, the individual contributions are summed. The first amplifier stage A1 receives an input signal IN. The input signal is amplified and fed to the input of the respective next amplifier stage of the cascade CAS.

(8) Each amplifier stage A.sub.1, A.sub.2, . . . A.sub.n comprises an input for a control signal CRTL. Via the control signal CRTL, the gain of each amplifier stage is controlled. The amplifier circuit AC further comprises a feedback circuit FC having an input port P.sub.in. Via a feedback loop FL, the feedback circuit FC is connected to a control line feeding the control signal CRTL to the individual amplifier stages. Thus, via the control line CRTL, the amplifier stages, e.g. their respective gain, is controlled. Via the input port P.sub.in, the feedback circuit FC receives a reference signal REF. The feedback loop FL enables accurately fixing the large signal behavior of the amplifier circuit AC by controlling the small signal gain of the amplifier stages. As a result, the slope of the VS.sub.i vs. log (V.sub.IN)-curve is fixed and the accuracy of the amplifier circuit is increased.

(9) FIG. 2 shows an embodiment of an amplifier circuit AC where the feedback circuit FC comprises a fully limiting amplifier stage A.sub.n+1 and an additional amplifier stage A.sub.0. The additional amplifier stage A.sub.0 has a signal input but no signal is fed into the signal input of the additional amplifier stage A.sub.0. Thus, the additional amplifier stage A.sub.0 provides the minimum contribution VS.sub.0 while the fully limiting amplifier stage A.sub.n+1 provides the maximum contribution VS.sub.clip. Further, a feedback circuit FC comprises a subtraction circuit SUB for evaluating the difference VS.sub.clipVS.sub.0. Thus, an output of the subtraction circuit SUB provides the large signal behavior VS.sub.clipVS.sub.0. Via the feedback loop FL that may comprise another amplifier A.sub.X and another subtraction circuit SUB2, the differences VS.sub.CLIPVS.sub.0 is set to the reference signal REF.

(10) The feedback circuit FC may comprise a low pass filter LPF to evaluate the average RSSI contribution of the fully limiting amplifier stage A.sub.n+1.

(11) FIG. 3 shows an embodiment of an amplifier circuit where the first amplifier stage A.sub.1 is utilized as an amplifier stage for obtaining VS.sub.0. Therefore, the output of the first amplifier stage is fed to the subtraction circuit SUB.

(12) FIG. 4 shows an embodiment of an amplifier circuit AC where the RSSI contribution VS.sub.clip is obtained by evaluating the average value of two additional fully limiting amplifier stages A.sub.n+1, A.sub.n+2. For that, the feedback circuit comprises an adding circuit ADD and a division-by-two circuit between the addition circuit ADD and the low pass filter LPF.

(13) FIG. 5 shows an embodiment of amplifier stage AS. The amplifier stage comprises an input port P.sub.IN and an output P.sub.OUT. The amplifier stage AS may work with balanced signals. Via a control port P.sub.CRTL, the gain of the amplifier stage AS can be adjusted. The voltage between a signal port P.sub.SL, and ground can be utilized as the level information provided by each amplifier stage. Via a supply port P.sub.SUP, the amplifier stage AS can be powered. An output port P.sub.OUT can be used to connect the output of the amplifier stage to the input port P.sub.IN of the respective next amplifier stage of the cascade. Via a bias port P.sub.BIAS, a biasing signal can be applied to the amplifier stage AS. T1 and T2 denote transistors that may be NMOS transistors.

(14) However, other circuits for the amplifier stages AS are also possible.

(15) FIG. 6 shows the influence of the input level signal V.sub.IN, or the respective logarithm of the input signal V.sub.IN, on the RSSI-sum VS.sub.i. In the RSSI range RSSI-R, the slope of the RSSI-sum is mainly constant and determined by the ratio: (VS.sub.clipVS.sub.0)/log(A.sub.V), i.e. by the ratio: large signal behavior divided by the logarithm of the small signal gain.

(16) By improving the accuracy of the small signal gain and of the large signal behavior, an improved accuracy of the slope and, thus, of the accuracy of a corresponding amplifier circuit is obtained.

(17) An amplifier circuit is not limited to the embodiments described in the specification or shown in the figures. Amplifier circuits comprising further circuit elements such as further amplifier stages are also comprises by the present invention.

LIST OF REFERENCE SYMBOLS

(18) A1, . . . An: amplifier stage AC: amplifier circuit ADD: adding circuit A.sub.n+1, A.sub.0: additional amplifier stages Ax: amplifier of the feedback loop CAS: cascade of amplifier stages CTRL: control line conducting a control signal to the amplifier stages FC: feedback circuit FL: feedback loop IN: input of the cascade log A.sub.V: large signal behavior LPF: low pass filter P.sub.BIAS: bias port of an amplifier stage PCRTL: control port of the amplifier stage PIN: input port POUT: output port of an amplifier stage PSL: signal port providing level information of an amplifier stage PSUP: supply port of an amplifier stage REF: reference signal R.sub.G,1, R.sub.G,2, R.sub.D,1, R.sub.D,2: resistive elements of an amplifier stage RSSI-R: RSSI range SUB, SUB2: subtraction circuit VS.sub.i: RSSI-sum T1, T2, T3: transistor V.sub.IN: input signal of the amplifier circuit VS.sub.clipVS.sub.0: large signal behavior