Germainium pin photodiode for integration into a CMOS or BICMOS technology

Abstract

A diode comprising a light-sensitive germanium region which is totally embedded in silicon and forms with the silicon a lower interface and lateral interfaces, wherein the lateral interfaces do not extend perpendicularly, but obliquely to the lower interface and therefore produce a faceted form.

Claims

1. A lateral PIN diode, comprising a light-sensitive germanium region which is totally embedded in silicon and forms with the silicon a lower interface and lateral interfaces, wherein the lateral interfaces do not extend perpendicularly, but obliquely to the lower interface and therefore produce a faceted form, wherein the germanium region has a portion which is only intrinsically conductive and which extends under an insulating strip disposed on the silicon, the lateral extension of said strip determining the intrinsic region of the diode, and wherein doped germanium and silicon regions laterally adjoin the intrinsically conductive portion of the germanium region and extend laterally from the intrinsic germanium region of the diode to a diode edge defined by an insulator.

2. The diode according to claim 1, wherein the germanium region tapers from the lower interface with increasing distance from the lower interface, the lateral interfaces preferably being produced by epitaxial growth of the germanium region on a silicon base selectively with respect to an insulating layer.

3. The diode according to claim 2, wherein a total height of the diode above the lower interface is 700 nm at most, said height including a maximum thickness of the germanium region above the lower interface and a thickness of a portion of the silicon layer above the germanium region.

4. The diode according to claim 3, wherein the total height is 500 nm at most.

5. The diode according to claim 4, wherein the thickness of the portion of the silicon layer portion above the germanium region, measured from the planar, facetless part of an upper interface between the germanium region and the silicon, ranges between 20 and 150 nm.

6. The diode according to claim 5, wherein a metal silicide layer is formed on the doped silicon regions.

7. The diode according to claim 6, wherein spacers laterally adjoin the insulating strip and define a spacing between the insulating strip and the metal silicide layer.

8. An opto-electronic component, comprising a diode according to claim 1 and a light guiding component monolithically integrated with said diode.

9. The opto-electronic component according to claim 8, wherein the light guiding component is a waveguide made of silicon and forming the lower interface with the germanium region of the diode.

10. The diode according to claim 1, wherein a total height of the diode above the lower interface is 700 nm at most, said height including a maximum thickness of the germanium region above the lower interface and a thickness of a portion of the silicon layer above the germanium region.

11. The diode according to claim 10, wherein the total height is 500 nm at most.

12. The diode according to claim 10, wherein the thickness of the portion of the silicon layer portion above the germanium region, measured from the planar, facetless part of an upper interface between the germanium region and the silicon, ranges between 20 and 150 nm.

13. The diode according to claim 1, wherein a metal silicide layer is formed on the doped silicon regions.

14. The diode according to claim 13, wherein spacers laterally adjoin the insulating strip and define a spacing between the insulating strip and the metal silicide layer.

15. An opto-electronic component, comprising a diode according to claim 2 and a light guiding component monolithically integrated with said diode.

16. The opto-electronic component according to claim 15, wherein the light guiding component is a waveguide made of silicon and forming the lower interface with the germanium region of the diode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features and advantages of the PIN photodiode according to the invention shall now be described in more detail reference to the attached Figures and with a description of further embodiments.

(2) FIG. 1 shows a first stage of an example of a process for producing an embodiment of a diode structure.

(3) FIGS. 2-5 show the second to fifth stage of the process for producing the embodiment of the diode structure.

(4) FIG. 6 shows a sixth stage of the process for producing the embodiment of the diode structure, and at the same time the completed embodiment of the diode structure according to the invention.

DETAILED DESCRIPTION

(5) FIGS. 1 to 6 illustrate, with schematic cross-sectional views in different stages of the process, an example of a process for producing an embodiment of the PIN photodiode according to the invention, and they also illustrate the features of such a PIN photodiode. All the Figures show structural cross-sections perpendicular to the direction of incidence of the light.

(6) An embodiment of a lateral PIN photodiode according to the invention shall firstly be described below with reference to FIGS. 4 and 6.

(7) On a monocrystalline waveguide 1, produced on a silicon dioxide layer 2, there is a germanium layer 5 which is covered laterally and above by a silicon layer 7. An important aspect is the oblique edge of a lateral interface 6 formed by the germanium layer 5 and the silicon layer, which is referred to in the following as a germanium-silicon interface, and the formation of which shall be described further below. The entire diode structure is laterally enclosed by an insulator layer 3, preferably by a silicon oxide layer. The diode structure is covered with an insulating strip 8, which, as explained in more detail below, allows production of an intrinsic germanium region 5a which is self-aligned with p- and n-doped regions 9 and 10. Lateral insulator layer spacers 11 are optional. The benefit they provide is to increase reliability in preventing undesired diode leakage currents which would occur if the metal silicide layer 12 formed on the p- and n-doped regions 9 and 10 comes into contact with the intrinsic region 5a.

(8) An example of a process for producing the PIN photodiode as just described shall now be described with reference to all the Figures.

(9) FIG. 1 shows a first stage of an example of a process for producing an embodiment of a diode structure. In this stage, selective epitaxial growth has resulted in a germanium layer 4 being formed in a window in an insulator layer 3. In this example, the insulator layer is a silicon oxide layer. The germanium layer 4 and also a portion of the insulator layer 3 lie on a previously produced monocrystalline silicon waveguide 1 located on a silicon oxide layer 2. The thickness of the germanium layer 4 may be considerably thicker here than the desired final thickness of the germanium region of the finished photodiode. Facet formation on the upper side of germanium layer 4, typical for selective Ge growth on (100) oriented silicon, is indicated in FIG. 1 by oblique edges. The thickness of insulator layer 3 above waveguide 1 is chosen such that it corresponds to the desired total detector height, compatible with CMOS and BiCMOS.

(10) FIG. 2 shows a second stage in production of the diode structure embodiment. Many chemicals that are used in the CMOS or BiCMOS process for cleaning or etching steps do not have sufficient selectivity to germanium, i.e., they strongly attack the grown germanium layer, which can greatly complicate the integration of the production process for the germanium PIN photodiodes into the CMOS or BiCMOS process. A gas phase etch-back process is therefore used as an alternative solution in the present embodiment. This gas phase etch-back process is already known per se, namely from the publication by Y. Yamamoto et al, in Thin Solid Films, Vol. 520 (2012) pp. 3216-3221. It can be carried out in the same production plant immediately after producing germanium layer 4 and requires no additional cleaning steps prior to the subsequent steps for completing the photodiode.

(11) FIG. 2 shows the diode structure after such a gas phase-etch-back process. The etching process is controlled in such a way that the final height of the processed germanium layer, marked with reference sign 5 in the Figures, over the waveguide is set. In the etching process, a characteristic structure having a lateral facet 6 is formed, as indicated in FIG. 2. As described in Y. Yamamoto et al, Thin Solid Films, Vol. 520 (2012) pp. 3216-3221, the process sequence depositing a relatively thick germanium layer and subsequent etching back allows the production of thin Ge layers having a lower defect density than can otherwise be achieved for thicker layers. This approach is important for achieving a low dark current level in the photodiodes.

(12) FIGS. 3 and 4 show a third and a fourth stage in production of the embodiment of the diode structure. FIG. 3 shows the diode structure after deposition of a silicon layer 7 by non-selective silicon epitaxy. FIG. 4 shows the diode structure after subsequent planarization by chemical-mechanical polishing (CMP). It is important that after these steps of the process, the germanium region of the diode is completely enclosed by silicon. This allows unrestricted application of the normal cleaning and wet etching processes of CMOS or BiCMOS technology and use of the same metal silicide for CMOS or BiCMOS components and photodiodes.

(13) FIG. 5 shows, as a fifth stage in the production of this embodiment of the diode structure, a phase during self-aligned production of a PIN structure with the aid of an insulating strip 8. The thickness of the latter is chosen such that no doping whatsoever is introduced under the strip during subsequent implantation of p- and n-regions 9 and 10. In FIG. 5, this is graphically indicated by the p- and n-regions being darker than a region 5a lying between the latter and under insulating strip 8. In this way, inner edges of resist masks (not shown) used for p- and n-implantation are positioned directly on insulating strip 8, without variations in the alignment of the resist masks with insulating strip 8 resulting in variations in the desired width of the intrinsic germanium region 5a. The width of the intrinsic germanium region can thus be adjusted very precisely, which is very important for the optical bandwidth.

(14) It is also important that not only the width of the intrinsic germanium region can be adjusted with the width of insulating strip 8, but also the ratio between doped germanium and silicon regions, which can be then exploited for optimizing the bandwidth of the diodes.

(15) FIG. 6 shows, as the sixth stage in production of this embodiment of the diode structure, the final diode structure before production of diode contacts. A metal silicide layer 12 has been produced by self-aligned formation, making optimal use of insulating layer spacers 11 above p- and n-regions 9 and 10. This makes it possible to achieve low contact impedances, which in turn are beneficial for achieving high optical bandwidth.

(16) With the structure achieved here, the contacts normally used in CMOS or BiCMOS processes (e.g. tungsten plugs (not shown)) can be shared to some extent.