Semiconductor device

Abstract

A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Claims

1. A semiconductor device, comprising: a substrate, including a first area and a second area, wherein the first area is closer to a pick-up region of the substrate than the second area; a well, located in the substrate and extending across the first and the second areas; a first MOS element of a first conductivity type in the first area; a second MOS element of the first conductivity type in the second area; and an isolation layer, buried in the substrate and located completely under the well in the first area, wherein the substrate has a second conductivity type, and a first bottom depth of a first electrical conduction path in the substrate in the first area is smaller than a second bottom depth of a second electrical conduction path in the substrate in the second area.

2. The semiconductor device of claim 1, further comprising: a deep well of the first conductivity type in the substrate of the first area, disposed in a manner such that the first bottom depth is smaller than the second bottom depth.

3. The semiconductor device of claim 2, wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The semiconductor device of claim 2, wherein the first conductivity type is P-type and the second conductivity type is N-type.

5. The semiconductor device of claim 1, which comprises an electrostatic discharge (ESD) device.

6. The semiconductor device of claim 5, wherein the ESD device comprises a multi-finger MOS device, and the first MOS element and the second MOS element are parts of the multi-finger MOS device.

7. The semiconductor device of claim 1, wherein the first MOS element and the second MOS element comprise BJT elements, NMOS elements, LDMOS elements, or DDMOS elements.

8. The semiconductor device of claim 1, wherein the first bottom depth of the first electrical conduction path decreases toward the pick-up region.

9. The semiconductor device of claim 8, wherein the first bottom depth of the first electrical conduction path decreases smoothly or stepwise toward the pick-up region.

10. A semiconductor device, comprising: a substrate, including a first area and a second area, wherein the first area is closer to a pick-up region of the substrate than the second area; a well, located in the substrate and extending across the first and the second areas; a first MOS element of a first conductivity type, above a first level in the substrate in the first area; a second MOS element of the first conductivity type, above the first level in the substrate in the second area; and an isolation layer, buried in the substrate in the first area but not extending to the second area, and being completely under the well in the first area, wherein a first distance between the first level and a top of the isolation layer is smaller than a second distance between the first level and a bottom level of the substrate in the second area.

11. The semiconductor device of claim 10, wherein the isolation layer comprises an insulating layer.

12. The semiconductor device of claim 11, wherein the insulating layer comprises silicon oxide or silicon nitride.

13. The semiconductor device of claim 10, wherein the isolation layer comprises a deep well of the first conductivity type.

14. The semiconductor device of claim 13, wherein the first conductivity type is N-type and the second conductivity type is P-type.

15. The semiconductor device of claim 13, wherein the first conductivity type is P-type and the second conductivity type is N-type.

16. The semiconductor device of claim 10, which comprises an electrostatic discharge (ESD) device.

17. The semiconductor device of claim 16, wherein the ESD device comprises a multi-finger MOS device, and the first MOS element and the second MOS element are parts of the multi-finger MOS device.

18. The semiconductor device of claim 10, wherein the first MOS element and the second MOS element comprise BJT elements, NMOS elements, LDMOS elements, or DDMOS elements.

19. The semiconductor device of claim 10, wherein the isolation layer has a substantially uniform thickness from near the pick-up region to apart from the pick-up region.

20. The semiconductor device of claim 10, wherein a thickness of the isolation layer increases toward the pick-up region.

21. The semiconductor device of claim 20, wherein the thickness of the isolation layer increases smoothly or stepwise toward the pick-up region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A and 1B respectively illustrate a top view and an I-I cross-sectional view of a semiconductor device according to an embodiment of this invention.

(2) FIG. 2 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this invention.

DESCRIPTION OF EMBODIMENTS

(3) The following embodiments are intended to further explain this invention but not to limit the scope thereof. For example, though the semiconductor device described in the embodiments is a multi-finger MOS device for ESD, the semiconductor device of this invention may alternatively be a FinFET device. Moreover, although the first and second MOS elements are NMOS elements in the embodiments, they may alternatively be BJT elements, LDMOS (Laterally Diffused MOS) elements, or DDMOS (Double Diffused MOS) elements.

(4) Further, though the first conductivity type is N-type and the second conductivity type is P-type in the embodiments, it is also possible that the first conductivity type is P-type and the second conductivity type is N-type.

(5) FIGS. 1A and 1B respectively illustrate a top view and an I-I cross-sectional view of a semiconductor device according to an embodiment of this invention.

(6) Referring to FIGS. 1A and 1B, the semiconductor device includes a multi-finger MOS device, which includes a P-type substrate 100, a P-well 102 in the substrate 100, an isolation layer 104 in the P-well 102, a plurality of substantially parallel finger gates 110 over the P-well 102, N-type source regions 112a and N-type drain regions 112b disposed in the substrate 100 between the gates 110 and arranged alternately, a P-type pick-up region 114 surrounding the source regions 112a and the drain regions 112b with the isolation layer 104 in between, a silicide layer 116 on the source regions 112a and the drain regions 112b, and an isolation layer 120 buried in the substrate 100 under some edge MOS elements of the multi-finger MOS device.

(7) The substrate 100 may be a bulk substrate, an epitaxy substrate, or a silicon-on-insulator (SOI) substrate. The gates 110 may include doped polysilicon. The dopant concentration of the P-well 102 is higher than that of the P-type substrate 100 but lower than that of the P-type pick-up region 114. The width of each drain region 112b is larger than that of each source region 112a.

(8) In the multi-finger device, the N-type source region 112a and the N-type drain region 112b of each MOS element, the P-well 102, and the P-type substrate 100 form a parasitic BJT 10-n (n=1, 2, . . . ), through which the ESD current is released.

(9) The isolation layer 120 makes the bottom depth of the electrical conduction path in the P-well 102 in the corresponding area smaller than that of the electrical conduction path in the P-well 102 and the substrate 100 in the area without the isolation layer 120. In other words, the distance d1 between the level of the bottoms of the source and drain regions 112a and 112b and the top surface of the isolation layer 120 is smaller than the distance d2 between the above level and the bottom level of the substrate 100 in the area without the isolation layer 120.

(10) At each of the left and right edges of the above multi-finger MOS device, the isolation layer 120 is located under at least one edge MOS element, for example, three edge MOS elements as shown in the figures. The ratio (w/X) of the distance (w) between the pick-up region 114 and the inner border of the isolation layer 120 to the length (X) of the multi-figure device in the arrangement direction of the MOS element is preferably in the range of 0.12 to 0.33.

(11) The isolation layer 120 may include an insulating layer or a deep N-well. As the isolation layer 120 includes a deep N-well, its formation can be easily integrated with usual CMOS process requiring deep wells. The dopant concentration of the deep N-well is lower than that of the N-type source regions 112a and the N-type drain regions 112b. As the isolation layer 120 includes an insulating layer, the insulating layer may include silicon oxide or silicon nitride.

(12) Moreover, although the isolation layer 120 has a substantially uniform thickness from near the pick-up region 114 to apart from the same in this embodiment, it may alternatively have a thickness increasing toward the pick-up region 114 in a manner such that the bottom depth of the overlying electrical conduction path decreases toward the pick-up region 114. Such embodiment is described below in reference of FIG. 2.

(13) Referring to FIG. 2, the thickness of the isolation layer 120 increase smoothly toward the pick-up region 114, while the other parts of the device are the same as those in the precedent embodiment. Alternatively, the thickness of the isolation layer 120 may increase stepwise toward the pick-up region 114.

(14) The above embodiments feature that the isolation layer 120 or 120 decreases the base resistance difference between central MOS elements and edge MOS elements of the multi-finger device. To demonstrate this, the base resistance values (relative values) of the respective BJTs in the multi-finger device shown in FIG. 1A/1B are calculated as Example 1, and those of a corresponding conventional multi-finger device without the deep N-well 120 are calculated as Comparative Example 1 for comparison.

(15) For a conventional multi-finger device (Comparative Example 1) with a structure as shown in FIG. 1A/1B without the deep N-well 120, the resistance R.sub.xy between the pick-up region and a position (x, y) can be calculated with Eq. (1):

(16) $\begin{array}{cc}\frac{1}{R_{\mathrm{xy}}}{}_{x=0}^X\frac{1}{\sqrt{{\left(X-x\right)}^2+y^2}}+{}_{x=0}^X\frac{1}{\sqrt{{\left(X-x\right)}^2+{\left(Y-y\right)}^2}}+{}_{y=0}^Y\frac{1}{\sqrt{x^2+{\left(Y-y\right)}^2}}+{}_{y=0}^Y\frac{1}{\sqrt{{\left(X-x\right)}^2+{\left(Y-y\right)}^2}}& \left(1\right)\end{array}$

(17) For a multi-finger device shown in FIG. 1A/1B of this invention (Example 1), the resistance between the pick-up region 114 and a position (x, y) can be calculated with Eq. (2):

(18) $\begin{array}{cc}\frac{1}{R_{\mathrm{xy}}}k{}_{x=0}^w\frac{1}{\sqrt{{\left(w-x\right)}^2+y^2}}+k{}_{x=0}^w\frac{1}{\sqrt{{\left(w-x\right)}^2+{\left(Y-y\right)}^2}}+k{}_{y=0}^Y\frac{1}{\sqrt{x^2+{\left(Y-y\right)}^2}}+\mathrm{minor}\mathrm{terms},& \left(2\right)\end{array}$
wherein k (<1) is the ratio of the substrate resistance in the area with the deep N-well 120 to that in the area of the P-well 102 without the deep N-well 120, w is defined as above, and the minor terms are integrations over the area without the deep N-well 120.

(19) In Example 1 and Comparative 1, X=33 m, and Y=24 m. In Example 1 of this invention, k=0.98 (=7.23/7.33), and w=4 m. The result of the numerical integrations at the position y=Y/2 for the respective BJT 10-n (n=1, 2, . . . , 18) with different positions x are listed in Table 1:

(20) TABLE-US-00001 TABLE 1 Base resistance R.sub.x,y=Y/2 (relative values) of the respective BJTs BJT No. (x=) 1, 18 2, 17 3, 16 4, 15 5, 14 6, 13 7, 12 8, 11 9, 10 R.sub.x,y=Y/2 of 0.600 0.639 0.669 0.692 0.702 0.708 0.710 0.712 0.713 Example 1 R.sub.x,y=Y/2 of 0.510 0.551 0.581 0.605 0.626 0.643 0.657 0.670 0.681 Comparative Example 1

(21) According to Table 1, the base resistance deviation in Example 1 is merely 17% (=(0.7130.600)/[(0.713+0.600)/2]), while that in Comparative Example 1 is 29%. It is clear that that the isolation layer or deep N-well 120 greatly decreases the base resistance difference between central MOS elements and edge MOS elements of the multi-finger device.

(22) This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.