METHOD FOR PRODUCING A MICROELECTRONIC DEVICE

Abstract

A method for producing a microelectronic device, in particular a MEMS chip device, comprising at least one carrier substrate. At least one electrodynamic actuator made of a metal conductor formed at least largely of copper is applied to the carrier substrate in at least one method step. At least one piezoelectric actuator is applied to the carrier substrate in at least one further method step.

Claims

1-10. (canceled)

11. A method for producing a microelectronic MEMS chip device including at least one carrier substrate, the method comprising the following steps: applying at least one electrodynamic actuator made of a metal conductor formed at least largely of copper to the carrier substrate; and applying at least one piezoelectric actuator to the carrier substrate.

12. The method as recited in claim 11, wherein the at least one piezoelectric actuator is made of a PZT material or a KNN material.

13. The method as recited in claim 11, wherein the piezoelectric actuator is applied to the carrier substrate after the at least one electrodynamic actuator is applied to the carrier substrate.

14. The method as recited in claim 11, further comprising: applying a CMOS substructure to the at least one carrier substrate.

15. The method as recited in claim 14, wherein at least one piezoelectric stack, which is formed in part by the at least one piezoelectric actuator, is applied to the CMOS substructure on the at least one carrier substrate.

16. The method as recited in claim 15, wherein the at least one piezoelectric stack is structured.

17. The method as recited in claim 15, wherein the at least one electrodynamic actuator is applied to the carrier substrate in a damascene process.

18. The method as recited in claim 15, further comprising: trenching the at least one carrier substrate is trenched.

19. A microelectronic device, the micromechanical device comprising: a carrier substrate on which at least one electrodynamic actuator made of a metal conductor formed at least largely of copper is applied, and one which at least one piezoelectric actuator is applied.

20. The microelectronic device, comprising: at least one carrier substrate; at least one piezoelectric actuator, made of a PZT material or a KNN material, arranged on the carrier substrate; and at least one electrodynamic actuator, made of a metal conductor formed at least largely of copper, arranged on the carrier substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Further advantages will become clear from the following description of the figures. An exemplary embodiment of the present invention is shown in the figures. The figures and the description contain many features in combination. A person skilled in the art will also expediently consider the features in isolation and combine them into further, useful combinations, in view of the disclosure herein.

[0019] FIG. 1 is a schematic view of a microelectronic device according to an example embodiment of the present invention.

[0020] FIG. 2 is a schematic view of the microelectronic device according to an example embodiment of the present invention.

[0021] FIG. 3 is a schematic representation of a method according to an example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0022] FIG. 1 shows a microelectronic device 10, in particular a MEMS chip device. The microelectronic device 10 comprises a carrier substrate 12. A piezoelectric actuator 16 is arranged on the carrier substrate 12. The piezoelectric actuator 16 is made of a piezoelectric perovskite material. An electrodynamic actuator 14 is arranged on the carrier substrate 12. The electrodynamic actuator 14 is made of a metal conductor formed at least largely of copper.

[0023] Diffusions 24, in particular n-dopant and/or p-dopant atoms, are arranged in the carrier substrate 12. The microelectronic device 10 comprises the electrodynamic actuator 14. The microelectronic device 10 comprises the piezoelectric actuator 16. The microelectronic device 10 comprises a CMOS substructure 20.

[0024] The CMOS substructure 20 comprises four layers by way of example. The CMOS substructure 20 can comprise a borosilicate glass layer 22 which is arranged directly on the carrier substrate 12 and in which one or more W plugs 26 are arranged.

[0025] The CMOS substructure 20 comprises a silicon nitride layer 40 arranged directly on the borosilicate glass layer 22. The CMOS substructure 20 comprises a silicon oxide layer 28 which is arranged directly on the silicon nitride layer 40 and in particular has a thickness that is greater than, in particular at least three times greater than, the silicon nitride layer 40 and/or the borosilicate glass layer 22. The CMOS substructure 20 comprises a further silicon nitride layer 30 arranged directly on the silicon oxide layer 28. The further silicon nitride layer 30 in particular passivates the electrodynamic actuator 14 on a side facing away from the carrier substrate 12.

[0026] The electrodynamic actuator 14 is integrated in the CMOS substructure 20, in particular is arranged in the silicon nitride layer 40 and the silicon oxide layer 28. The electrodynamic actuator 14 is connected to the diffusions 24 in the carrier substrate 12 via one or more W plugs 26. The electrodynamic actuator 14 can be electrically connected, in particular by the further silicon nitride layer 30, via an electrical contact 36 in the further silicon nitride layer 30. The electrical contact 36, 36′, 36″ comprises an aluminum and/or copper layer 34 and a barrier layer 32, which is in particular arranged between the electrodynamic actuator 14 and the aluminum and/or copper layer 34.

[0027] A piezoelectric stack 18, in particular the piezoelectric actuator 16, is arranged on the carrier substrate 12, in particular on the CMOS substructure 20. The piezoelectric actuator 16 is in particular made of a perovskite ceramic, such as a KNN or PZT ceramic. The piezoelectric actuator 16 is made of a PZT material or a KNN material. The piezoelectric stack 18 comprises an adhesion layer 42, in particular a TaN layer, a TiN layer, or a titanium oxide layer, which is in particular arranged directly on the further silicon nitride layer 30. The piezoelectric stack 18 comprises an electrode layer 44, in particular a platinum layer, which is in particular arranged directly on the adhesion layer 42. The piezoelectric stack 18 comprises a seed layer 46, in particular an LNO layer, in particular an LaNiO3 layer, or a PbO layer, which is in particular arranged directly on the electrode layer 44. The electrode layer 44, 44′ is in particular made of platinum. The piezoelectric stack 18 is formed in part by the piezoelectric actuator 16, which is in particular arranged directly on the seed layer 46. The piezoelectric stack 18 comprises a further electrode layer 44, which is in particular arranged directly on the piezoelectric actuator 16. The electrode layer 44 can be electrically contacted via a further electrical contact 36′. The further electrode layer 44 can be electrically contacted via an additional electrical contact 36″. The further electrical contact 36′ and the additional electrical contact 36″ are arranged to be spaced apart from one another, in particular to contact different sides of the piezoelectric actuator 16. The piezoelectric stack 18 is passivated by a barrier layer 50, in particular a TaN layer, a TiN layer, or a titanium oxide layer, and an additional silicon nitride layer 38, in particular on a side facing away from the carrier element. The piezoelectric actuator 16 is formed as a piezoelectric thin film. The piezoelectric stack 18 can comprise a further barrier layer 50, in particular a TaN layer, a TiN layer, or a titanium oxide layer, in particular between the piezoelectric actuator 16 and the further electrode layer 44′.

[0028] The microelectronic device 10 can be designed as a MEMS scanner or a MEMS gyroscope.

[0029] FIG. 2 shows the microelectronic device 10, in particular in a trenched state, comprising a structured CMOS substructure 20, with the carrier substrate 12 being trenched in particular. The carrier substrate 12 preferably comprises grooves, in particular trenches 48. The trenches 48 extend through the CMOS substructure 20 on the carrier substrate 12.

[0030] FIG. 3 shows a method 52 for producing a microelectronic device 10, in particular a MEMS chip device. The microelectronic device 10, in particular the MEMS chip device, is in particular produced using the method 52 shown in FIG. 3 for producing a microelectronic device 10.

[0031] In at least one method step, in particular a CMOS step 54, the CMOS substructure 20 is applied to, in particular deposited on, the carrier substrate 12. In the CMOS step 54, in particular metal regions and/or n-doped and/or p-doped troughs, in particular the diffusions 24, are formed in the carrier substrate 12. In the CMOS step 54, conducting tracks, piezoresistors, and/or transistors can in particular be formed.

[0032] In at least one method step, in particular a copper-applying step 56, the electrodynamic actuator 14 made of a metal conductor formed at least largely of copper is applied to the carrier substrate 12. In at least one method step, in particular the copper-applying step 56, the electrodynamic actuator 14 is applied to the carrier substrate 12 in a damascene process, in particular by plating technology. In particular, the copper-applying step 56 is carried out after the CMOS step 54. In particular, recesses, in particular grooves, are etched in the CMOS substructure 20 in the copper-applying step 56. In particular, the recesses are lined with barrier layers and seed layers, such as Ta layers and/or TaN layers, in the copper-applying step 56. In particular, in the copper-applying step 56, the lined recesses are filled with copper using plating technology, in particular in a copper damascene process, in particular to form the electrodynamic actuator 14. In particular, in the copper-applying step 56, the electrodynamic actuator 14 is planarized to a height of the CMOS substructure 20.

[0033] In at least one method step, in particular a copper-conditioning step 58, the electrodynamic actuator 14 is processed on the carrier substrate 12, in particular annealed at over 400° C., preferably at over 500° C., particularly preferably at at least 530° C. In the copper-conditioning step 58, the electrodynamic actuator 14 is passivated by an insulator, in particular by an insulator layer, for example the further silicon nitride layer 30. The copper-conditioning step 58 is in particular carried out after the copper-applying step 56.

[0034] In at least one further method step, in particular a processing step 60, the piezoelectric actuator 16 is applied to, in particular deposited on, the carrier substrate 12. In the at least one further method step, in particular the processing step 60, the piezoelectric stack 18, which is formed in part by the piezoelectric actuator 16, is applied to, in particular deposited on, the CMOS substructure 20 on the at least one carrier substrate 12. In the at least one further method step, in particular the processing step 60, the piezoelectric stack 18 is passivated by an insulator.

[0035] The at least one further method step, in particular the processing step 60, is in particular carried out after the at least one method step, in particular the at least one copper-applying step 56 and/or the copper-conditioning step 58.

[0036] In at least one method step, in particular a structuring step 62, the piezoelectric stack 18 is structured, in particular provided with recesses. In particular, in the structuring step 62, recesses are made, preferably etched, in the additional silicon nitride layer 38 and/or in the barrier layer 50. In particular, in the structuring step 62, at least one recess can be made, preferably etched, in the further silicon nitride layer 30. In particular, etched areas made in the structuring step 62 can cover a greater area than trenches 48 in the carrier substrate 12. The structuring step 62 is in particular carried out after the processing step 60. In a method step, in particular in the structuring step 62, the piezoelectric stack 18 can be provided with a pyramidal structure, in particular by removing material from the individual layers.

[0037] In at least one method step, in particular a contacting step 64, the at least one piezoelectric stack 18 and/or the at least one electrodynamic actuator 14 is electrically contacted, in particular wired, by electrical contacts 36, 36′, 36″. In the contacting step 64, the piezoelectric stack 18 can for example be electrically connected to the CMOS substructure 20. The contacting step 64 is in particular carried out after the structuring step 62.

[0038] In at least one method step, in particular an encapsulation step 66, the piezoelectric actuator 16 together with the electrodynamic actuator 14 can be hermetically encapsulated on the at least one carrier substrate 12, in particular at at least 400° C., preferably at at least 430° C. The encapsulation step 66 is in particular carried out after the contacting step 64.

[0039] In at least one method step, in particular a trenching step 68, the at least one carrier substrate 12 can be trenched, in particular completely through-trenched, in particular to produce movable MEMS structures. In particular, in the trenching step 68, the carrier substrate 12 can be partially trenched or completely trenched from two sides, in particular both sides, in particular to form movable MEMS structures. In particular, the trenching step 68 can be carried out before and/or after the encapsulation step 66.

[0040] In an optional method step, in particular before the trenching step 68, the insulator layer, in particular the further silicon nitride layer 30, and/or the silicon oxide layer 28 and/or another oxide layer of the CMOS substructure 20, can be etched, in particular locally.

[0041] In particular, the processing step 60 can be carried out before the copper-applying step 56 and the copper-conditioning step 58. In this case, the piezoelectric stack 18 is applied to the CMOS substructure 20 and is then passivated by the other oxide layer. In one method step, the other oxide layer is planarized. In one method step, at least one recess for the at least one electrodynamic actuator 14 is made in the other oxide layer. The method 52 can then be performed from the copper-applying step 56 onward, in particular without the processing step 60.