Abstract
A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the device channel have been applied to advanced DRAM process nodes. The same etching process of the recess channel MOSFET device is applied to form the recess channel semiconductor NVM device. The tunneling oxides are grown on silicon surface after the recess channel hole etching process. The storing material is deposited into the recess channel holes with coupling dielectrics on top of the storing material. The gate material is then deposited and etched to form the control gate. Owing to the recess channel embedded below the silicon substrate, the scaling challenges such as gate channel length, floating gate interference, high aspect ratio for gate stack etching, and the mechanical stability of gate formation for the semiconductor NVM device can be significantly reduced.
Claims
1. A non-volatile memory (NVM) device, comprising: a substrate having an active region defined by a field isolation structure, the active region having a recess channel hole thereon; a tunneling oxide layer on an inner wall of the recess channel hole and a surface of the active region; a charge storing structure filling the recess channel hole and formed on the tunneling oxide layer in a portion that is within the recess channel hole; a coupling dielectric layer formed on the charge storing structure and the field isolation structure; a control gate formed on the coupling dielectric layer; and a source region and a drain region at upper portions of the active region adjacent to the charge storing structure.
2. The NVM device according to claim 1, wherein the tunneling oxide layer has a thickness between 60 and 100 .
3. The NVM device according to claim 1, wherein the recess channel hole is rounded to prevent sharp silicon corners.
4. The NVM device according to claim 1, wherein the source region and the drain region are located above a device channel of the NVM device, and the device channel of the NVM device is formed along an outer wall of the recess channel hole below the tunneling oxide layer.
5. The NVM device according to claim 1, wherein the charge storing structure is made of one selected from the group consisting of conducting floating gate, charge trap material and nano-particles embedded in oxides.
6. The NVM device according to claim 5, wherein when the NVM device is a conducting floating gate NVM device and no charges are stored on the charge storing structure, a floating gate voltage V.sub.f is given by: V.sub.f=V.sub.cgC.sub.c(C.sub.c+C.sub.mos), wherein C.sub.c is a capacitance between the charge storing structure and the control gate, V.sub.cg is an applied control gate voltage and C.sub.mos is a capacitance between the charge storing structure and its device channel.
7. The NVM device according to claim 5, wherein when the NVM device is a conducting floating gate NVM device, a threshold voltage shift from the NVM device's intrinsic threshold voltage is given by: V.sub.th=Q/C.sub.c, wherein Q is an amount of charges on the charge storing structure and C.sub.c is a capacitance between the control gate and the charge storing structure.
8. The NVM device according to claim 1, wherein the field isolation structure comprises at least one shallow trench isolation region.
9. The NVM device according to claim 1, wherein the charge storing structure has a first portion filling the recess channel hole and a second portion protruding from the substrate surface.
10. The NVM device according to claim 1, wherein the recess channel hole has a width substantially equal to that of the active region.
11. A method of forming a non-volatile memory (NVM) device, comprising: forming a field isolation structure on a substrate, the field isolation structure defining an active region; forming a recess channel hole at a first portion of the active region; growing a tunneling oxide layer on an inner wall of the recess channel hole and a surface of the active region; disposing a charge storing layer on the tunneling oxide layer to fill the recess channel hole; disposing a coupling dielectric layer on the charge storing layer; disposing a metal gate layer on the coupling dielectric layer; etching away portions of the metal gate layer, the coupling dielectric layer and the charge storing layer to form a control gate and a charge storing structure with the coupling dielectric layer interposed there between; and forming a source region and a drain region at a second portion of the active region adjacent to the charge storing structure.
12. The method according to claim 11, wherein the step of forming the recess channel hole comprises: etching away the first portion of the active region to an etched depth to form the recess channel hole in the substrate so that the recess channel hole has a width substantially equal to that of the active region; and rounding the recess channel hole to prevent sharp silicon corners.
13. The method according to claim 11, wherein the tunneling oxide layer has a thickness between 60 and 100 .
14. The method according to claim 11, wherein the step of forming the source region and the drain region comprises: forming the source region and the drain region at the second portion of the active region adjacent to the charge storing structure and above a device channel of the NVM device.
15. The method according to claim 11, wherein the charge storing layer is made of one selected from the group consisting of conducting floating gate, charge trap material and nano-particles embedded in oxides.
16. The method according to claim 11, wherein the step of forming the field isolation structure comprises: forming at least one shallow trench isolation region on the substrate, the at least one shallow trench isolation region defining the active region.
17. The method according to claim 11, wherein the step of etching away further comprises: forming the charge storing structure having a first portion filling the recess channel hole and a second portion protruding from the substrate surface.
18. The method according to claim 11, wherein the step of forming the source region and the drain region comprises: diffusing impurities into the second portion of the active region to form the source region and the drain region adjacent to the charge storing structure.
19. The method according to claim 11, wherein the step of forming the source region and the drain region comprises: implanting impurities into the second portion of the active region to form the source region and the drain region adjacent to the charge storing structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiments of the present invention, in which:
[0011] FIG. 1 illustrates the cross-section view of conventional recess channel transistors used for access transistors in DRAM memory cells.
[0012] FIG. 2 shows the schematic of the recess channel semiconductor non-volatile memory device according to the invention.
[0013] FIG. 3 shows the equivalent circuit schematic for a floating gate type of recess channel NVM device according to an embodiment of the invention.
[0014] FIGS. 4a and 4b respectively illustrate two programming methods, hot electron injection and Fowler-Nordheim tunneling, for the recess channel NVM devices in FIG. 2.
[0015] FIGS. 5a and 5b respectively illustrate two erase methods, Fowler-Nordheim tunneling and band-to-band hot-hole injection, for the recess channel NVM device in FIG. 2.
[0016] FIG. 6 shows the schematic of the recess channel NVM devices in NAND-type cell array according to one embodiment of the invention.
[0017] FIG. 7 shows the top view of the recess channel NVM devices in NAND-type cell array of FIG. 6.
[0018] FIG. 8a shows a reverse control gate mask for recess channel hole etch process for NAND-type array of FIG. 6.
[0019] FIGS. 8b and 8c show the cross section views for line AA and line BB (as the locations indicated in FIG. 7) after shallow trench isolation process and recess channel hole etch process for NAND-type array of FIG. 6.
[0020] FIG. 9a shows a first polysilicon mask for NAND-type array of FIG. 6.
[0021] FIGS. 9b and 9c show the cross section views for line AA and line BB (as the locations indicated in FIG. 7) after first polysilicon etch process for NAND-type array of FIG. 6.
[0022] FIG. 10a shows a control gate mask for NAND-type array of FIG. 6
[0023] FIGS. 10b and 10c show the cross section views for line AA and line BB (as the locations indicated in FIG. 7) after control gate etch process for NAND-type array of FIG. 6.
[0024] FIGS. 11a and 11b illustrate N-type impurities ion implantation to form the source/drain electrodes for NAND-type array of FIG. 6.
[0025] FIG. 12 shows the schematic of the recess channel NVM devices in NOR-type cell array according to another embodiment of the invention.
[0026] FIG. 13 shows the top view of the recess channel NVM devices in NOR-type cell array of FIG. 12.
[0027] FIG. 14a shows a reverse control gate mask for recess channel hole etch process for NOR-type array of FIG. 13.
[0028] FIGS. 14b and 14c show the cross section views for line AA and line BB (as the locations indicated in FIG. 13) after shallow trench isolation process and recess channel hole etch process for NOR-type array of FIG. 12.
[0029] FIG. 15a shows a first polysilicon mask for NOR-type array of FIG. 13.
[0030] FIGS. 15b and 15c show the cross section views for line AA and line BB (as the locations indicated in FIG. 13) after first polysilicon etch process for NOR-type array of FIG. 12.
[0031] FIG. 16a shows a control gate mask for NOR-type array of FIG. 13.
[0032] FIGS. 16b and 16c show the cross section views for line AA and line BB (as the locations indicated in FIG. 13) after control gate etch process for NOR-type array of FIG. 12.
[0033] FIGS. 17a and 17b illustrate N-type impurities ion implantation to form the source/drain electrodes for NOR-type array of FIG. 12.
DETAILED DESCRIPTION OF THE INVENTION
[0034] The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.
[0035] In one embodiment, the recess channel NVM devices 601 form an mn NAND-type cell array 600 as the schematic shown in FIG. 6. The NAND-type cell array 600 consists of plural NAND strings 610 in FIG. 6. Each NAND string 610 is electrically connected to its correspondent vertical bitline 630 through its bitline selection transistor 602, and to the horizontal common source line CS 640 through its common source transistors 603. The control gates in a row of NVM devices 601 are connected to form a wordline 620 while the gates in a row of bitline selection transistors 602 and the gates in a row of common source transistors 603 are connected to form the bitline selection line (Sel) 650 and the common source selection line (SC) 660, respectively. As shown in FIG. 6, the mn NAND flash array 600 is configured with n wordlines, m bitlines, one common source line (CS), one bitline selection line (Sel), and one common source selection line (SC). To illustrate the fabrications of the recess channel NVM devices for the NAND flash array 600, the top view of the correspondent NAND flash array for the schematic in FIG. 6 is shown in FIG. 7. The associate processing masks and the correspondent cross section views of AA and BB lines accordingly with their process steps are the followings: (1) P-type impurities and N-type impurity for the cell array are implanted into silicon substrate to form the array P-well 800 shown in FIGS. 8b and 8c, and deep N-well (not shown), respectively. (2) Shallow Trench Isolation (STI) process module with an active area mask is performed to separate the active areas 801 from the field isolation oxide areas 802 shown in FIGS. 8b and 8c. (3) The reverse control gate mask 825 in FIG. 8a is applied to etch the recess channel holes by selective Reactive Ion Etch (RIE) process. The selective RIE process etches the exposed silicon substrate areas to form multiple recess channel holes 803 without etching the field oxide areas 802 in the array. The recess channel holes 803 in the cell array after etch process are located at the square patterned areas 702 from the top view of FIG. 7. The widths of the recess channel holes 803 are substantially equal to those of the exposed active areas 801. The recess channel holes 803 are further rounded to prevent sharp silicon corners from creating mechanical stress and high electrical fields. The final cross section views after recess channel hole etch process are shown in FIG. 8b (AA) and FIG. 8c (BB). (4) A tunneling oxide 910 shown in FIGS. 9b and 9c with a thickness between 60 100 (angstrom) is grown on the silicon surfaces along with the recess channel silicon surfaces. A layer of first polysilicon 920 is deposited to fill the recess channel holes by Chemical Vapor Deposition (CVD). The first polysilicon mask 925 covering the NVM cell array active areas (square pattern in strips) as shown in FIG. 9a is applied for blocking the removing of the first polysilicon on the active areas in the cell array during the first polysilicon etch process. Consequently the first polysilicon film covering the field areas in the cell array and the areas outside the cell array are completely removed after the first polysilicon etch process. The resultant cross sections (line AA and BB) after the first polysilicon etch process are shown in FIGS. 9b and 9c, respectively. (5) The high-k (electrical permittivity) coupling dielectric film stack 1001 consisting of either choice of nitride, aluminum oxide, hafnium oxide, or zirconium oxide, is deposited to a thin oxide liner on top of the first polysilicon 920. A second metal gate material 1002 such as silicided-polysilicon, tungsten-polysilicon, titanium nitride, tantalum nitride, tantalum, or aluminum, is then deposited on top of the coupling dielectric stacks 1001. The control gate mask 1005 shown in FIG. 10a for the self-aligned gate etching process, is applied to etch off the gate material 1002 along with the remaining first polysilicon 920 on the array active areas for the formations of control gates (wordlines) as the cross section views of FIGS. 10b (AA) and 10c (BB), respectively. In the embodiment, each of the charge storing structure 920 (after the self-aligned gate etching process) has a first portion filling the recess channel hole 803 and a second portion protruding from the substrate surface or the surface of the active area 801 as shown in FIG. 10c. Another mask (not shown) for the MOSFET transistor gates including access transistor gates Sel and SC is applied to etch off the gate material for the formation of the generic transistor gates. (6) The N-type impurities 1100 such as arsenic ions or phosphorus ions are either implanted or diffused into silicon substrate to form the N-type source/drain electrodes 118 as illustrated in FIGS. 11a and 11b. (7) Spacer process module is then applied to form MOSFET spacers. After impurity activation, the device formations in the frontend of fabrication have been completed. The fabrication continues to the backend processes of metallization for wiring connection.
[0036] In another embodiment the recess channel NVM devices form NOR-type cell device array 1200 as the schematic and the correspondent top view shown in FIGS. 12 and 13, respectively. Pluralities of NOR-pair devices 1210 are configured to form NOR-type cell array 1200 in FIG. 12. The shared common source electrodes for a row of the NOR-pair NVM devices 1210 form a common source line 1220. The control gates of the recess channel NVM devices 1210 in a row form a wordline 1230. The drain electrodes of the NVM devices 1210 in a column form a bitline 1240. The mn NOR-type array 1200 is configured into m-column and n-row recess channel NVM devices with m bitlines 1240, n wordlines 1230, and n/2 common source lines 1220. To illustrate the fabrications of the recess channel NVM devices for the NOR-type array 1200, we show the mask view and the cross section views of AA and BB lines in FIG. 13 accordingly with the process steps as the followings: (1) P-type impurities and N-type impurity for the cell array are implanted into silicon substrate to form the array P-well 1400 shown in FIGS. 14b and 14c, and deep N-well (not shown), respectively. (2) Shallow Trench Isolation (STI) process module with an active area mask is performed to separate the active areas 1401 from the field isolation oxide areas 1402 shown in FIGS. 14b and 14c. (3) The reverse control gate mask 1425 in FIG. 14a is applied to etch the recess channel holes 1403 by Reactive Ion Etch (RIE) process. The selective RIE process etches the exposed silicon areas to a depth without etching the field oxide areas 1402. The recess channel holes 1403 in the cell array after the etch process are located at the square patterned areas 1302 from the top view of FIG. 13. The widths of the recess channel holes 1403 are substantially equal to those of the exposed active areas 1401. The recess channel holes 1403 are further rounded to prevent sharp silicon corners from creating mechanical stress and high electrical fields. The cross section views after recess channel hole etch process are shown in FIGS. 14b (AA) and 14c (BB). (4) A tunneling oxide 1510 shown in FIGS. 15b and 15c with a thickness of around 60 100 (angstrom) is grown on the silicon along with the recess channel surfaces. A layer of first polysilicon 1520 is deposited to fill the recess channel holes 1403 by Chemical Vapor Deposition (CVD). The first polysilicon mask 1525 covering the NVM cell array active areas (square pattern) as shown in FIG. 15a is applied for blocking the removing of the polysilicon on the active areas in the cell array during the first poly silicon etch process. Consequently the first polysilicon film covering the field areas in the cell array and the areas outside the cell array are removed during the first polysilicon etch process. The resultant cross sections (line AA and BB) after the first polysilicon etch process are shown in FIGS. 15b, and 15c, respectively. (5) The high-k (electrical permittivity) coupling dielectric film stack 1601 consisting of either choice of nitride, aluminum oxide, hafnium oxide, or zirconium oxide, is deposited to a thin oxide liner on top of the first polysilicon 1520. Then a second metal gate material 1602 such as silicided-polysilicon, tungsten polysilicon, titanium nitride, tantalum nitride, tantalum, or aluminum, is deposited on top of the coupling dielectric stacks 1601. The control gate mask 1625, shown in FIG. 16a for the self-aligned gate etching process, is applied to etch off the gate material 1602 along with the remaining first polysilicon 1520 on the array active areas for the formations of control gates (wordlines) as the cross section views of FIGS. 16b (AA) and 16c (BB), respectively. In the embodiment, each of the charge storing structure 1520 has a first portion filling the recess channel hole 1403 and a second portion protruding from the substrate surface or the surface of the active area 1401 as shown in FIG. 16c. Another mask (not shown) for the MOSFET transistor gates is applied to etch off the gate material for the formation of the generic transistor gates. (6) The N-type impurities 1710 such as arsenic ions or phosphorus ions are implanted or diffused into silicon substrate to form the N-type source/drain electrodes 1720 as illustrated in FIGS. 17a and 17b. (7) Spacer process module is applied to form MOSFET spacers. After impurity activation, the device formations in the frontend of fabrication have been completed. The fabrication continues to the backend processes of metallization for wiring connection.
[0037] The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations of geometrical shapes including lengths and widths, gate material or tunneling dielectrics will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term the invention, the present invention or the like is not necessary limited the claim scope to a specific embodiment, and the reference to particularly preferred exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
