METHOD AND APPARATUS FOR EXCESS LOOP DELAY COMPENSATION IN DELTA-SIGMA MODULATOR

Abstract

A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital out put signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.

Claims

1. A delta-sigma modulator, comprising: a signal subtraction circuit, arranged to subtract an analog feedback signal from an analog input signal to generate a difference signal; a loop filter, arranged to perform a filtering operation upon the difference signal to generate a filtered signal; a quantizer, arranged to quantize the filtered signal into a digital output signal, wherein at least one inherent circuit characteristic of the quantizer is adjusted in response to a digital code input; a digital-to-analog converter (DAC), arranged to generate the analog feedback signal according to the digital output signal; and a control circuit, arranged to generate the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.

2. The delta-sigma modulator of claim 1, wherein the ELD compensation is achieved by an analog subtraction at an input of the quantizer.

3. The delta-sigma modulator of claim 1, wherein a hardware configuration of the quantizer is adjusted in response to the digital code input, thus adjusting the at least one inherent circuit characteristic of the quantizer.

4. The delta-sigma modulator of claim 1, wherein the at least one inherent circuit characteristic of the quantizer includes a threshold level setting inherent to the quantizer.

5. The delta-sigma modulator of claim 1, wherein the quantizer comprises a plurality of comparators, each receiving the filtered signal and having a digitally controlled comparator offset acting as a threshold level that is compared with the filtered signal; the digital code input comprises a plurality of digital codes; and digitally controlled comparator offsets of the comparators are set based on the digital codes, respectively.

6. The delta-sigma modulator of claim 5, wherein the control circuit comprises: a plurality of multiplexers, coupled to the comparators, respectively, wherein each of the multiplexers is arranged to receive a plurality of candidate digital codes and output one of the candidate digital codes to a corresponding comparator.

7. The delta-sigma modulator of claim 6, wherein the ELD compensation is performed with a coefficient; and the control circuit further comprises: a digital code setting circuit, arranged to adaptively adjust the candidate digital codes received by each of the multiplexers according to the coefficient.

8. The delta-sigma modulator of claim 7, wherein the coefficient is not constrained to a power-of-two value.

9. An analog-to-digital conversion circuit, comprising: a quantizer, arranged to quantize an analog signal into a digital signal, wherein the quantizer comprises: a plurality of comparators, each receiving the analog signal and having a digitally controlled comparator offset acting as a threshold level that is compared with the analog signal; and a control circuit, comprising: a plurality of multiplexers, coupled to the comparators, respectively, wherein each of the multiplexers is arranged to receive a plurality of candidate digital codes and output one of the candidate digital codes to a corresponding comparator, and digitally controlled comparator offsets of the comparators are set by digital codes generated from the multiplexers, respectively.

10. The analog-to-digital conversion circuit of claim 9, wherein the analog-to-digital conversion circuit is part of a delta-sigma modulator.

11. A delta-sigma modulation method, comprising: subtracting an analog feedback signal from an analog input signal to generate a difference signal; performing a filtering operation upon the difference signal to generate a filtered signal; generating a digital code input to a quantizer for setting an excess loop delay (ELD) compensation; adjusting at least one inherent circuit characteristic of the quantizer according to the digital code input; utilizing the quantizer to quantize the filtered signal into a digital output signal; and performing a digital-to-analog conversion operation based on the digital output signal, and accordingly generating the analog feedback signal.

12. The delta-sigma modulation method of claim 11, wherein the ELD compensation is achieved by an analog subtraction at an input of the quantizer.

13. The delta-sigma modulation method of claim 11, wherein adjusting the at least one inherent circuit characteristic of the quantizer comprises: adjusting a hardware configuration of the quantizer in response to the digital code input.

14. The delta-sigma modulation method of claim 11, wherein the at least one inherent circuit characteristic of the quantizer includes a threshold level setting inherent to the quantizer.

15. The delta-sigma modulation method of claim 11, wherein the quantizer comprises a plurality of comparators, each receiving the filtered signal and having a digitally controlled comparator offset acting as a threshold level that is compared with the filtered signal; the digital code input comprises a plurality of digital codes; and adjusting the at least one inherent circuit characteristic of the quantizer according to the digital code input comprises: setting digitally controlled comparator offsets of the comparators according to the digital codes, respectively.

16. The delta-sigma modulation method of claim 15, wherein each of the digital codes is generated by: receiving a plurality of candidate digital codes; and selecting one of the candidate digital codes as a digital code transmitted to a corresponding comparator.

17. The delta-sigma modulation method of claim 16, wherein the ELD compensation is performed with a coefficient; and the delta-sigma modulation method further comprises: adaptively adjusting the candidate digital codes according to the coefficient.

18. The delta-sigma modulation method of claim 17, wherein the coefficient is not constrained to a power-of-two value.

19. An analog-to-digital conversion method, comprising: utilizing a quantizer to quantize an analog signal into a digital signal, wherein the quantizer comprises: a plurality of comparators, each receiving the analog signal and having a digitally controlled comparator offset acting as a threshold level that is compared with the analog signal; and generating a plurality of digital codes to the comparators, respectively, wherein each of the digital codes is generated by: receiving a plurality of candidate digital codes; and selecting one of the candidate digital codes as a digital code transmitted to a corresponding comparator; and setting digitally controlled comparator offsets of the comparators according to the digital codes, respectively.

20. The analog-to-digital conversion method of claim 19, wherein the analog-to-digital conversion method is employed by a delta-sigma modulator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a block diagram illustrating a delta-sigma modulator using a proposed excess loop delay compensation scheme according to an embodiment of the present invention.

[0012] FIG. 2 is a diagram illustrating an exemplary embodiment of the analog-to-digital conversion circuit shown in FIG. 1.

[0013] FIG. 3 is a circuit diagram of a dynamic comparator using two methods to set a comparator offset.

[0014] FIG. 4 is a diagram illustrating exemplary comparator offsets controlled by digital code groups when a coefficient is set by one value.

[0015] FIG. 5 is a diagram illustrating exemplary comparator offsets controlled by digital code groups when a coefficient is set by another value.

[0016] FIG. 6 is a diagram illustrating exemplary comparator offsets controlled by digital code groups when a coefficient is set by yet another value.

DETAILED DESCRIPTION

[0017] Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms include and comprise are used in an open-ended fashion, and thus should be interpreted to mean include, but not limited to . . . . Also, the term couple is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0018] FIG. 1 is a block diagram illustrating a delta-sigma modulator using a proposed excess loop delay (ELD) compensation scheme according to an embodiment of the present invention. The delta-sigma modulator 100 is a continuous-time delta-sigma modulator, and includes a signal subtraction circuit 102, a loop filter 104, a quantizer 106, a control circuit 108, and a digital-to-analog converter (DAC) 110. The signal subtraction circuit 102 may be an adder (which may be implemented using a difference amplifier to perform analog signal subtraction). The signal subtraction circuit 102 is arranged to subtract an analog feedback signal V.sub.FB from an analog input signal VIN to generate a difference signal V.sub.S. The loop filter 104 may include one or more integrators/resonators. The loop filter 104 is arranged to perform a filtering operation upon the difference signal Vs to generate a filtered signal V.sub.S. The combination of quantizer 106 and control circuit 108 may be regarded as an analog-to-digital conversion circuit 112 with an ELD compensation function integrated therein. The quantizer 106 is controlled by the control circuit 108, and arranged to quantize (i.e., digitize) the filtered signal Vs' into a digital output signal D.sub.OUT. In this embodiment, the ELD compensation is performed with a scaling factor (or called coefficient a) at the quantizer 106 under the control of the control circuit 108. The DAC 110 is located in a feedback path between an output of the quantizer 106 and one input of the signal subtraction circuit 102, and arranged to perform a digital-to-analog conversion operation based on the digital output signal D.sub.OUT and accordingly generate the analog feedback signal V.sub.FB to the signal subtraction circuit 102. The signal subtraction circuit 102, loop filter 104 and DAC 110 may be implemented using conventional designs. As the present invention focuses on the design of the analog-to-digital conversion circuit 112, further description of signal subtraction circuit 102, loop filter 104 and DAC 110 is omitted here for brevity.

[0019] In this embodiment, the control circuit 108 is arranged to generate a digital code input D.sub.code to the quantizer 106 for setting the ELD compensation, where at least one inherent circuit characteristic of the quantizer 106 is adjusted in response to the digital code input D.sub.code. In one exemplary implementation, the at least one inherent circuit characteristic of the quantizer 106 is adjusted by changing a hardware configuration of the quantizer 106. For example, the at least one inherent circuit characteristic of the quantizer 106 includes a threshold level setting inherent to the quantizer 106, such that the ELD compensation is effectively achieved by an analog subtraction at an input of the quantizer 106. It should be noted that the threshold levels (i.e., quantization levels) are created inside the quantizer 106 rather than provided from an external circuit of the quantizer 106.

[0020] The control circuit 108 controls and adjusts the ELD compensation applied to the delta-sigma modulator 100 in a digital manner. It should be noted that the control circuit 108 generates the digital code input D.sub.code to the quantizer 106 instead of directly providing the threshold levels (i.e., quantization levels) to the quantizer 106. Hence, using a multiplexer for selecting threshold voltages from a plurality of candidate threshold voltages generated by a resistor string is avoided. The conventional digital ELD compensation method is only useful if the coefficient can be made or rounded to a value that is easily implemented without multipliers, i.e., the coefficient must be a power-of-two value 2.sup.N. Since the control circuit 108 can generate the digital code input D.sub.code to easily adjust the threshold level setting inherent to the quantizer 106 (i.e., ELD compensation performed at the quantizer 106), the coefficient is not constrained to be a power-of-two value 2.sup.N. Further, the control circuit 108 does not have active and passive components located in a signal path of the delta-sigma modulation loop, such that there is no signal delay (e.g., gate delay) introduced by the control circuit 108. To put it simply, the proposed digital ELD compensation scheme of the present invention overcomes the limitations in the conventional digital ELD compensation schemes and is practical beyond a high clock rate such as 2 GHz.

[0021] FIG. 2 is a diagram illustrating an exemplary embodiment of the analog-to-digital conversion circuit 112 shown in FIG. 1. The quantizer 106 includes a plurality of comparators for generating a plurality of comparison results to serve as different bits of one digital value. In this embodiment, the quantizer 106 is shown having eight comparators 202_1-202_8. Hence, each digital value of the digital output signal Dour has eight bits Q.sub.0-Q.sub.7 generated from the comparators 202_1-202_8. By way of example, the comparators 202_1-202_8 may be implemented using dynamic comparators (or called clocked comparators), each receiving the same filtered signal Vs' (i.e., loop filter output) and having a digitally controlled comparator offset acting as a threshold level that is compared with the filtered signal V.sub.S. In addition, the digital code input D.sub.code has a plurality of digital codes. Since the number of comparators 202_1-202_8 implemented in the quantizer 106 is equal to 8, the control circuit 108 therefore generates eight digital codes D.sub.1-D.sub.8 to the comparators 202_1-202_8, respectively. In this way, the digitally controlled comparator offsets of the comparators 202_1-202_8 are controlled by the digital codes D.sub.1-D.sub.8, respectively.

[0022] FIG. 3 is a circuit diagram of a dynamic comparator using two methods to set a comparator offset. By way of example, each of the comparators 202_1-202_8 may be implemented using the dynamic comparator 300 shown in FIG. 3. One method for setting the comparator offset is to create an imbalanced input pair, as shown in the dashed rectangle 301. For example, a binary-weighted tail-steering array, shown in the dashed rectangle 302, is controlled by 4 more significant bits [9:6] of a 10-bit digital code for coarse offset tuning. The other method for setting the comparator offset is to add imbalanced capacitor load, as shown by tunable capacitors C1 and C2. Each of the tunable capacitors C1 and C2 may be implemented using a capacitor array. Hence, the tunable capacitors C1 and C2 are controlled by 6 less significant bits [5:0] of the 10-bit digital code for fine offset tuning. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. There are other methods that can be adopted to create an imbalanced structure in response to a digital code to thereby introduce the desired comparator offset that acts as one threshold level for signal quantization/digitization.

[0023] Please refer to FIG. 2 again. The control circuit 108 includes a plurality of multiplexers (MUXs) 204_1-204_8 and a digital code setting circuit 206. During a power-on period of an electronic device using the delta-sigma modulator 100, the digital code setting circuit 206 may calibrate nine digital code groups S.sub.0-S.sub.8 corresponding to the coefficient used in the delta-sigma modulator 100, especially the ELD compensation performed within the analog-to-digital conversion circuit 112. FIG. 4 is a diagram illustrating exemplary comparator offsets controlled by the digital code groups S.sub.0-S.sub.8 when =1. Each of the digital code groups S.sub.0-S.sub.8 may include eight digital codes, and each of the digital codes may have ten bits. After the calibration procedure is accomplished, each of the digital codes is ensured to make a comparator have a desired comparator offset if the digital code is selected and transmitted to the comparator. Taking the digital code group So for example, the 8.sup.th digital code is used to set a largest comparator offset by +187.5 mV, the 7.sup.th digital code is used to set a comparator offset by +162.5 mV, the 6.sup.th digital code is used to set a comparator offset by +137.5 mV, the 5.sup.th digital code is used to set a comparator offset by +112.5 mV, the 4th digital code is used to set a comparator offset by +87.5 mV, the 3.sup.rd digital code is used to set a comparator offset by +62.5 mV, the 2.sup.nd digital code is used to set a comparator offset by +37.5 mV, and the 1.sup.st digital code is used to set a smallest comparator offset by +12.5 mV.

[0024] With regard to each of the digital code groups S.sub.0-S.sub.8, the digital code setting circuit 206 outputs digital codes of the same digital code group to different multiplexers 204_1-204_8 according to the order of corresponding comparator offsets. Taking the digital code group So for example, the 1.sup.st digital code (which is used to set the smallest comparator offset) is received by the multiplexer 204_1, the 2.sup.nd digital code is received by the multiplexer 204_2, the 3.sup.rd digital code is received by the multiplexer 204_3, the 4.sup.th digital code is received by the multiplexer 204_4, the 5.sup.th digital code is received by the multiplexer 204_5, the 6.sup.th digital code is received by the multiplexer 204_6, the 7.sup.th digital code is received by the multiplexer 204_7, and the 8.sup.th digital code (which is used to set the largest comparator offset) is received by the multiplexer 2048. In this way, each of the multiplexers 204_1-204_8 receives a plurality of candidate digital codes from different digital code groups, and outputs one of the candidate digital codes to a corresponding comparator.

[0025] Different digital code groups S.sub.0-S.sub.8 correspond to different ELD compensation settings, respectively. Hence, based on each digital value generated from the quantizer 106, the digital code setting circuit 206 determines which digital code group should be used to apply an appropriate ELD compensation to the delta-sigma modulation loop, and sets the multiplexer control signal mux_sel correspondingly. For example, when the digital code group So is selected by the multiplexer control signal mux_sel, the multiplexer 202_1 outputs the 1.sup.st digital code of the digital code group So as the digital code D.sub.1 such that the corresponding comparator 202_1 uses a built-in threshold level 12.5 mV that is digitally controlled by the digital code D.sub.1, the multiplexer 202_2 outputs the 2.sup.nd digital code of the digital code group So as the digital code D.sub.2 such that the corresponding comparator 202_2 uses a built-in threshold level 37.5 mV that is digitally controlled by the digital code D.sub.2, the multiplexer 202_3 outputs the 3.sup.rd digital code of the digital code group So as the digital code D.sub.3 such that the corresponding comparator 202_3 uses a built-in threshold level 62.5 mV that is digitally controlled by the digital code D.sub.3, the multiplexer 202_4 outputs the 4.sup.th digital code of the digital code group So as the digital code D.sub.4 such that the corresponding comparator 202_4 uses a built-in threshold level 87.5 mV that is digitally controlled by the digital code D.sub.4, the multiplexer 202_5 outputs the 5.sup.th digital code of the digital code group So as the digital code D.sub.5 such that the corresponding comparator 202_5 uses a built-in threshold level 112.5 mV that is digitally controlled by the digital code D.sub.5, the multiplexer 202_6 outputs the 6.sup.th digital code of the digital code group So as the digital code D.sub.6 such that the corresponding comparator 202_6 uses a built-in threshold level 137.5 mV that is digitally controlled by the digital code D.sub.6, the multiplexer 202_7 outputs the 7.sup.th digital code of the digital code group So as the digital code D.sub.7 such that the corresponding comparator 202_7 uses a built-in threshold level 162.5 mV that is digitally controlled by the digital code D.sub.7, and the multiplexer 202_8 outputs the 8.sup.th digital code of the digital code group So as the digital code D.sub.8 such that the corresponding comparator 202_8 uses a built-in threshold level 187.5 mV that is digitally controlled by the digital code D.sub.8.

[0026] As mentioned above, during a power-on period of an electronic device using the delta-sigma modulator 1001 the digital code setting circuit 206 calibrates digital code groups S.sub.0-S.sub.8 corresponding to the coefficient used in the delta-sigma modulator 100, especially the ELD compensation performed within the analog-to-digital conversion circuit 112. The digital code setting circuit 206 may be arranged to support calibration of digital code groups S.sub.0-S.sub.8 for different coefficient values, and adaptively adjusts digital codes in the digital code groups S.sub.0-S.sub.8. It should be noted that the coefficient is allowed to have a value larger than one, and is not constrained to be a power-of-two value. FIG. 5 is a diagram illustrating exemplary comparator offsets controlled by the digital code groups S.sub.0-S.sub.8 when =1.5. FIG. 6 is a diagram illustrating exemplary comparator offsets controlled by the digital code groups S.sub.0-S.sub.8 when =2. In a case where the delta-sigma modulator 100 uses the coefficient set by a first value (e.g., =1 or 2), the digital code setting circuit 206 properly sets the digital code groups S.sub.0-S.sub.8 by first digital codes calibrated during a power-on period of an electronic device using the delta-sigma modulator 100. In another case where the delta-sigma modulator 100 uses the coefficient set by a second value (e.g., =1.5), the digital code setting circuit 206 properly sets the digital code groups S.sub.0-S.sub.8 by second digital codes calibrated during a power-on period of an electronic device using the delta-sigma modulator 100.

[0027] In the present invention, the analog-to-digital conversion circuit 112 shown in FIG. 2 is part of the delta-sigma modulator 100 shown in FIG. 1. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. That is, the analog-to-digital conversion circuit 112 with the proposed circuit structure may be used in any application requiring an analog-to-digital conversion function. Hence, any analog-to-digital conversion circuit using the proposed circuit structure shown in FIG. 2 also falls within the scope of the present invention.

[0028] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.