MULTI-VOLTAGE GENERATION CIRCUIT

Abstract

A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

Claims

1. A multi-voltage generation circuit comprising: a current modulation circuit configured to generate a plurality of low-frequency currents; a plurality of voltage modulation circuits each comprising: a respective one of a plurality of voltage amplifiers configured to generate a respective one of a plurality of modulated initial voltages based on a respective one of a plurality of modulated target voltages; and a respective one of a plurality of offset capacitors each modulated to a respective one of a plurality of offset voltages by a respective one of the plurality of low-frequency currents such that the respective one of the plurality of offset voltages can raise the respective one of the plurality of modulated initial voltages to thereby generate a respective one of a plurality of modulated voltages; and a control circuit configured to: determine an order for generating the plurality of low-frequency currents in one or more operation periods; and cause the current modulation circuit to generate the plurality of low-frequency currents in each of the one or more operation periods according to the determined order.

2. The multi-voltage generation circuit of claim 1, wherein the control circuit is further configured to determine the order for generating the plurality of low-frequency currents to minimize a relative change between each of the plurality of low-frequency currents.

3. The multi-voltage generation circuit of claim 1, wherein the current modulation circuit comprises: a multi-level charge pump (MCP) configured to operate based on a plurality of duty cycles to generate a plurality of low-frequency voltages each as a function of a battery voltage; and a power inductor coupled between the MCP and a common node and configured to induce the plurality of low-frequency currents based on the plurality of low-frequency voltages, respectively; wherein the control circuit is further configured to determine the plurality of duty cycles in accordance with the determined order for generating the plurality of low-frequency currents to thereby cause the current modulation circuit to generate the plurality of low-frequency currents in each of the one or more operation periods.

4. The multi-voltage generation circuit of claim 3, wherein the control circuit is further configured to: determine a plurality of charge intervals in each of the one or more operation periods in accordance with the determined order for generating the plurality of low-frequency currents; and cause each of the plurality of offset capacitors to be charged to the respective one of the plurality of offset voltages during a respective one of the plurality of charge intervals.

5. The multi-voltage generation circuit of claim 4, wherein the control circuit is further configured to: determine a plurality of discharge intervals each corresponding to a respective one of the plurality of charge intervals; and cause each of the plurality of offset capacitors to be discharged to maintain the respective one of the plurality of modulated voltages during a respective one of the plurality of discharge intervals.

6. The multi-voltage generation circuit of claim 5, wherein each of the plurality of voltage modulation circuits further comprises: a respective voltage output that outputs the respective one of the plurality of modulated voltages, wherein the respective one of the plurality of offset capacitors is coupled between a respective one of the respective one of the plurality of voltage amplifiers and the respective voltage output; a respective bypass switch coupled between the respective output of the respective one of the plurality of voltage amplifiers and a ground; and a respective on-off switch coupled between the power inductor and the respective voltage output.

7. The multi-voltage generation circuit of claim 6, wherein the control circuit is further configured to, for each of the plurality of voltage modulation circuits: close the respective on-off switch during the respective one of the plurality of charge intervals to provide a respective one of the plurality of low-frequency currents from the common node to the respective voltage output; close the respective bypass switch during the respective one of the plurality of charge intervals such that the respective one of the plurality of low-frequency currents can charge the respective one of the plurality of offset capacitors to the respective one of the plurality of offset voltages; and cause the respective one of the plurality of voltage amplifiers to source or sink a respective high-frequency current during the respective one of the plurality of charge intervals to thereby maintain the respective one of the plurality of modulated voltages.

8. The multi-voltage generation circuit of claim 7, wherein the control circuit is further configured to, for each of the plurality of voltage modulation circuits: open the respective on-off switch during the respective one of the plurality of discharge intervals to block the respective one of the plurality of low-frequency currents from flowing from the common node to the respective voltage output; and open the respective bypass switch during the respective one of the plurality of discharge intervals such that the respective one of the plurality of offset capacitors is discharged to maintain the respective one of the plurality of modulated voltages.

9. The multi-voltage generation circuit of claim 7, wherein each of the plurality of voltage amplifiers is further configured to generate a respective one of a plurality of sense currents indicating a respective amount of the high-frequency current that is sourced/sunk by the respective one of the plurality of voltage amplifiers during the respective one of the plurality of charge intervals.

10. The multi-voltage generation circuit of claim 9, wherein the control circuit is further configured to determine each of the plurality of duty cycles based on one or more of: the respective one of the plurality of modulated initial voltages; the respective one of the plurality of offset voltages; the respective one of the plurality of modulated voltages; and the respective one of the plurality of sense currents.

11. A method for generating multiple low-frequency currents comprising: determining an order for generating a plurality of low-frequency currents in one or more operation periods; and generating the plurality of low-frequency currents in each of the one or more operation periods according to the determined current generation order.

12. The method of claim 11, further comprising determining the current generation order to minimize a relative change between each of the plurality of low-frequency currents.

13. The method of claim 11, further comprising: operating based on a plurality of duty cycles to generate a plurality of low-frequency voltages each as a function of a battery voltage; inducing the plurality of low-frequency currents based on the plurality of low-frequency voltages, respectively; and determining the plurality of duty cycles in accordance with the determined current generation in order to thereby generate the plurality of low-frequency currents in each of the one or more operation periods.

14. The method of claim 13, further comprising: determining a plurality of charge intervals in each of the one or more operation periods in accordance with the determined current generation order; and charging a plurality of offset capacitors in the plurality of charge intervals based on the plurality of low-frequency currents, respectively.

15. The method of claim 14, further comprising: determining a plurality of discharge intervals each corresponding to a respective one of the plurality of charge intervals; and discharging the plurality of offset capacitors in the plurality of discharge intervals, respectively.

16. A multi-voltage power management circuit comprising: a plurality of power amplifier circuits configured to concurrently amplify a plurality of radio frequency (RF) signals based on a plurality of modulated voltages, respectively; and a multi-voltage generation circuit comprising: a current modulation circuit configured to generate a plurality of low-frequency currents; a plurality of voltage modulation circuits each comprising: a respective one of a plurality of voltage amplifiers configured to generate a respective one of a plurality of modulated initial voltages based on a respective one of a plurality of modulated target voltages; and a respective one of a plurality of offset capacitors each modulated to a respective one of a plurality of offset voltages by a respective one of the plurality of low-frequency currents such that the respective one of the plurality of offset voltages can raise the respective one of the plurality of modulated initial voltages to thereby generate a respective one of the plurality of modulated voltages; and a control circuit configured to: determine an order for generating the plurality of low-frequency currents in one or more operation periods; and cause the current modulation circuit to generate the plurality of low-frequency currents in each of the one or more operation periods according to the determined order.

17. The multi-voltage power management circuit of claim 16, wherein the control circuit is further configured to determine the order for generating the plurality of low-frequency currents to minimize a relative change between each of the plurality of low-frequency currents.

18. The multi-voltage power management circuit of claim 16, wherein the current modulation circuit comprises: a multi-level charge pump (MCP) configured to operate based on a plurality of duty cycles to generate a plurality of low-frequency voltages each as a function of a battery voltage; and a power inductor coupled between the MCP and a common node and configured to induce the plurality of low-frequency currents based on the plurality of low-frequency voltages, respectively; wherein the control circuit is further configured to determine the plurality of duty cycles in accordance with the determined order for generating the plurality of low-frequency currents to thereby cause the current modulation circuit to generate the plurality of low-frequency currents in each of the one or more operation periods.

19. The multi-voltage power management circuit of claim 18, wherein the control circuit is further configured to: determine a plurality of charge intervals in each of the one or more operation periods in accordance with the determined order for generating the plurality of low-frequency currents; and cause each of the plurality of offset capacitors to be charged to the respective one of the plurality of offset voltages during a respective one of the plurality of charge intervals.

20. The multi-voltage power management circuit of claim 19, wherein the control circuit is further configured to: determine a plurality of discharge intervals each corresponding to a respective one of the plurality of charge intervals; and cause each of the plurality of offset capacitors to be discharged to maintain the respective one of the plurality of modulated voltages during a respective one of the plurality of discharge intervals.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1 is a schematic diagram of an exemplary multi-voltage power management circuit wherein a multi-voltage generation circuit is configured according to embodiments of the present disclosure to concurrently generate and maintain multiple modulated voltages by sharing a current modulation circuit;

[0013] FIG. 2 illustrates an exemplary operation of a voltage modulation circuit for generating and maintaining any one of the multiple modulated voltages during an operation period(s);

[0014] FIG. 3 provides an exemplary illustration of a time-division scheme that can be employed by the multi-voltage generation circuit in FIG. 1 for concurrently generating and maintaining the multiple modulated voltages;

[0015] FIG. 4 is a schematic diagram of an exemplary control circuit that can be provided in the multi-voltage generation circuit in FIG. 1 for generating and maintaining the multiple modulated voltages concurrently;

[0016] FIG. 5 provides an exemplary illustration as to how the control circuit in FIG. 4 can determine the time-division scheme in FIG. 3 based on a current generation order; and

[0017] FIG. 6 is a flowchart of an exemplary process for generating multiple low-frequency currents to cause the multi-voltage generation circuit in FIG. 1 to generate and maintain the modulated voltages.

DETAILED DESCRIPTION

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0021] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Embodiments are described herein with reference to a multi-voltage generation circuit. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltage can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

[0025] In this regard, FIG. 1 is a schematic diagram of an exemplary multi-voltage power management circuit 10 wherein a multi-voltage generation circuit 12 is configured according to embodiments of the present disclosure to concurrently generate and maintain multiple modulated voltages V.sub.CC1-V.sub.CCN by sharing a current modulation circuit 14. Herein, the multi-voltage generation circuit 12 includes multiple voltage modulation circuits 16(1)-16(N) each configured to share the current modulation circuit 14 based on time-division to thereby generate and maintain a respective one of the modulated voltages V.sub.CC1-V.sub.CCN. The voltage modulation circuits 16(1)-16(N) are configured to output the modulated voltages V.sub.CC1-V.sub.CCN via multiple voltage outputs 18(1)-18(N), respectively.

[0026] In an embodiment, the voltage outputs 18(1)-18(N) are coupled to multiple load circuits 20(1)-20(N), respectively. In this regard, the voltage modulation circuits 16(1)-16(N) are configured to concurrently provide and maintain the modulated voltages V.sub.CC1-V.sub.CCN for the load circuits 20(1)-20(N). In a non-limiting example, the load circuits 20(1)-20(N) can be power amplifier circuits each configured to amplify a respective one of multiple RF signals (not shown) based on a respective one of the modulated voltages V.sub.CC1-V.sub.CCN. Understandably, the load circuits 20(1)-20(N) can also be any other active circuits that operate based on a voltage. Further, the load circuits 20(1)-20(N) may also include a mixture of power amplifier circuits and other types of active circuits. By sharing the current modulation circuit 14 among the voltage modulation circuits 16(1)-16(N), the multi-voltage power management circuit 10 can concurrently support the load circuits 20(1)-20(N) with significantly reduced footprint.

[0027] According to an embodiment of the present disclosure, the current modulation circuit 14 includes a multi-level charge pump (MCP) 22 and a power inductor 24. The MCP 22 is configured to operate based on a plurality of duty cycles 26(1)-26(N) to generate a plurality of low-frequency voltages V.sub.DC1-V.sub.DCN (e.g., DC voltages), each as a function of a battery voltage V.sub.BAT. In a non-limiting example, the MCP 22 can be a DC-DC buck-boost converter that can operate in a buck mode and/or a boost mode. Herein, the MCP 22 is configured to generate each of the low-frequency voltages V.sub.DC1-V.sub.DCN at 0×V.sub.BAT or 1×V.sub.BAT when operating in the buck mode, or at 2×V.sub.BAT when operating in the boost mode. Understandably, the MCP 22 can toggle between 0×V.sub.BAT, 1×V.sub.BA, and/or 2×V.sub.BAT based on a respective one of the duty cycles 26(1)-26(N) to thereby generate each of the low-frequency voltages V.sub.DC1-V.sub.DCN at any desired voltage level. In other words, it is possible to adjust the low-frequency voltages V.sub.DC1-V.sub.DCN by simply adjusting the duty cycles 26(1)-26(N).

[0028] The power inductor 24 is coupled between the MCP 22 and a common node 28. Herein, the power inductor 24 is configured to induce a multiple low-frequency current I.sub.DC1-I.sub.DCN (e.g., a DC current) based on the low-frequency voltages V.sub.DC1-V.sub.DCN, respectively. Given that the low-frequency voltages V.sub.DC1-V.sub.DCN can be adjusted based on the duty cycles 26(1)-26(N), the low-frequency currents I.sub.DC1-I.sub.DCN can likewise be adjusted based on the duty cycles 26(1)-26(N).

[0029] In an embodiment, the multi-voltage generation circuit 12 further includes a control circuit 30, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. As further discussed in FIG. 4, the control circuit 30 can be configured to adjust each of the duty cycles 26(1)-26(N) based on a variety of feedback provided by the voltage modulation circuits 16(1)-16(N). In addition, the control circuit 30 is further configured to determine a time-division schedule whereby the voltage modulation circuits 16(1)-16(N) can share the current modulation circuit 14.

[0030] In an embodiment, each of the voltage modulation circuits 16(1)-16(N) includes a respective one of multiple voltage amplifiers 32(1)-32(N), a respective one of multiple offset capacitors C.sub.OFF1-C.sub.OFFN, a respective bypass switch S.sub.BYP, and a respective on-off switch S.sub.ON-OFF. In a non-limiting example, the control circuit 30 can control (e.g., toggle) the bypass switch S.sub.BYP and the on-off switch S.sub.ON-OFF in each of the voltage modulation circuits 16(1)-16(N) via a respective one of multiple control signals 34(1)-34(N).

[0031] Each of the voltage amplifiers 32(1)-32(N) is configured to generate a respective one of multiple modulated initial voltages V.sub.AMP1-V.sub.AMPN at a respective one of multiple outputs 36(1)-36(N) based on a respective one of multiple modulated target voltages V.sub.TGT1-V.sub.TGTN and a respective one of multiple supply voltages V.sub.SUP1-.sub.SUPN. For example, the voltage amplifier 32(1) generates the modulated initial voltage VAMP1 at the output 36(1) of the voltage amplifier 32(1) based on the modulated target voltage V.sub.TGT1 and the supply voltage V.sub.SUP1, and the voltage amplifier 32(N) generates the modulated initial voltage V.sub.AMPN at the output 36(N) of the voltage amplifier 32(N) based on the modulated target voltage V.sub.TGTN and the supply voltage V.sub.SUPN.

[0032] In an embodiment, each of the voltage amplifiers 32(1)-32(N) may be configured to source or sink a respective one of multiple high-frequency current I.sub.AMP1-I.sub.AMPN (e.g., alternating currents) to help maintain a respective one of the modulated voltages V.sub.CC1-V.sub.CCN at a desired level. In this regard, each of the voltage amplifiers 32(1)-32(N) may generate a respective one of multiple sense currents I.sub.SENSE1-I.sub.SENSEN to indicate an amount of the respective one of the high-frequency current I.sub.AMP1-I.sub.AMPN that is sourced or sunk by the respective one of the voltage amplifiers 32(1)-32(N).

[0033] Each of the offset capacitors C.sub.OFF1-C.sub.OFFN is coupled between a respective one of the outputs 36(1)-36(N) and a respective one of the voltage outputs 18(1)-18(N). For example, the offset capacitor C.sub.OFF1 is coupled between the output 36(1) of the voltage amplifier 32(1) and the voltage output 18(1) of the voltage modulation circuit 16(1), and the offset capacitor C.sub.OFFN is coupled between the output 36(N) of the voltage amplifier 32(N) and the voltage output 18(N) of the voltage modulation circuit 16(N). Each of the offset capacitors C.sub.OFF1-C.sub.OFFN is configured to raise a respective one of the modulated voltages V.sub.AMP1-V.sub.AMPN by a respective one of multiple offset voltages V.sub.OFF1-V.sub.OFFN to thereby generate a respective one of the modulated voltages V.sub.CC1-V.sub.CCN at a respective one of the voltage outputs 18(1)-18(N). For example, the offset capacitor C.sub.OFF1 is configured to raise the modulated initial voltage V.sub.AMP1 by the offset voltage V.sub.OFF1 to thereby generate the modulated voltage V.sub.CC1 (V.sub.CC1=V.sub.AMP1+V.sub.OFF1) at the voltage output 18(1), and the offset capacitor C.sub.OFFN is configured to raise the modulated initial voltage V.sub.AMPN by the offset voltage V.sub.OFFN to thereby generate the modulated voltage V.sub.CCN (V.sub.CCN=V.sub.AMPN+V.sub.OFFN) at the voltage output 18(N).

[0034] In one embodiment, the offset capacitors C.sub.OFF1-C.sub.OFFN can be configured to have an identical capacitance. In an alternative embodiment, the offset capacitors C.sub.OFF1-C.sub.OFFN can also be configured to have different capacitances. Further, the offset capacitors C.sub.OFF1-C.sub.OFFN can also be a same type or different types of capacitors.

[0035] The bypass switch S.sub.BYP in each of the voltage modulation circuits 16(1)-16(N) is coupled between a respective one of the outputs 36(1)-36(N) and a ground (GND). For example, the bypass switch S.sub.BYP in the voltage modulation circuit 16(1) is coupled between the output 36(1) of the voltage amplifier 32(1) and the GND, and the bypass switch S.sub.BYP in the voltage modulation circuit 16(N) is coupled between the output 36(N) of the voltage amplifier 32(N) and the GND.

[0036] The on-off switch S.sub.ON-OFF in each of the voltage modulation circuits 16(1)-16(N) is coupled between the common node 28 and a respective one of the voltage outputs 18(1)-18(N). For example, the on-off switch S.sub.ON-OFF in the voltage modulation circuit 16(1) is coupled between the common node 28 and the voltage output 18(1) of the voltage modulation circuit 16(1), and the on-off switch S.sub.ON-OFF in the voltage modulation circuit 16(N) is coupled between the common node 28 and the voltage output 18(N) of the voltage modulation circuit 16(N).

[0037] In an embodiment, the on-off switch S.sub.ON-OFF in each of the voltage modulation circuits 16(1)-16(N) can be closed to provide a respective one of the low-frequency currents I.sub.DC1-I.sub.DCN from the common node 28 to a respective one of the voltage outputs 18(1)-18(N). In contrast, the on-off switch S.sub.ON-OFF in each of the voltage modulation circuits 16(1)-16(N) can be opened to prevent the respective one of the low-frequency currents I.sub.DC1-I.sub.DCN from flowing from the common node 28 to the respective one of the voltage outputs 18(1)-18(N).

[0038] Each of the voltage modulation circuits 16(1)-16(N) further includes a respective one of multiple voltage feedback paths 38(1)-38(N). Each of the voltage feedback paths 38(1)-38(N) is configured to provide a respective one of multiple modulated voltage feedbacks V.sub.CC-FB1-V.sub.VCC-FBN from a respective one of the voltage outputs 18(1)-18(N) to a respective input of the voltage amplifiers 32(1)-32(N). In this regard, each of the voltage modulation circuits 16(1)-16(N) is a closed-loop voltage modulation circuit.

[0039] Each of the voltage modulation circuits 16(1)-16(N) can be configured to generate and maintain a respective one of the modulated voltages V.sub.CC1-V.sub.CCN based on operations described below. Herein, operations of the voltage modulation circuit 16(1) are discussed as a non-limiting example. Understandably, the operation principles described with reference to the voltage modulation circuit 16(1) are applicable to any of the voltage modulation circuits 16(1)-16(N).

[0040] In essence, the voltage modulation circuit 16(1) can be configured to generate and maintain the modulated voltage V.sub.CC1 by toggling repeatedly between a charge interval and a discharge interval. FIG. 2 illustrates an exemplary operation of the voltage modulation circuit 16(1) for generating and maintain the modulated voltage V.sub.CC1 by toggling between a charge interval CH.sub.1 and a discharge interval DCH.sub.1 during an operation period OP.sub.X. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0041] During the charge interval CH.sub.1, the control circuit 30 closes the on-off switch S.sub.ON-OFF and the bypass switch S.sub.BYP such that the low-frequency current I.sub.DC1 can flow from the common node 28 through the offset capacitor C.sub.OFF1 and to the GND to thereby charge the offset capacitor C.sub.OFF1 to the offset voltage V.sub.OFF1. While the offset capacitor C.sub.OFF is being charged, the control circuit 30 activates the voltage amplifier 32(1) to generate the modulated initial voltage V.sub.AMP1 to help maintain the modulated voltage V.sub.CC1 at a desired level.

[0042] Once the offset capacitor C.sub.OFF1 is charged up to the offset voltage V.sub.OFF1, the voltage modulation circuit 16(1) will enter the discharge interval DCH.sub.1. During the discharge interval DCH.sub.1, the control circuit 30 opens the on-off switch S.sub.ON-OFF and the bypass switch S.sub.BYP concurrently. In this regard, the low-frequency current I.sub.DC1 is blocked from the common node and the offset capacitor C.sub.OFF1 is gradually discharged to maintain the modulated voltage V.sub.CC1 at the desired level.

[0043] As shown in FIG. 2, during the charge interval CH.sub.1, the voltage amplifier 32(1) may gradually reduce the modulated initial voltage V.sub.AMP1 as the offset capacitor C.sub.OFF1 is charged to gradually increase the offset voltage V.sub.OFF1. In contrast, during the discharge interval DCH.sub.1, the offset voltage V.sub.OFF1 will gradually decrease as the offset capacitor C.sub.OFF1 is discharged. Accordingly, the voltage amplifier 32(1) may gradually increase the modulated initial voltage V.sub.AMP1. As such, the voltage modulation circuit 16(1) can maintain the modulated voltage V.sub.CC1 consistently at the desired level.

[0044] In an embodiment, the voltage amplifier 32(1) may source or sink the high-frequency current I.sub.AMP1 to help charge or discharge a holding capacitor (not shown) in the load circuit 20(1) to thereby help maintain the modulated voltage V.sub.CC1 at the desired level. In this regard, the voltage amplifier 32(1) will generate the sense current I.sub.SENSE1 to indicate the high-frequency current I.sub.AMP1 that is sourced or sunk by the voltage amplifier 32(1).

[0045] With reference back to FIG. 1, each of the voltage modulation circuits 16(2)-16(N) can be configured to generate and maintain a respective one of the modulated voltages V.sub.CC2-V.sub.CCN by toggling repeatedly between a respective charge interval and a respective discharge interval as described above in the example of the voltage modulation circuit 16(1). In this regard, the control circuit 30 is configured to determine the respective charge interval and the respective discharge interval for each of the voltage modulation circuits 16(1)-16(N) such that the voltage modulation circuits 16(1)-16(N) can share the current modulation circuit 14 on a time-division basis.

[0046] FIG. 3 provides an exemplary illustration of a time-division operation among the voltage modulation circuits 16(1)-16(N) in FIG. 1. Common elements between FIGS. 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0047] Notably, the time-division operation is repeated in each of one or more operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1. Notably, the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1 are merely examples for the purpose of illustration. It should be appreciated that the time-division operation can be repeated over any number of operation periods as needed.

[0048] Specifically, during the operation period OP.sub.X, the control circuit 30 determines multiple charge intervals CH.sub.1-CH.sub.N and multiple discharge intervals DCH.sub.1-DCH.sub.N for the voltage modulation circuits 16(1)-16(N), respectively. As shown in FIG. 3, the charge intervals CH.sub.1-CH.sub.N are so determined not to overlap with one another. In contrast, the discharge intervals DCH.sub.1-DCH.sub.N may overlap with one another.

[0049] The charge intervals CH.sub.1-CH.sub.N can be of equal duration or different durations, depending on whether the offset capacitors C.sub.OFF1-C.sub.OFFN are having an identical capacitance or different capacitances. Specifically, when the offset capacitors C.sub.OFF1-C.sub.OFFN are having the identical capacitance, the charge intervals CH.sub.1-CH.sub.N can have an identical duration. In contrast, when the offset capacitors C.sub.OFF1-C.sub.OFFN are having different capacitances, the charge intervals CH.sub.1-CH.sub.N can have different durations. Regardless, a total duration of the charge intervals CH.sub.1-CH.sub.N shall be less than or equal to the duration of the operation period OP.sub.X.

[0050] In this regard, each of the voltage modulation circuits 16(1)-16(N) toggles between a respective one of the charge intervals CH.sub.1-CH.sub.N and a respective one of the discharge intervals DCH.sub.1-DCH.sub.N to generate and maintain a respective one of the modulated voltages V.sub.CC1-V.sub.CCN. The voltage modulation circuits 16(1)-16(N) can make the modulated voltages V.sub.CC1-V.sub.CCN concurrently available to enable simultaneous operations of the load circuits 20(1)-20(N), despite operating based on the time-division scheme.

[0051] With reference back to FIG. 1, since the modulated voltages V.sub.CC1-V.sub.CCN can be at different voltage levels, the control circuit 30 needs to adjust the duty cycles 26(1)-26(N) accordingly for each of the voltage modulation circuits 16(1)-16(N). According to an embodiment of the present disclosure, the control circuit 30 may determine the duty cycles 26(1)-26(N) for a respective one of the voltage modulation circuits 16(1)-16(N) based on one or more of: a respective one of the modulated initial voltages V.sub.AMP1-V.sub.AMPN, a respective one of the offset voltages V.sub.OFF1-V.sub.OFFN, a respective one of the modulated voltages V.sub.CC1-V.sub.CCN, and a respective one of the sense currents I.sub.SENSE1-I.sub.SENSEN.

[0052] FIG. 4 is a schematic diagram providing an exemplary illustration of the control circuit 30 in FIG. 1 configured according to an embodiment of the present disclosure. Common elements between FIGS. 1 and 4 are shown therein with common element numbers and will not be re-described herein.

[0053] Herein, the control circuit 30 includes a first multiplexer 40, a second multiplexer 42, a third multiplexer 44, a fourth multiplexer 46, a first combiner 48, a second combiner 50, a third combiner 52, a controller 54, and a loop filter 56.

[0054] When determining a respective one of the duty cycles 26(1)-26(N) for a respective one of the voltage modulation circuits 16(1)-16(N), the first multiplexer 40 outputs a respective one of the modulated initial voltages V.sub.AMP1-V.sub.AMPN, the second multiplexer 42 outputs a respective one of the modulated voltages V.sub.CC1-V.sub.CCN, the third multiplexer 44 outputs a respective one of the offset voltages V.sub.OFF1-V.sub.OFFN, and the fourth multiplexer 46 outputs a respective one of the sense currents I.sub.SENSE1-I.sub.SENSEN.

[0055] The first combiner 48 combines the respective one of the modulated initial voltages V.sub.AMP1-V.sub.AMPN and the respective one of the modulated voltages V.sub.CC1-V.sub.CCN to output a first combined voltage V.sub.1. The second combiner 50 combines the first combined voltage V.sub.1 with the respective one of the offset voltages V.sub.OFF1-V.sub.OFFN to output a second voltage V.sub.2. The loop filter 56 is configured to convert the second voltage V.sub.2 into a first current I.sub.1, which is combined with the respective one of the sense currents I.sub.SENSE1-I.sub.SENSEN at the third combiner 52 to generate a combined current I.sub.COMB. The controller 54, which can be a bang-bang controller as an example, can then determine the respective one of the duty cycles 26(1)-26(N) for the respective one of the voltage modulation circuits 16(1)-16(N) based on the combined current I.sub.COMB.

[0056] Notably, since the modulated voltages V.sub.CC1-V.sub.CCN can be different from one another in each of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on, the current modulation circuit 14 needs to adapt the low-frequency currents I.sub.DC1-I.sub.DCN accordingly in each of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on. As such, it is desirable to minimize an amount of current change (increase or decrease) between each of the low-frequency currents I.sub.DC1-I.sub.DCN to help improve efficiency of the current modulation circuit 14.

[0057] In this regard, the control circuit 30 can further include a scheduling circuit 58 to determine an order (also referred to as “current generation order”) for generating the low-frequency currents I.sub.DC1-I.sub.DCN in each of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on. Accordingly, the control circuit 30 can determine the duty cycles 26(1)-26(N) according to the determined current generation order to thereby cause the current modulation circuit 14 to generate the low-frequency currents I.sub.DC1-I.sub.DCN according to the determined current generation order.

[0058] In a non-limiting example, once the scheduling circuit 58 determines the current generation order for a respective one of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on, the scheduling circuit 58 can control the first multiplexer 40, the second multiplexer 42, the third multiplexer 44, and the fourth multiplexer 46 via a selection signal 60. As such, the scheduling circuit 58 can cause the modulated initial voltages V.sub.AMP1-V.sub.AMPN, the modulated voltages V.sub.CC1-V.sub.CCN, the offset voltages V.sub.OFF1-V.sub.OFFN, and the sense currents I.sub.SENSE1-I.sub.SENSEN to be outputted from the first multiplexer 40, the second multiplexer 42, the third multiplexer 44, and the fourth multiplexer 46 in accordance with the determined current generation order. Accordingly, the control circuit 30 can generate the duty cycles 26(1)-26(N) in accordance with the determined current generation order.

[0059] According to an embodiment of the present disclosure, the scheduling circuit 58 is configured to determine the current generation order (e.g., based on the modulated target voltages V.sub.TGT1-V.sub.TGTN) to minimize a relative change between each of the low-frequency currents I.sub.DC1-I.sub.DCN in each of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on. In this regard, FIG. 5 provides an exemplary illustration as to how the control circuit 30 in FIG. 4 can determine the charge intervals CH.sub.1-CH.sub.N and the discharge intervals DCH.sub.1-DCH.sub.N in FIG. 3 based on the determined current generation order. For the sake of illustration, FIG. 5 is described with reference to the voltage modulation circuits 16(1)-16(3) among the voltage modulation circuits 16(1)-16(N).

[0060] In one example, the scheduling circuit 58 receives the modulated target voltages V.sub.TGT1, V.sub.TGT2, and V.sub.TGT3 that indicate changes of the modulated voltages V.sub.CC1, V.sub.CC2, and V.sub.CC3 in the operation period OP.sub.X−1 relative to what were in a prior operation period (e.g., OP.sub.X−2) are ΔV.sub.1(X−1), ΔV.sub.2(X−1), and ΔV.sub.3(X−1), respectively. The scheduling circuit 58 further determines that ΔV.sub.2(X−1)<ΔV.sub.3(X−1)<ΔV.sub.1(X−1). Accordingly, the scheduling circuit 58 can determine the current generation order in the operation period OP.sub.X−1 to be I.sub.DC2, I.sub.DC3, and I.sub.DC1. In this regard, the control circuit 30 will generate the duty cycles 26(2), 26(3), and 26(1) to cause the current modulation circuit 14 to generate the low-frequency currents I.sub.DC2, I.sub.DC3, and I.sub.DC1, respectively. Given the current generation order, the control circuit 30 will also determine the charge intervals CH.sub.2, CH.sub.3, and CH.sub.1 in the operation period OP.sub.X−1 for charging the offset capacitors C.sub.OFF2, C.sub.OFF3, and C.sub.OFF1, respectively. Upon determining the charge intervals CH.sub.2, CH.sub.3, and CH.sub.1, the control circuit 30 can further determine the discharge intervals DCH.sub.2, DCH.sub.3, and DCH.sub.1 accordingly.

[0061] In another example, the scheduling circuit 58 receives the modulated target voltages V.sub.TGT1, V.sub.TGT2, and V.sub.TGT3 that indicate changes of the modulated voltages V.sub.CC1, V.sub.CC2, and V.sub.CC3 in the operation period OP.sub.X relative to what were in a prior operation period (e.g., OP.sub.X−1) are ΔV.sub.1(X), ΔV.sub.2(X), and ΔV.sub.3(X), respectively. The scheduling circuit 58 further determines that ΔV.sub.1(X)<ΔV.sub.3(X)<ΔV.sub.2(X). Accordingly, the scheduling circuit 58 can determine the current generation order in the operation period OP.sub.X to be I.sub.DC1, I.sub.DC3, and I.sub.DC2. In this regard, the control circuit 30 will generate the duty cycles 26(1), 26(3), and 26(2) to cause the current modulation circuit 14 to generate the low-frequency currents I.sub.DC1, I.sub.DC3, and I.sub.DC2, respectively. Given the current generation order, the control circuit 30 will also determine the charge intervals CH.sub.1, CH.sub.3, and CH.sub.2 in the operation period OP.sub.X for charging the offset capacitors C.sub.OFF1, C.sub.OFF3, and C.sub.OFF2, respectively. Upon determining the charge intervals CH.sub.1, CH.sub.3, and CH.sub.2, the control circuit 30 can further determine the discharge intervals DCH.sub.1, DCH.sub.3, and DCH.sub.2 accordingly.

[0062] In another example, the scheduling circuit 58 receives the modulated target voltages V.sub.TGT1, V.sub.TGT2, and V.sub.TGT3 that indicate changes of the modulated voltages V.sub.CC1, V.sub.CC2, and V.sub.CC3 in the operation period OP.sub.X+1 relative to what were in a prior operation period (e.g., OP.sub.X) are ΔV.sub.1(X+1), ΔV.sub.2(X+1), and ΔV.sub.3(X+1), respectively. The scheduling circuit 58 further determines that ΔV.sub.3(X+1)<ΔV.sub.2(X+1)<ΔV.sub.1(X+1). Accordingly, the scheduling circuit 58 can determine the current generation order in the operation period OP.sub.X+1 to be I.sub.DC3, I.sub.DC2, and I.sub.DC1. In this regard, the control circuit 30 will generate the duty cycles 26(3), 26(2), and 26(1) to cause the current modulation circuit 14 to generate the low-frequency currents I.sub.DC3, I.sub.DC2, and I.sub.DC1, respectively. Given the current generation order, the control circuit 30 will also determine the charge intervals CH.sub.3, CH.sub.2, and CH.sub.1 in the operation period OP.sub.X+1 for charging the offset capacitors C.sub.OFF3, C.sub.OFF2, and C.sub.OFF1, respectively. Upon determining the charge intervals CH.sub.3, CH.sub.2, and CH.sub.1, the control circuit 30 can further determine the discharge intervals DCH.sub.3, DCH.sub.2, and DCH.sub.1 accordingly.

[0063] The multi-voltage generation circuit 12 in FIG. 2 can be configured to generate the low-frequency currents I.sub.DC1-I.sub.DCN according to a process. In this regard, FIG. 6 is a flowchart of an exemplary process 200 for generating the low-frequency currents I.sub.DC1-D.sub.DCN to cause the multi-voltage generation circuit 12 in FIG. 1 to generate and maintain the modulated voltages V.sub.CC1-V.sub.CCN.

[0064] Herein, the control circuit 30 is configured to determine an order (a.k.a. current generation order) for generating the low-frequency currents I.sub.DC1-I.sub.DCN in the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on (step 202). Accordingly, the current modulation circuit 14 can generate the low-frequency currents I.sub.DC1-I.sub.DCN in each of the operation periods OP.sub.X−1, OP.sub.X, OP.sub.X+1, and so on according to the determined current generation order (step 204).

[0065] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.