Solar cell and method for manufacturing same

Abstract

Disclosed are a solar cell and a method for manufacturing the same. The solar cell comprises asymmetric nanowires each of which has an angled sidewall, and thus incident light can be concentrated at a p-n junction portion by means of a total reflection phenomenon of light caused by the difference between the refractive indices of a semiconductor layer and a transparent electrode layer, and light absorption may increase due to an increase in the light travel distance, thus improving photoelectric efficiency. Further, the method for manufacturing the solar cell involves etching a substrate and integrally forming the substrate and a p-type semiconductor layer including the asymmetric nanowires each of which has the angled sidewalls, thereby enabling reduced manufacturing costs and simple and easy manufacture of the nanowires having the angled sidewalls.

Claims

1. A solar cell, comprising: a substrate; a p-type semiconductor layer disposed on a front surface of the substrate and including a plurality of nanowires arranged to be spaced apart in a direction substantially perpendicular to the substrate; and an n-type semiconductor layer disposed on the p-type semiconductor layer along surfaces of the plurality of nanowires, wherein each of the plurality of nanowires has an inclined sidewall, and each nanowire has a portion whose diameter decreases in a direction toward the substrate.

2. The solar cell of claim 1, wherein each of the plurality of nanowires has an inverted conical or inverted truncated conical structure.

3. The solar cell of claim 1, wherein each of the plurality of nanowires has a sandglass- or diamond-shaped structure in which an inverted conical or inverted truncated conical structure with a diameter decreasing in the direction toward the substrate is combined with a conical or truncated conical structure with a diameter increasing in the direction toward the substrate.

4. The solar cell of claim 1, wherein the sidewall of each of the plurality of nanowires forms an angle of about 15 or more and less than 90 with a horizontal plane.

5. The solar cell of claim 1, wherein an interval between the nanowires is about 15 nm to 10 m.

6. The solar cell of claim 1, further comprising a transparent electrode layer located on the n-type semiconductor layer.

7. The solar cell of claim 1, wherein the substrate and the p-type semiconductor layer are formed as a unibody structure.

8. The solar cell of claim 1, wherein the substrate and the p-type semiconductor layer contain p-type silicon.

9. A method of manufacturing a solar cell, comprising: providing a substrate; forming a p-type semiconductor layer including a plurality of nanowires having inclined sidewalls on the substrate; and forming an n-type semiconductor layer on the p-type semiconductor layer along surfaces of the plurality of nanowires, wherein each nanowire has a portion whose diameter decreases in a direction toward the substrate.

10. The method of claim 9, wherein each of the plurality of nanowires is formed to have an inverted conical or inverted truncated conical structure.

11. The method of claim 9, wherein the p-type semiconductor layer is formed as a unibody structure with the substrate by etching the substrate.

12. The method of claim 11, wherein the p-type semiconductor layer is formed to include the plurality of nanowires having inclined sidewalls by anisotropically etching the substrate.

13. The method of claim 9, further comprising forming a transparent electrode layer on the n-type semiconductor layer.

14. The solar cell of claim 1, further comprising: a back surface electrode disposed on a back surface of the substrate; and a front surface electrode disposed on the n-type semiconductor layer.

15. The solar cell of claim 1, further comprising an insulating layer formed to cover the n-type semiconductor layer and configured to fill between the plurality of nanowires.

16. The solar cell of claim 1, wherein a smallest diameter of each nanowire is between 5 to 20 nm.

17. The method of claim 9, wherein a smallest diameter of each nanowire is between 5 to 20 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a perspective view showing an existing nanowire-based solar cell.

(2) FIG. 2A is a perspective view showing a solar cell in accordance with an embodiment of the present invention.

(3) FIG. 2B is a cross-sectional view of a nanowire in accordance with an embodiment of the present invention.

(4) FIG. 3A is a schematic diagram showing reflection of sunlight perpendicularly incident on an existing nanowire-based solar cell.

(5) FIG. 3B is a schematic diagram showing reflection of sunlight perpendicularly incident on a solar cell in accordance with an embodiment of the present invention.

(6) FIG. 4A is a graph showing a rate of generation of electron-hole pairs (excitons) when sunlight is perpendicularly incident on an existing nanowire-based solar cell.

(7) FIG. 4B is a graph showing a rate of generation of electron-hole pairs (excitons) when sunlight is perpendicularly incident on a solar cell in accordance with an embodiment of the present invention.

(8) FIG. 5A is a view showing an angle (standing angle) which a sidewall of a nanowire forms with respect to a horizontal plane in a solar cell in accordance with an embodiment of the present invention.

(9) FIG. 5B is a graph showing a sunlight absorption rate and a generated current according to a standing angle in a solar cell in accordance with an embodiment of the present invention.

(10) FIGS. 6A to 6H are process flow diagrams showing a method of manufacturing a solar cell in accordance with an embodiment of the present invention.

(11) FIGS. 7A and 7B are cross-sectional views showing a nanowire in accordance with another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

(12) Example embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention, and thus example embodiments of the present invention may be embodied in many alternate forms and should not be construed as limited to example embodiments of the present invention set forth herein.

(13) It will be understood that when a layer is referred to as being on another layer or a substrate, the layer may be formed directly on the other layer or the substrate, or an intervening layer may exist between the layer and the other layer or the substrate. Furthermore, throughout this disclosure, directional terms such as upper, upper (portion), and upper surface may also encompass meanings of lower, lower (portion), and lower surface. That is, a spatial direction is construed as a relative direction, instead of an absolute direction.

(14) In the drawings, the thicknesses of layers and regions may be exaggerated or omitted for clarity. Like numerals refer to like elements throughout the description of the figures.

(15) FIG. 2A is a perspective view showing a solar cell in accordance with an embodiment of the present invention.

(16) FIG. 2B is a cross-sectional view of a nanowire in accordance with an embodiment of the present invention.

(17) Referring to FIGS. 2A and 2B, a solar cell in accordance with an embodiment of the present invention includes a substrate 100, a p-type semiconductor layer 200 located on the substrate 100, an n-type semiconductor layer 300 located on the p-type semiconductor layer 200, a transparent electrode layer 400 located on the n-type semiconductor layer 300, a front surface electrode 500 located on the transparent electrode layer 400, a back surface electrode 600 located on a surface of the substrate 100, and an insulating layer 700 located on the entire transparent electrode layer 400. However, the transparent electrode layer 400 employed in this embodiment is not an essential element of the present invention and may be excluded in some cases.

(18) The substrate 100 may be a p-type silicon substrate doped with impurities at high concentration. Here, the impurities may be selected from Group III elements. For example, the Group III elements may be B, Al, Ga, etc. The substrate 100 may be a single- or poly-crystalline silicon substrate.

(19) The p-type semiconductor layer 200 may include a plurality of nanowires 200 located on the substrate 100. That is, the p-type semiconductor layer 200 may include a plurality of nanowires 200 substantially perpendicularly arranged at regular intervals on the substrate 100.

(20) Since the p-type semiconductor layer 200 is formed of p-type silicon, the substrate 100 may be used. That is, the p-type semiconductor layer 200 may be formed as a unibody structure with the substrate 100. The p-type semiconductor layer 200 may be formed by etching an upper portion of the substrate 100 in the form of nanowires.

(21) The n-type semiconductor layer 300 is located on the p-type semiconductor layer 200. The n-type semiconductor layer 300 may be formed along surfaces of the plurality of nanowires 200. As an example, the n-type semiconductor layer 300 may be an n-type silicon layer doped with impurities. The impurities may be selected from Group V elements. As an example, the Group V element may be P, As, Sb, etc. The thickness of the n-type semiconductor layer 300 may be preferably 10 nm to 500 nm.

(22) A p-n junction is formed at an interface between the p-type semiconductor layer 200 and the n-type semiconductor layer 300. When sunlight is radiated, the p-n junction absorbs photon to generate an electron-hole pair and separates the electron-hole pair to be transferred to the front surface electrode 500 and the back surface electrode 600, respectively.

(23) A sidewall of each of the plurality of nanowires 200 may have an inclination. That is, the sidewall of each of the plurality of nanowires 200 may have a constant gradient. As an example, the plurality of nanowires 200 may be formed in such a way that a width thereof decreases from a top toward a bottom, and thus have an inverted conical or inverted truncated conical structure in which an upper diameter is greater than a lower diameter.

(24) The upper diameter and the lower diameter of each of the plurality of nanowires 200 are selected from a range of from 5 nm to 1 m in such a way that the upper diameter is greater than the lower diameter.

(25) In particular, when the upper diameter and the lower diameter are 20 nm or less, a band-gap may increase due to a quantum effect according to proximity to the bottom of the nanowires 200 of which the diameter decreases, and thereby a gap from a sub-band level may increase. Accordingly, since electron-hole recombination is reduced, photoelectric efficiency can be improved.

(26) An interval between the plurality of nanowires 200 is preferably 15 nm to 10 m. Here, the interval between the nanowires refers to a distance from a nanowire to a neighboring nanowire.

(27) When perpendicularly incident sunlight is sequentially incident on the n-type semiconductor layer 300 having a relatively greater refractive index and the transparent electrode layer 400 or insulating layer 700 having a relatively smaller refractive index around the interface between the n-type semiconductor layer 300 and the transparent electrode layer 400 or insulating layer 700, total reflection in which 100% of light is reflected may occur due to the inclination of the sidewall of each of the plurality of nanowires 200. Accordingly, since the incident sunlight is concentrated at the p-n junction portion located in the vicinity of the lower portion of the nanowire 200, and the travel distance of light increases, photoelectric efficiency can be improved.

(28) An intrinsic semiconductor layer (not shown) may be interposed between the p-type semiconductor layer 200 and the n-type semiconductor layer 300. The intrinsic semiconductor layer may be an intrinsic silicon layer in which p-type or n-type impurities are not doped. As an example, the intrinsic semiconductor layer may be preferably hydrogenated amorphous silicon layer (-Si:H).

(29) The transparent electrode layer 400 may be further disposed on the n-type semiconductor layer 300. The transparent electrode layer 400 may be formed on the entire n-type semiconductor layer 300. Accordingly, the transparent electrode layer 400 may be formed to surround front or top surfaces of the plurality of nanowires 200.

(30) The transparent electrode layer 400 may function as an electron transfer pathway and an anti-reflection layer. The transparent electrode layer 400 may be preferably formed of a conductive material having translucency. The transparent electrode layer 400 may be formed of one selected from a carbon allotrope, a transparent conductive oxide, and a metal. As an example, the carbon allotrope may be graphene, carbon nanotube, etc. In addition, the transparent conductive oxide may be indium tin oxide (ITO), Al-doped ZnO (AZO), Ga-doped ZnO (GZO), In-doped ZnO (IZO), etc. The metal may be Al, Pt, Ti, etc.

(31) The front surface electrode 500 may be formed on a part of the transparent electrode layer 400. The front surface electrode 500 may be arranged for connection with an external circuit. The front surface electrode 500 may be electrically connected to the transparent electrode layer 400. Two or more front surface electrodes 500 may be arranged to be apart from each other at an interval.

(32) The front surface electrode 500 may be formed of a metal having excellent conductivity or an alloy thereof. As an example, the front surface electrode 500 may be formed of at least one selected from Al, Ag, Ni, Cu, Ti, Pd, Cr, and W, and an alloy thereof.

(33) The back surface electrode 600 may be formed on a back surface of the substrate 100. The back surface electrode 600 may be arranged for connection with an external circuit. The back surface electrode 600 may be electrically connected to the substrate 100. The back surface electrode 600 may include the same metal or alloy thereof as the front surface electrode 500.

(34) The insulating layer 700 may be formed to cover the transparent electrode layer 400 and the front surface electrode 500. The insulating layer 700 may fill the region between the plurality of nanowires 200. Thereby, the insulating layer 700 supports and fixes the plurality of nanowires 200 to maintain structural stability of a device.

(35) The insulating layer 700 may be a transparent insulating layer. As an example, the insulating layer 700 may be a silicon oxide layer, a silicon nitride layer, or a double layer thereof. However, the present invention is not limited thereto, and any material as long as it has transparency and serves as a passivation layer can be used.

(36) A separate anti-reflection layer (not shown) may be further located on the insulating layer 700 in order to prevent reflection of light.

(37) FIG. 3A is a schematic diagram showing reflection of sunlight perpendicularly incident on an existing nanowire-based solar cell.

(38) Referring to FIG. 3A, the existing nanowire-based solar cell includes a plurality of cylindrical nanowires 200 of which a sidewall is not tilted. Accordingly, most of perpendicularly incident sunlight passes through areas other than a p-n junction portion in which generation and separation of electron-hole pairs occur due to the linearity of light. Accordingly, probability of recombination of separated electrons or holes increases, which leads to reduction of photoelectric efficiency.

(39) FIG. 3B is a schematic diagram showing reflection of sunlight perpendicularly incident on a solar cell in accordance with an embodiment of the present invention.

(40) Referring to FIG. 3B, the solar cell in accordance with the embodiment of the present invention may have an inverted conical or inverted truncated conical structure of which a diameter of a nanowire 200 decreases from a top toward a bottom. That is, the nanowire 200 may have a sidewall inclined at an angle with respect to a perpendicular direction. Accordingly, when sunlight is perpendicularly incident, since the light is incident from the n-type semiconductor layer 300 having a high refractive index to the transparent electrode layer 400 or the insulating layer 700 having a low refractive index, 100% of light may be reflected without being refracted. That is, total reflection of light may occur. In this case, the incident sunlight may be concentrated at a p-n junction portion located in the vicinity of the lower portion of the nanowire 200.

(41) FIG. 4A is a graph showing a rate of generation of electron-hole pairs (excitons) when sunlight is perpendicularly incident on an existing nanowire-based solar cell.

(42) FIG. 4B is a graph showing a rate of generation of electron-hole pairs (excitons) when sunlight is perpendicularly incident on a solar cell in accordance with an embodiment of the present invention.

(43) Referring to FIGS. 4A and 4B, in the case of an existing nanowire-based solar cell, generated excitons are distributed inversely proportional to the distance of incidence and distributed substantially evenly in the entire device. On the contrary, in the case of a solar cell in accordance with an embodiment of the present invention, generated excitons are intensively distributed in the p-n junction portion in the vicinity of the lower portion of the nanowire due to total reflection of light.

(44) In this case, since recombination of electron-hole pairs is reduced due to an effect of electric field applied near the p-n junction and a quantum effect according to a diameter of the nanowire, a photoelectric effect may increase.

(45) FIG. 5A is a view showing an angle (standing angle) which a sidewall of a nanowire forms with a horizontal plane in a nanowire-based solar cell in accordance with an embodiment of the present invention.

(46) FIG. 5B is a graph showing a sunlight absorption rate and a generated current according to a standing angle in a solar cell in accordance with an embodiment of the present invention.

(47) Referring to FIGS. 5A and 5B, an angle that a horizontal plane and a sidewall of a nanowire form is defined as a standing angle. Accordingly, in the case of a cylindrical nanowire having the same top and bottom diameters, the standing angle is about 90, the light absorption rate is about 85%, and current values are about 35 mA/cm.sup.2. On the other hand, it is found that, as the standing angle becomes smaller than 90, that is, as the standing angle decreases, the light absorption rate and currents increase. It can be interpreted that incident sunlight travels farther in the nanowire since the incident sunlight is totally reflected as a standing angle decreases.

(48) However, when the standing angle is smaller than 15 which is a critical angle for total reflection, the solar cell in accordance with an embodiment of the present invention rather shows a lower light absorption rate and a lower current value than the existing nanowire-based solar cell since incident sunlight is scattered to the outside of the nanowire.

(49) Accordingly, the sidewall of the nanowire needs to be designed to have a gradient greater than or the same as a critical angle so as to generate total reflection of incident sunlight. Accordingly, the angle that the sidewall of the nanowire forms with the horizontal plane is preferably selected from the range of about 15 to 90. That is, a gradient of the sidewall of the nanowire may be adjusted so that the standing angle is within the range of about 15 to 90.

(50) FIGS. 6A to 6H are process flow diagrams showing a method of manufacturing a solar cell in accordance with an embodiment of the present invention.

(51) Referring to FIG. 6A, a first hardmask 120a is deposited on a substrate 100. As an example, the substrate 100 may be a p-type silicon substrate doped with impurities at high concentration. The first hardmask 120a may be a silicon oxide layer or a silicon nitride layer. A nanowire pattern is formed on the substrate 100 by disposing a photoresist pattern 140a on a part of the first hardmask 120a.

(52) The first hardmask 120a may be formed using sputtering or chemical vapor deposition. The photoresist pattern 140a may be formed using electron beam lithography, ion beam lithography, X-ray lithography, ultraviolet lithography, photolithography, or nano imprint lithography.

(53) Referring to FIG. 6B, a second hardmask 120b is formed on the substrate 100, using the photoresist pattern 140a of FIG. 6A. The second hardmask 120b may be used as an etch mask for etching the substrate 100.

(54) The second hardmask 120b may be a silicon oxide layer or a silicon nitride layer. As an example, the second hardmask 120b may be formed using sputtering, chemical vapor deposition, etc. Here, a specific area may be masked using a normal photolithography and etching process.

(55) Referring to FIG. 6C, a p-type semiconductor layer 200 is formed by etching the substrate 100 using the second hardmask 120b as an etch mask. The p-type semiconductor layer 200 may include a plurality of nanowires 200 having inclined sidewalls.

(56) Here, the etching process may be a dry or wet etching process. As an example, the plurality of nanowires 200 having an inverted conical or inverted truncated conical structure in which an upper diameter is greater than a lower diameter may be formed by anisotropically etching the substrate 100 in such a way that a width decreases from a top toward a bottom.

(57) However, the shape of nanowire 200 is not limited thereto, and difference between the upper diameter and the lower diameter can be variously changed by changing an etch rate and selectivity. In addition, a standing angle can be changed by adjusting a gradient of the sidewall of the nanowire 200.

(58) Here, when the standing angle is smaller than 15 which is a critical angle for total reflection of light, incident sunlight is scattered to the outside of the nanowire 200. Accordingly, the sidewall of the nanowire 200 may be preferably designed to have a gradient of a critical angle or more so as to generate total reflection of light. Accordingly, an angle that the sidewall of the nanowire 200 forms with the horizontal plane is preferably selected from the range of about 15 to 90.

(59) Meanwhile, the upper and lower diameters of each nanowire 200 are preferably selected from the range of 5 nm to 1 m in order to fabricate a nano-scale device. In addition, an interval between the plurality of nanowires 200 is preferably selected from the range of 15 nm to 10 m.

(60) Referring to FIG. 6D, an n-type semiconductor layer 300 is formed on the p-type semiconductor layer 200 along surfaces of the plurality of nanowires 200. The n-type semiconductor layer 300 may be a silicon layer doped with n-type impurities. The n-type semiconductor layer 300 may be formed by a deposition or ion-injection process. The n-type semiconductor layer 300 is preferably formed to have a thickness of 10 nm to 500 nm.

(61) Referring to FIG. 6E, a transparent electrode layer 400 is formed on the n-type semiconductor layer 300. The transparent electrode layer 400 may be formed of a conductive material having translucence in order for more sunlight to be penerated. As an example, the transparent electrode layer 400 may be formed of at least one selected from a carbon allotrope, a transparent conductive oxide, and a metal. The transparent electrode layer 400 may be formed using thermal deposition, electron beam deposition, RF sputtering, or magnetron sputtering.

(62) Referring to FIGS. 6F and 6G, a front surface electrode 500 may be formed on a part of the transparent electrode layer 400 so that the transparent electrode layer 400 is connected to an external circuit. In addition, a back surface electrode 600 may be formed on a back of the substrate 100 so that the p-type semiconductor layer 200 is connected to an external circuit. The electrodes 500 and 600 may be a metal having excellent conductivity, or an alloy thereof. The electrodes 500 and 600 may be formed using thermal deposition, vacuum deposition, etc. Here, photoresist 140b may be coated on the transparent electrode layer 400 in order to protect the plurality of previously formed nanowires 200 when the back surface electrode 600 is formed.

(63) Referring to FIG. 6H, an insulating layer 700 is formed to cover the entire transparent electrode layer 400. The insulating layer 700 may fill the region between the plurality of nanowires 200, and support and fix the plurality of nanowires 200. The insulating layer 700 may be a transparent insulating layer. As an example, the insulating layer 700 may be silicon oxide layer, silicon nitride layer, or a double layer thereof. However, the present invention is not limited thereto, and any material as long as it has transparency and serves as a passivation layer can be used. The insulating layer 700 may be formed using sputtering or CVD.

(64) FIGS. 7A and 7B are cross-sectional views showing a nanowire in accordance with another embodiment of the present invention.

(65) Referring to FIGS. 7A and 7B, a nanowire 200 may have a sandglass- or diamond-shaped structure in which an inverted conical or inverted truncated conical structure with an upper diameter greater than a lower diameter is combined with a conical or truncated conical structure with an upper diameter smaller than a lower diameter. The sandglass-shaped structure has a conical or truncated conical structure disposed adjacent to the substrate 100, and an inverted conical or inverted truncated conical structure disposed on the conical or truncated conical structure. On the contrary, the diamond-shaped structure has an inverted conical or inverted truncated conical structure disposed adjacent to the substrate 100, and a conical or truncated conical structure disposed on the inverted conical or inverted truncated conical structure.

(66) Here, gradients of both sidewalls of the nanowire 200 having the sandglass-shaped or diamond-shaped structure may be changed based on a specific point.

(67) However, the shape of the nanowire 200 is not limited thereto, and any shape of nanowire 200 as long as it has a structure using total reflection of light can be used.

(68) Although a few embodiments have been described, it will be apparent to those skilled in the art that various modifications can be made to the above-described exemplary embodiments of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers all such modifications provided they come within the scope of the appended claims and their equivalents.