Nano multilayer film, field effect tube, sensor, random accessory memory and preparation method

Abstract

A nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type, and a random access memory of electrical field drive type can obtain an electro-resistance effect in an electrical field modulation multilayer film at room temperature. The nano multilayer film includes in succession from bottom to top a bottom layer, a substrate, a bottom layer, a functional layer, a buffer layer, an insulation layer, a conductive layer, and a cap layer. The buffer layer and the insulation layer can be selectively added as required when the conductive layer is made of a magnetic metal. The effect of influencing and changing the conductivity of the metal layer and thus adjusting the change in the resistance of the devices can obtain different resistance states corresponding to different electrical fields and achieving an electro-resistance effect.

Claims

1. A nano multilayer film of electrical field modulation type, characterized by comprising in succession from bottom to top: a bottom layer; a substrate; a buffer layer; an insulating barrier layer; a conductive layer; and a cap layer, wherein the bottom layer is of a conductive material and, as a lower electrode, is used for applying an electrical field onto the substrate; the substrate is of a ferroelectric or multi-ferric material which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the buffer layer, as an upper electrode, is used for applying an electrical field onto the ferroelectric material or the multi-ferric material, and is a non-magnetic metal layer; the insulating barrier layer is of an oxide; the cap layer, as a protective layer, prevents the oxidation of the conductive layer; by applying an electrical field between the bottom layer and the buffer layer, the intensity and the direction of electrical polarization of the substrate change, which influences and changes an in-plane conductivity of the conductive layer, so that different resistance states corresponding to different electrical fields can be obtained, thereby achieving a reversible ER effect.

2. The nano multilayer film of electrical field modulation type according to claim 1, characterized in that the conductive layer is a non-magnetic metal layer, a magnetic metal layer, or an antiferromagnetic layer, or is one of a conductive polymer material, a topological insulator material, and a conductive semiconductor doped material.

3. The nano multilayer film of electrical field modulation type according to claim 2, characterized in that the non-magnetic metal layer comprises a non-magnetic metal or a non-magnetic alloy, with a thickness of 2 to 100 nm, and the magnetic metal layer of the nano multilayer film is made of a magnetic metal or a magnetic alloy, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm, the magnetic metal layer comprises a directly or indirectly pinning structure, wherein the directly pinning structure comprises an antiferromagnetic/ferromagnetic layer, and wherein the indirectly pinning structure comprises an antiferromagnetic layer/a first ferromagnetic layer/a non-magnetic metal layer/a second ferromagnetic layer.

4. A nano multilayer film of electrical field modulation type, characterized by comprising in succession from bottom to top: a substrate; a bottom layer; a functional layer; a buffer layer; an insulating barrier layer; a conductive layer; and a cap layer, wherein the bottom layer is of a conductive material and, as a lower electrode, is used for applying an electrical field onto the functional layer; the functional layer is a ferroelectric thin film or a multi-ferric thin film which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the buffer layer, as an upper electrode, is used for applying an electrical field onto the material of the ferroelectric thin film or the multi-ferric thin film, and is a non-magnetic metal layer; the insulating barrier layer is of an oxide; the cap layer, as a protective layer, prevents the oxidation of the conductive layer; by applying an electrical field between the bottom layer and the buffer layer, the intensity and the direction of electrical polarization of the functional layer change, which influences and changes an in-plane conductivity of the conductive layer, so that different resistance states corresponding to different electrical fields can be obtained, thereby achieving a reversible ER effect.

5. The nano multilayer film of electrical field modulation type according to claim 4, characterized in that the functional layer comprises a ferroelectric nanofilm or a multi-ferric nanofilm.

6. The nano multilayer film of electrical field modulation type according to claim 4, characterized in that the conductive layer is disposed on the insulating barrier layer, and its conductivity can be regulated by the intensity and the direction of electrical polarization of the ferroelectric or multi-ferric thin film in the bottom via electrical polarization interaction or magnetoelectric coupling.

7. A nano multilayer film of electrical field modulation type, characterized by comprising in succession from bottom to top: a substrate; a bottom layer; a functional layer; a buffer layer; an insulating barrier layer; a magnetic layer; and a cap layer, wherein the substrate is one of a non-ferroelectric material and a multi-ferric material; the bottom layer is of a conductive material and, as a lower electrode, is used for applying an electrical field onto the functional layer; the functional layer is a ferroelectric thin film or a multi-ferric thin film which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the cap layer, as an upper electrode and a protective layer, prevents the oxidation of the magnetic layer; the buffer layer is a non-magnetic metal layer; the insulating barrier layer is of an oxide; by applying an electrical field between the bottom layer and the cap layer, the intensity and the direction of electrical polarization of the functional layer change, which influences and changes the in-plane conductivity of the magnetic layer, so that different resistance states corresponding to different electrical fields can be obtained, thereby achieving a reversible ER effect.

8. The nano multilayer film of electrical field modulation type according to claim 7, characterized in that the functional layer of the nano multilayer film comprises a ferroelectric or multi-ferric nanofilm.

9. The nano multilayer film of electrical field modulation type according to claim 7, characterized in that the magnetic layer is disposed on the material of the functional layer, and its conductivity can be regulated by the intensity and the direction of electrical polarization of the ferroelectric or the multi-ferric thin film in the bottom via electrical polarization interaction or magnetoelectric coupling.

10. The nano multilayer film of electrical field modulation type according to claim 7, characterized in that the magnetic layer is made of a ferromagnetic metal or a ferromagnetic alloy, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

11. A logic device based on a nano multilayer film having banter symmetrical double functional layers, characterized in that NAND Logic and NOR logic can be achieved by setting an initial output logic state using the nano multilayer film according to any one of claims 1, 4 and 7.

12. An electrical field sensor of switch type based on electroresistance effect, characterized by comprising the nano multilayer film of electrical field modulation type according to any one of claims 1, 4 and 7.

13. A random access memory of electrical field drive type based on electroresistance effect comprising a nanodevice of electrical field modulation type as the memory cell, characterized by comprising the nano multilayer film of electrical field modulation type according to any one of claims 1, 4 and 7.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1a is a schematic view illustrating the structure of a nano multilayer film according to the present invention;

(2) FIG. 1b shows Structure A: BOL 1/SUB/B FL/ISO/NM (or FM, or AFM)/CAP;

(3) FIG. 1c shows Structure B: SUB/BOL 2/FCL/ISO/NM (or FM, or AFM)/CAP;

(4) FIG. 1d shows Structure C: SUB/BOL 2/FCL/BFL/ISO/NM (or FM, or AFM)/CAP;

(5) FIG. 1e shows Structure D: SUB/BOL 2/FCL/FM1/NM/FM2/AFM/CAP;

(6) FIG. 1f shows Structure E: SUB/BOL 2/FCL/FM/AFM/CAP;

(7) FIG. 1g shows Structure F: SUB/BOL 2/FCL/FM1/NM/FM2/CAP;

(8) FIG. 1h shows Structure G: SUB/BOL 2/FCL/FM/CAP;

(9) FIG. 2a is a schematic view illustrating the structure of a nano multilayer film in Example 1 according to the present invention;

(10) FIG. 2b is a schematic view illustrating the relationship between the variation of resistance R of a device and the variation of an external electrical field E;

(11) FIG. 3a is a schematic view illustrating the structure of a nano multilayer film in Example 2 according to the present invention;

(12) FIG. 3b is a schematic view illustrating the relationship between the variation of resistance R of a device, in which the intermediate conductive layer is the magnetic metal Co.sub.75Fe.sub.25, and the variation of an external electrical field E;

(13) FIG. 3c is a schematic view illustrating the measurement results of the varying external electrical field E and the resistance R of a nano multilayer film in case the intermediate conductive layer is Co.sub.75Fe.sub.25, wherein the measurement is performed while a magnetic field of 1 kOe is being applied;

(14) FIG. 3d is a schematic view illustrating the measurement results of the varying external electrical field E and the resistance R of a nano multilayer film in case the intermediate conductive layer is a 5 nm-thick Al film;

(15) FIG. 3e is a schematic view illustrating the measurement results of the varying external electrical field E and the resistance R of a nano multilayer film in case the intermediate conductive layer is a 5 nm-thick IrMn antiferromagnetic alloy film;

(16) FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G and 4H are schematic views illustrating the core structures of eight memory cells of electrical field modulation type;

(17) FIGS. 5A1, 5A2, 5A3, 5B1, 5B2, 5B3, 5C1, 5C2, 5C3, 5D1, 5D2, 5D3, 5E1, 5E2, 5E3, 5F1, 5F2, 5F3, 5G1, 5G2, 5G3, 5G4, 5G5 and 5G6 are cross-sectional views and plan views corresponding to the core structures of seven memory cells of electrical field modulation type shown in the figures;

(18) FIG. 6 is a schematic view of an array of seven memory cells of electrical field modulation type illustrated in FIGS. 4 and 5;

(19) FIGS. 7A, 7B and 7C are cross-sectional views and plan views showing the structures of memory cells of electrical field modulation type having transistors;

(20) FIGS. 8A and 8B are schematic views of two arrays of memory cells of electrical field modulation type having transistors;

(21) FIG. 9 is a schematic view showing the overall structure of a random access memory based on memory cells of electrical field modulation type according to the present invention;

(22) FIG. 10A shows the core structure of an ER FET, to which an electrical field is vertically applied, and the self-defined electrical symbols;

(23) FIG. 10B shows the core structure of an ER FET, to which an electrical field is horizontally applied, and the self-defined electrical symbols;

(24) FIG. 11A shows the basic structure of a complementary ER FET, to which an electrical field is vertically applied, and the self-defined electrical symbols;

(25) FIG. 11B is a diagram showing the technological structure of a complementary ER FET, to which an electrical field is vertically applied;

(26) FIG. 11C shows the basic structure of a complementary ER FET, to which an electrical field is horizontally applied, and the self-defined electrical symbols;

(27) FIG. 11D is a diagram showing the technological structure of a complementary ER FET, to which an electrical field is horizontally applied;

(28) FIG. 12A shows an inverter circuit realized by using an ER FET;

(29) FIG. 12B shows a NAND gate circuit realized by using an ER FET;

(30) FIG. 12C shows a NOR gate circuit realized by using an ER FET;

(31) FIG. 13A shows an inverter circuit realized by using a complementary ER FET;

(32) FIG. 13B shows a NAND gate circuit realized by using a complementary ER FET;

(33) FIG. 13C shows a NOR gate circuit realized by using a complementary ER FET;

(34) FIG. 14 shows a circuit with a two-channel input LUT (look-up table) function in a FPGA that is realized by using an ER FET and a complementary ER FET;

(35) FIG. 15A is a schematic view showing a logic device based on Structure h in Scheme 2;

(36) FIG. 15B is the corresponding truth table;

(37) FIG. 16A is a schematic view showing a logic device based on Structure h in Scheme 3;

(38) FIG. 16B is the corresponding truth table;

(39) FIG. 17A is a schematic view showing a logic device based on Structure d in Scheme 1;

(40) FIG. 17B is the corresponding truth table;

(41) FIG. 18A is a schematic view showing a logic device based on Structure h in Scheme 4;

(42) FIG. 18B is the corresponding truth table;

(43) FIG. 19A is a schematic view showing a logic device based on Structure h in Scheme 4;

(44) FIG. 19B is the corresponding truth table;

(45) FIG. 20A is a schematic view showing a logic device based on Structure d in Scheme 4; and

(46) FIG. 20B is the corresponding truth table.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(47) The object of the present invention is to present a nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type and a random access memory of electrical field drive type, configured to achieve a novel reversible ER effect in a nano multilayer film of electrical field modulation type at room temperature, and to apply the reversible ER effect in electronic devices.

(48) The nano multilayer film comprises, in succession from bottom to top, a bottom layer, a substrate, a bottom layer, a functional layer, a buffer layer, an insulating barrier layer, an intermediate conductive layer, and a cap layer, wherein when the intermediate conductive layer is a magnetic metal, magnetic alloy or magnetic metal composite layer, the buffer layer and the insulation layer can be selectively added as required. The intermediate conductive layer comprises a metal layer, a conductive polymer material, topological insulator material, a conductive semiconductor doped material, or the like. The metal layer comprises a non-magnetic metal layer, a magnetic metal layer, an anti ferromagnetic layer, or the like. When the intermediate conductive layer is a non-magnetic metal layer or an antiferromagnetic layer, the buffer layer and the insulating barrier layer must be added in order to obtain a relatively high signal to noise ratio.

(49) According to the first aspect of the present invention, a nano multilayer film of electrical field modulation type is provided, which comprises in succession from bottom to top: a bottom layer; a substrate; a buffer layer; an insulating barrier layer; a conductive layer; and a cap layer.

(50) wherein, the bottom layer is a conductive material which, as a lower electrode, is used for applying an electrical field onto the substrate; the substrate is a ferroelectric or multi-ferric material which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the buffer layer, as an upper electrode, is used for applying an electrical field onto the ferroelectric or multi-ferric material; the intermediate insulation layer is an oxide; the cap layer, as a protective layer, prevents the oxidation of the intermediate conductive layers. An electrical field is applied between the bottom layer and the buffer layer (the upper and the lower electrodes), and because of the changes in the intensity and the direction of electrical polarization of the substrate (of a ferroelectric or multi-ferric material), the in-plane conductivity between the neighboring conductive layers is influenced and changed, so as to obtain different resistance states corresponding to different electrical fields, thereby achieving a reversible ER effect.

(51) The bottom layer of the above nano multilayer film comprises a conductive metal material.

(52) The substrate of the above nano multilayer film comprises a substrate made of a ferroelectric or multi-ferric material.

(53) The buffer layer of the above nano multilayer film can improve the interface between the substrate and the multilayer film, and can be used as an upper electrode for applying an electrical field onto the ferroelectric or multi-ferric film material.

(54) The conductive layer of the above nano multilayer film can grow perfectly on the insulating barrier layer, and its conductivity can be regulated by the intensity and the direction of electrical polarization of the ferroelectric or multi-ferric film at the bottom via electrical polarization interaction or magnetoelectric coupling.

(55) The conductive layer of the above nano multilayer film comprises a non-magnetic metal layer, a magnetic metal layer, an antiferromagnetic layer, a conductive polymer material, a topological insulator material, a conductive semiconductor doped material, or the like.

(56) The non-magnetic metal layer of the above nano multilayer film consists of a non-magnetic metal or an alloy thereof, with a thickness of 2 to 100 nm.

(57) The intermediate conductive layer of the above nano multilayer film comprises a conductive polymer material, a topological insulator material, a conductive semiconductor doped material, or the like.

(58) The magnetic metal layer of the above nano multilayer film is made of a magnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(59) The magnetic metal layer of the above nano multilayer film comprises a directly or indirectly pinning structure, the directly pinning structure comprising an antiferromagnetic (AFM)/ferromagnetic (FM) layer, and the indirectly pinning structure comprising an antiferromagnetic (AFM) layer/a first ferromagnetic (FM1) layer/a non-magnetic metal (NM) layer/a second ferromagnetic (FM2) layer.

(60) The antiferromagnetic material of the above nano multilayer film comprises an antiferromagnetic alloy or oxide.

(61) The ferromagnetic (FM) layer, the first ferromagnetic (FM1) layer and the second ferromagnetic (FM2) layer of the above nano multilayer film are made of a ferromagnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(62) The cap layer of the above nano multilayer film comprises a monolayer or multilayer film made of a not readily oxidable metal material, with a thickness of 2 to 200 nm.

(63) According to the second aspect of the present invention, a nano multilayer film of electrical field modulation type is provided, which comprises in succession from bottom to top: a substrate; a bottom layer; a functional layer; a buffer layer; an insulating barrier layer; a conductive layer; and a cap layer.

(64) wherein, the bottom layer is of a conductive material which, as a lower electrode, is used for applying an electrical field onto the functional layer; the functional layer is a ferroelectric or multi-ferric film which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the buffer layer, as an upper electrode, is used for applying an electrical field onto the ferroelectric or multi-ferric film material; the intermediate insulation layer is of an oxide; the cap layer, as a protective layer, prevents the oxidation of the intermediate conductive layers. An electrical field is applied between the bottom layer and the buffer layer (the upper and the lower electrodes), and because of the changes in the intensity and the direction of electrical polarization of the functional layer (of a ferroelectric or multi-ferric material), the in-plane conductivity between the neighboring conductive layers is influenced and changed, so that different resistance states corresponding to different electrical fields can be obtained, thereby achieving a reversible ER effect.

(65) The substrate of the above nano multilayer film comprises a Si substrate, SiC, a glass substrate or SiSiO.sub.2 substrate, a MgO monocrystalline substrate, an Al.sub.2O.sub.3 monocrystalline substrate, an organic flexible substrate, or the like.

(66) The bottom layer of the above nano multilayer film comprises a conductive metal material.

(67) The functional layer of the above nano multilayer film comprises a ferroelectric or multi-ferric nano-film, which can deposit a seed layer in advance as required for optimizing an interface with the substrate and improving the crystalline structure of the ferroelectric or multi-ferric nano-film.

(68) The buffer layer of the above nano multilayer film can improve the interface between the insulating barrier layer and the functional layer, and can be used as an upper electrode for applying an electrical field onto the material of the ferroelectric or multi-ferric film.

(69) The conductive layer of the above nano multilayer film can grow perfectly on the insulating barrier layer, and its conductivity (resistance) can be regulated by the intensity and the direction of electrical polarization of the ferroelectric or multi-ferric film in the bottom via electrical polarization interaction or magnetoelectric coupling effect.

(70) The conductive layer of the above nano multilayer film comprises a non-magnetic metal layer, a magnetic metal layer, an antiferromagnetic layer, a conductive polymer material, a topological insulator material, a conductive semiconductor doped material, or the like.

(71) The non-magnetic metal layer of the above nano multilayer film consists of a non-magnetic metal or an alloy thereof, with a thickness of 2 to 100 nm.

(72) The intermediate conductive layer of the above nano multilayer film comprises a conductive polymer material, a topological insulator material, a conductive semiconductor doped material, or the like.

(73) The magnetic metal layer of the above nano multilayer film is made of a magnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(74) The magnetic metal layer of the above nano multilayer film comprises a directly or indirectly pinning structure, the directly pinning structure comprising an antiferromagnetic (AFM)/ferromagnetic (FM) layer, and the indirectly pinning structure comprising an antiferromagnetic (AFM) layer/a first ferromagnetic (FM1) layer/a non-magnetic metal (NM) layer/a second ferromagnetic (FM2) layer.

(75) The antiferromagnetic material of the above nano multilayer film comprises an antiferromagnetic alloy or oxide.

(76) The ferromagnetic (FM) layer, the first ferromagnetic (FM1) layer and the second ferromagnetic (FM2) layer of the above nano multilayer film are made of a ferromagnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(77) The cap layer of the above nano multilayer film comprises a monolayer or multilayer film made of a not readily oxidable metal material, with a thickness of 2 to 200 nm.

(78) According to the fourth aspect of the present invention, a nano multilayer film of electrical field modulation type is provided, which comprises in succession from bottom to top: a substrate; a bottom layer; a functional layer; a magnetic layer; and a cap layer.

(79) wherein, the substrate is a non-ferroelectric or multi-ferric material; the bottom layer is a conductive material which, as a lower electrode, is used for applying an electrical field onto the functional layer; the functional layer is a ferroelectric or multi-ferric film which can alter and regulate the intensity and the direction of electrical polarization under the action of an electrical field; the cap layer, as an upper electrode and a protective layer, prevents the oxidation of the intermediate magnetic layer. An electrical field is applied between the bottom layer and the cap layer (the upper and the lower electrodes), and since the changes in the intensity and the direction of electrical polarization of the functional layer (a ferroelectric or multi-ferric material) influence and change the in-plane conductivity between the neighboring metal and magnetic layers, different resistance states corresponding to different electrical fields can be obtained, thereby achieving a reversible ER effect.

(80) The bottom layer of the above nano multilayer film comprises a conductive metal material.

(81) The substrate of the above nano multilayer film comprises a Si substrate, SiC, a glass substrate or SiSiO.sub.2 substrate, a MgO monocrystalline substrate, an Al.sub.2O.sub.3 monocrystalline substrate, an organic flexible substrate, or the like.

(82) The functional layer of the above nano multilayer film comprises a ferroelectric or multi-ferric nanofilm.

(83) The magnetic layer of the above nano multilayer film can grow perfectly on the material of the functional layer, and its conductivity can be regulated by the intensity and the direction of electrical polarization of the ferroelectric or multi-ferric film at the bottom via electrical polarization interaction or magnetoelectric coupling.

(84) The magnetic layer of the above nano multilayer film is made of a ferromagnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(85) The magnetic layer of the above nano multilayer film comprises a directly or indirectly pinning structure, the directly pinning structure comprising an antiferromagnetic (AFM)/ferromagnetic (FM) layer, and the indirectly pinning structure comprising an antiferromagnetic (AFM) layer/a first ferromagnetic (FM1) layer/a non-magnetic metal (NM) layer/a second ferromagnetic (FM2) layer.

(86) The antiferromagnetic material of the above nano multilayer film comprises an anti ferromagnetic alloy or oxide.

(87) The ferromagnetic (FM) layer, the first ferromagnetic (FM1) layer and the second ferromagnetic (FM2) layer of the above nano multilayer film are made of a ferromagnetic metal or an alloy thereof, with a thickness of 2 to 100 nm, or made of a diluted magnetic semiconductor material or a semi-metallic material, with a thickness of 2 to 100 nm.

(88) The cap layer of the above nano multilayer film comprises a monolayer or multilayer film made of a not readily oxidable metal material, with a thickness of 2 to 200 nm.

(89) According to the fifth aspect of the present invention, FETs of electrical field modulation type based on the ER effect is provided. By applying different voltages to the gates of the nano multilayer film of electrical field modulation type according to the first, second, third and fourth aspects of the present invention, a certain electrical field is formed between the cap layer and the bottom layer. Additionally, a certain voltage is applied between the source and the drain, because of the generation of the ER effect, the multilayer film has different resistances corresponding to different electrical fields, whereupon the conductivity from the source to the drain varies. Therefore, the conductivity or resistance values from the source electrode to the drain electrode can be regulated via the voltages applied to the gates.

(90) FIG. 1a shows the nano multilayer film according to one embodiment of the present invention, which comprises in succession from bottom to top: a bottom layer 102 (abbreviated as BOL 1), a substrate 101 (abbreviated as SUB), a bottom layer 103 (abbreviated as BOL 2), a function layer 104 (abbreviated as FCL), a buffer layer 105 (abbreviated as BFL), an insulation layer 106 (abbreviated as ISO), an intermediate conductive layer 107 (abbreviated as IML), and a cap layer 108 (abbreviated as CAP). Each of the layers is described in detail below.

(91) The substrate 101 is a ferroelectric or multi-ferric substrate, or a general substrate including a Si substrate, SiC, a glass substrate or SiSiO.sub.2 substrate, a MgO mono-crystalline substrate, an Al.sub.2O.sub.3 mono-crystalline substrate, an organic flexible substrate, or the like.

(92) The substrate 101 of the above substrate is a ferroelectric or multi-ferric substrate, including Pb(Mg.sub.1/3Nb.sub.2/3)OPbTiO.sub.3 (PMN-PT), BiFeO.sub.3 (BFO), BaTiO.sub.3, Pb(Zn.sub.1/3Nb.sub.2/3)O.sub.3PbTiO.sub.3 (PZN-PT), PbTiO.sub.3 (PTO), SrTiO.sub.3 (STO), BiMnO.sub.3 or the like, with a thickness of 0.1 to 1 mm.

(93) The substrate of the nano multilayer film is a general substrate including a Si substrate, SiC, a glass substrate or SiSiO.sub.2 substrate, a MgO mono-crystalline substrate, an Al.sub.2O.sub.3 mono-crystalline substrate, an organic flexible substrate, or the like, with a thickness of 0.1 to 1 mm.

(94) The bottom layer 102 of the nano multilayer film is a conductive metal layer. The conductive metal layer is generally made of Cu, Cr, V, Nb, Mo, Ru, Pd, Ta, W, Pt, Ag, Au or an alloy thereof, with a thickness of 2.0 to 100 nm.

(95) The bottom layer 103 of the nano multilayer film is a conductive metal layer. The conductive metal layer is generally used Cu, Cr, V, Nb, Mo, Ru, Pd, Ta, W, Pt, Ag, Au or an alloy thereof, with a thickness of 2.0 to 100 nm.

(96) The functional layer 104 is a ferroelectric or multi-ferric film. The ferroelectric or multi-ferric film generally includes Pb(Mg.sub.1/3Nb.sub.2/3)O.sub.3PbTiO.sub.3 (PMN-PT), BiFeO.sub.3 (BFO), BaTiO.sub.3 (BTO), PbTiO.sub.3 (PTO), SrTiO.sub.3 (STO), BiMnO.sub.3 or the like, with a thickness of 5 to 500 nm; a seed layer of SrRuO.sub.3 or TiO.sub.2 or the like can be deposited in advance, in order to ensure a relatively good functional layer and a relatively close binding of the functional layer to the substrate.

(97) In general, the buffer layer 105 is a non-magnetic metal layer (including a single layer or multiple layers) which has a relatively good electrical conductivity and binds closely to the substrate. The material is preferably Ta, Ru, Cr, Au, Ag, Pt, Pd, Cu, CuN or the like, or may also be a metal alloy or a metal composite layer, of which the thickness may range from 2.0 to 100 nm.

(98) The insulation layer 106 is generally made of a material, such as AlO.sub.x, MgO, Mg.sub.1-xZn.sub.xO, AlN, Ta.sub.2O.sub.5, MgAlO.sub.x, ZnO, MgSiO.sub.x, SiO.sub.2, HfO.sub.2, TiO.sub.2, Alq3, an LB organic composite film, GaAs, AlGaAs, InAs or the like, preferably made of MgO, AlO.sub.x, MgZnO, AlN and Alq3, or an LB organic composite film, with a thickness of 0.5 to 10 nm.

(99) The intermediate conductive layer 107 is a ferromagnetic metal, or a directly or indirectly pinning structure. Directly pinning means directly contacting the antiferromagnetic layer AFM with the ferromagnetic layer FM (abbreviated as AFM/FM), and indirectly pinning means interposing there between a composite layer NM/FM (abbreviated as FM1/NM/FM2/AFM).

(100) The ferromagnetic metal of the above magnetic layer 107 comprises a ferromagnetic metal with a relatively high spin polarization, preferably Co, Fe or Ni, or a film made of an alloy of these ferromagnetic metals, preferably a ferromagnetic alloy, such as CoFe, CoFeB, NiFeCr or NiFe (e.g. Ni.sub.18Fe.sub.19 or Co.sub.75Fe.sub.25), with a thickness of 2.0 to 100 nm, or a diluted magnetic semiconductor material, such as GaMnAs or GaMnN, or a semi-metallic material, such as CoMnSi, CoFeAl, CoFeSi, CoMnAl, CoFeAlSi, CoMnGe, CoMnGa, CoMnGeGa, La.sub.1-xSr.sub.xMnO.sub.3 or La.sub.1-xCa.sub.xMnO.sub.3 (where 0<X<1), with a thickness of 2.0 to 100 nm.

(101) The antiferromagnetic layer AFM of the above magnetic layer 107 comprises an antiferromagnetic alloy material, preferably PtMn, IrMn, FeMn or NiMn, with a thickness of 5 to 50 nm, or an antiferromagnetic oxide, preferably CoO or NiO, with a thickness of 5 to 50 nm. The ferromagnetic layer FM is made of a ferromagnetic metal with a relatively high spin polarization, preferably Co, Fe or Ni, or a film made of an alloy of these ferromagnetic metals, preferably a ferromagnetic alloy such as CoFe, CoFeB, NiFeCr or NiFe (e.g. Ni.sub.81Fe.sub.19 or Co.sub.75Fe.sub.25), with a thickness of 2.0 to 100 nm, or a diluted magnetic semiconductor material, such as GaMnAs or GaMnN, or a semi-metallic material, such as CoMnSi, CoFeAl, CoFeSi, CoMnAl, CoFeAlSi, CoMnGe, CoMnGa, CoMnGeGa, La.sub.1-xSr.sub.xMnO.sub.3 or La.sub.1-xCa.sub.xMnO.sub.3 (where 0<x<1), with a thickness of 2.0 to 100 nm. The ultrathin non-magnetic metal layer NM interposed between the ferromagnetic layer FM and the antiferromagnetic layer AFM is generally made of Cu, Cr, V, Nb, Mo, Ru, Pd, Ta, W, Pt, Ag, Au or an alloy thereof, with a thickness of 0.1 to 5 nm.

(102) The intermediate conductive layer is a non-magnetic metal layer with a relatively good conductivity (including a single-layer or multi-layer composite metal film). The material is preferably Ta, Cu, Ti, Ru, Au, Ag, Pt, Al, Cr, V, W, Nb or the like, with a thickness of 2.0 to 100 nm.

(103) The intermediate conductive layer is an antiferromagnetic metal layer. The material is preferably IrMn, FeMn, PtMn or NiMn, with a thickness of 5 to 50 nm. Alternatively, it is an antiferromagnetic oxide, preferably CoO, NiO or the like, with a thickness of 5 to 50 nm.

(104) The intermediate conductive layer is a conductive polymer material, a topological insulator material, or doped conductive semiconductor materials. The material is preferably Graphene, a conductive semiconductor doped material, or the like. The material is preferably a conductive material, such as Graphene, doped polyacetylene, Sb, BiTe, BiSe or SbTe.

(105) The cap layer 108 is a metal layer (including a single-layer or multi-layer composite metal film) which is not easy to oxidize and has a relatively good conductivity. The material is preferably Ta, Cu, Ti, Ru, Au, Ag, Pt or the like, with a thickness of 2.0 to 200 nm, for protecting the core structure from oxidation and corrosion.

(106) Therefore, the magnetic nano multilayer film structure of the present invention includes, but is not limited to:

(107) Structure A: BOL 1/SUB/B FL/ISO/NM (or FM, or AFM)/CAP (FIG. 1b);

(108) Structure B: SUB/BOL 2/FCL/ISO/NM (or FM, or AFM)/CAP (FIG. 1c);

(109) Structure C: SUB/BOL 2/FCL/BFL/ISO/NM (or FM, or AFM)/CAP (FIG. 1d);

(110) Structure D: SUB/BOL 2/FCL/FM1/NM/FM2/AFM/CAP (FIG. 1e);

(111) Structure E: SUB/BOL 2/FCL/FM/AFM/CAP (FIG. 1f);

(112) Structure F: SUB/BOL 2/FCL/FM1/NM/FM2/CAP (FIG. 1g); and

(113) Structure G: SUB/BOL 2/FCL/FM/CAP (FIG. 1h).

Example 1

(114) In a magnetron sputtering apparatus, 5 nm-thick Co.sub.75Fe.sub.25 was directly grown as a magnetic layer on a (001)-PMN-PT ferroelectric oxide substrate at a vacuum degree of greater than 210.sup.6 Pa, a deposition rate of 0.06 nm is, and an Ar pressure of 0.07 Pa. Then, 6 nm Ta was directly deposited as a cap layer on the 5 nm-thick Co.sub.75Fe.sub.25 magnetic layer to prevent oxidation of the Co.sub.75Fe.sub.25 magnetic layer. The obtained nano multilayer film was placed into the magnetron sputtering apparatus, and a 100 nm-thick Au film was deposited at the top of the 6 nm-thick Ta cap layer at a vacuum degree of greater than 210.sup.5 Pa, a deposition rate of 10 nm/min, and an Ar pressure of 0.1 Pa to produce a top electrode. Finally, 10 nm-thick Cr and 100 nm-thick Au films were directly deposited as the bottom electrode on the back of the (001)-PMN-PT ferroelectric oxide substrate so as to apply an electrical field.

(115) An electrical field of 8 kV/cm to 8 kV/cm is applied between the contact electrode and the Au film on the lower surface of the (001)-PMN-PT ferroelectric oxide substrate, as shown in FIG. 2a; FIG. 2b is a schematic view showing the varying external electrical field E applied between the contact electrode and the Au film on the lower surface of the (001)-PMN-PT ferroelectric oxide substrate and the measurement results of the resistance of the nano multilayer film.

Example 2

(116) In a magnetron sputtering apparatus, a Ta (5 nm) buffer layer (BFL) was deposited on a (001)-PMN-PT ferroelectric oxide substrate at a vacuum degree of greater than 110.sup.6 Pa, a deposition rate of 0.1 nm/s, and an Ar pressure of 0.07 Pa during deposition. Then, in the magnetron sputtering apparatus, AlO.sub.x with a deposition thickness of 1.0 nm was directly deposited as an insulating barrier layer on the Ta buffer layer at a vacuum degree of greater than 210.sup.6 Pa, a deposition rate of 0.07 nm/s, and an Ar pressure of 0.07 Pa. Subsequently, the magnetic metal Co.sub.73Fe.sub.25 with a thickness of 5 nm was directly deposited (alternatively, the non-magnetic metal Al with a thickness of 5 nm was directly deposited, or the antiferromagnetic layer IrMn with a thickness of 5 nm was deposited) as an intermediate conductive layer on the 1.0 nm AlO.sub.x insulating barrier layer at a vacuum degree of greater than 110.sup.6 Pa, a deposition rate of 0.1 nm/s, and an Ar pressure of 0.07 Pa during deposition. Cr with a thickness of 10 nm and Au with a thickness of about 100 nm were sputtered onto the lower surface of the (001)-PMN-PT ferroelectric oxide substrate so as to apply an electrical field. An electrical field of 8 kV/cm to 8 kV/cm was applied between the contact electrode and the Au film on the lower surface of the (001)-PMN-PT ferroelectric oxide substrate, as shown in FIG. 3a; FIG. 3b is a schematic view showing the measurement results of the varying external electrical field E and the resistance R of the nano multilayer film when the intermediate conductive layer was Co.sub.75Fe.sub.25; FIG. 3c is a schematic view showing the measurement results of the varying external electrical field E and the resistance R of the nano multilayer film when the intermediate conductive layer was Co.sub.75Fe.sub.25, wherein the measurement was performed while a magnetic field of 1 kOe was being applied, so as to measure and analyze the relationship among the resistance of the nano multilayer film, the varying external electrical field and the fixed external magnetic field. As can be seen from the figures, there is still a 260% resistance variation relationship. In addition, it can be analyzed from the measurement results that the external magnetic field does not affect the R-E curve of the nano multilayer film. This shows that the effect does not result from magnetic interaction. FIG. 3d is a schematic view illustrating the varying external electrical field E and the measurement results of the resistance R of a nano multilayer film in case the intermediate conductive layer is an Al film of 5 nm thick. As can be seen from the figure, there is still a 100% resistance variation. This implies that the effect does not result from magnetoelectric interaction. FIG. 3e is a schematic view illustrating the measurement results of the varying external electrical field E and the resistance R of a nano multilayer film in case the intermediate conductive layer is a 5 nm-thick IrMn film. As can be seen from the figure, there is still a 44% resistance variation.

(117) FIG. 4 (FIG. 4A to FIG. 4H) are schematic views illustrating the core structures of eight electric-field-modulated memory cells. The random access memory based on the aforesaid electric-field-modulated memory cells according to the present invention has a novel memory cell architecture, in which data is written by using an electrical field to regulate the electrical polarization direction of the ferroelectric material. This novel architecture requires that the memory cell have a particular cell structure, as shown in FIGS. 5 and 7. Wherein, the cell structure shown in FIG. 5 is a structure free of a transistor, while what is shown in FIG. 7 is a form having a transistor.

(118) For the cell structures shown in figure, the array thereof is shown in FIG. 6. For transistor-containing cells, the cell array is shown in FIG. 8.

Example 3

(119) The present invention provides a novel array of electric-field-modulated memory cells. FIG. 5A (FIG. 5A1, FIG. 5A2 and FIG. 5A3) exemplifies the structure of the cell array.

(120) The conductive layer of the multi-layer film in the cell is connected to 2a and 2b via 1a and 1b. The buffer layer is connected to 2c via 1c. The bottom layer is connected to 2d via 1d.

(121) The multi-layer film in the cell is connected to 2a, 2b, 2c and 2d via 1a, 1b, 1c, and 1d, respectively, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(122) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(123) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(124) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(125) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(126) The wires 4a and 2d are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 4a and 2d to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data.

(127) Based on such a cell structure, the form shown in FIG. 3 constitutes a memory cell array. Wherein, each cell is connected with four metal wires. Metal wires 2a and 4a are used for data reading, corresponding to RL1 and RL0, respectively, as shown in FIG. 3. When data is being read, an appropriate positive voltage is applied to RL1 to read the data of the cell. Metal wires 4b and 2d are used for data writing, corresponding to WL0 and WL1, respectively, as shown in FIG. 4. When data is being written, an appropriate voltage is applied between WL0 and WL1 to reverse the electrical dipole moment of the functional layer, thereby writing data into the conductive layer. To achieve a positive voltage between WL1 and WL0, WL0 can be grounded while a positive voltage is applied to the wire WL1. To achieve a negative voltage between WL1 and WL0, WL1 can be grounded while a positive voltage is applied to the wire WL0.

Example 4

(128) The present invention provides a novel memory cell array of electrical field modulation type. FIG. 5B (FIG. 5B1, FIG. 5B2, FIG. 5B3) exemplifies the structure of the cell array.

(129) The conductive layer of the multi-layer film in the cell is connected to 2a, 2b and 2c via 1a, 1b and 1c. The bottom layer is connected to 2d via 1d, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(130) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(131) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(132) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(133) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(134) The wires 4a and 2d are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 4a and 2d to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data.

(135) Based on such a cell structure, the form shown in FIG. 3 constitutes a memory cell array. Wherein, each cell is connected with four metal wires. Metal wires 2a and 4b are used for data reading, corresponding to RL1 and RL0, respectively, as shown in FIG. 6. When data is being read, an appropriate positive voltage is applied to RL1 to read out the data in the cell. Metal wires 4a and 2d are used for data writing and corresponding to WL0 and WL1, respectively, as shown in FIG. 7. When data is being written, an appropriate voltage is applied between WL0 and WL1 to reverse the electrical dipole moment of the functional layer, thereby writing data into the conductive layer. To achieve a positive voltage between WL1 and WL0, WL0 can be grounded while a positive voltage is applied to the wire WL1. To achieve a negative voltage between WL1 and WL0, WL1 can be grounded while a positive voltage is applied to the wire WL0.

Example 5

(136) The present invention provides a novel memory cell array of electrical field modulation type. FIG. 5C (FIG. 5C1, FIG. 5C2 and FIG. 5C3) exemplifies the structure of the cell array.

(137) The conductive layer of the multi-layer film in the cell is connected to 2a and 2b via 1a and 1b. The buffer layer is connected to 2c via 1c. The bottom layer on the back of the substrate is connected to 2d via 1d.

(138) The multi-layer film in the cell is connected to 2a, 2b, 2c and 2d via 1a, 1b, 1c, and 1d, respectively, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(139) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(140) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(141) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(142) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(143) The wires 4a and 2d are used for data writing. When data is being written, an electrical field is generated in the functional layer by applying appropriate positive and negative voltages to 4a and 2d, so as to change the resistivity of the conductive layer, thereby storing 0 and 1 of data.

(144) The array thus formed is similar to those described in Examples 1 and 2, as shown in FIG. 6.

Example 6

(145) The present invention provides a novel memory cell array of electrical field modulation type. FIG. 5D (FIG. 5D1, FIG. 5D2 and FIG. 5D3) exemplifies the structure of the cell array.

(146) The conductive layer of the multi-layer film in the cell is connected to 2a, 2b and 2c via 1a, 1b and 1c. The bottom layer on the back of the substrate is connected to 2d via 1d, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(147) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(148) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(149) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(150) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(151) The wires 4a and 2d are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 4a and 2d to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data. The array thus formed is similar to those described in Examples 1 and 2, as shown in FIG. 6.

Example 7

(152) The present invention provides a novel memory cell array of electrical field modulation type. FIG. 5E (FIG. 5E1, FIG. 2E2 and FIG. 5E3) exemplifies the structure of the cell array.

(153) The conductive layer of the multi-layer film in the cell is connected to 2a and 2b via 1a and 1b. The buffer layer is connected to 2c via 1c. The bottom layer on the back of the substrate is connected to 2d via 1d.

(154) The multi-layer film in the cell is connected to 2a, 2b, 2c and 2d via 1a, 1b, 1c, and 1d, respectively, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(155) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(156) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(157) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(158) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(159) The wires 4a and 2d are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 4a and 2d to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data. The array thus formed is similar to those described in Examples 1 and 2, as shown in FIG. 6.

Example 8

(160) The present invention provides a novel memory cell array of electrical field modulation type. FIG. 5F (FIG. 5F1, FIG. 5F2 and FIG. 5F3) exemplifies the structure of the cell array.

(161) The conductive layer of the multi-layer film in the cell is connected to 2a, 2b and 2c via 1a, 1b and 1c. The bottom layer on the back of the substrate is connected to 2d via 1d, wherein 2a and 2d are metal wires adapted for connecting all memory cells, 2a and 2d are on the same layer and parallel to each other, and 2b and 2c are transition metal layers.

(162) The electrodes of the transition metal layers 2b and 2c are connected to wires 4a and 4b through via holes 3a and 3b, respectively, wherein 4a and 4b are metal wires adapted for connecting all memory cells, and 4a and 4b are on the same layer and parallel to each other.

(163) The wires 2a and 4b are perpendicular to each other for data reading for a cell at the intersection.

(164) When the wires 2a and 4b are being used for data reading, a low current is passed between 2a and 4b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(165) The wires 4a and 2d are perpendicular to each other for data writing for a cell at the intersection.

(166) The wires 4a and 2d are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 4a and 2d to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data. The array thus formed is similar to those described in Examples 1 and 2, as shown in FIG. 6.

Example 9

(167) According to Example 1, an electrical field is applied to the memory cell not in a mode of vertical-direction application but in a mode of in-plane application. The structure is shown in FIG. 5G (FIG. 5G1, FIG. 5G2, FIG. 5G3, FIG. 5G4, FIG. 5G5 and FIG. 5G6), wherein the electrodes for applying an electrical field are at both ends of the functional layer so as to apply an in-plane electrical field.

Example 10

(168) The present invention further provides a novel memory cell array of electrical field modulation type. FIG. 7 (FIG. 7A, FIG. 7B and FIG. 7C) exemplifies the structure of the cell array.

(169) The bottom layer of the multi-layer film in the cell is connected to the drain electrode 2c of the transistor through via a hole 3a.

(170) The source electrode of the transistor in the cell is connected to the wire 2a via 1a. The wire 2a connects the source electrodes of all the transistors and ground them.

(171) The gate of the transistor is connected to the wire 2b via 1b. The wire 2b connects the gates in all the cells.

(172) The bottom layer of the multi-layer film in the cell is connected to the metal wire 5c through a via hole 4d. The conductive layer is connected to the metal wire 5c through a via hole 4c. The metal wire 5c is grounded.

(173) The conductive layer of the multi-layer film in the cell is connected to Sb via 4a. The buffer layer is connected to 5a via 4a.

(174) In the cell, 5a and 5b are connected to metal wires 7a and 7b via 6a and 6b, respectively. The metal wires 7a and 7b are on the same layer and parallel to each other.

(175) Both of the metal wires 7a and 7b are perpendicular to the metal wire 2b, wherein 7a and 2b are adapted for writing data, and 7b and 2b for reading data.

(176) When the wires 7b and 2b are being used for data reading, a low current is passed between 7a and 2b and the voltages at both ends are measured to thereby obtain a high resistance state 1 or a low resistance state 0.

(177) The wires 7a and 2b are used for data writing. When data is being written, appropriate positive and negative voltages are applied to 7a and 2b to generate an electrical field in the functional layer to change the resistivity of the conductive layer, thereby storing 0 and 1 of data.

(178) Based on such a cell structure, the form shown in FIG. 5A constitutes a memory cell array. Wherein, each cell is connected with three operable metal wires and one ground wire. Metal wire 2b, corresponding to WRL shown in FIG. 6, is adapted for forming a cross structure together with a metal wire for reading or for writing, so as to select a memory cell. WRL is adapted for opening the transistor in the bottom of the cell. Metal wires 7b and 2b are adapted for reading data, wherein 7b corresponds to the metal wire RL, as shown in FIG. 5A.

(179) When data is being read, an appropriate positive voltage is applied to WRL to thereby open the transistor in the cell. Meanwhile, a positive voltage is applied to RL to read the data of the selected cell.

(180) The metal wires 7a and 2b are adapted for reading data, wherein 7a corresponds to the metal wire WL, as shown in FIG. 5A. When data is being written, an appropriate positive voltage is applied to WRL to thereby open the transistor in the cell. Meanwhile, a voltage is applied to WL to write data into the selected cell. An appropriate positive or negative voltage is applied between the metal wires WL and WRL to reverse the electrical dipole moment of the functional layer, thereby writing data into the conductive layer.

Example 11

(181) According to the cell array structure set forth in Example 8, an array shown in FIG. 8B is constituted.

(182) Wherein, each cell is connected to three operable metal wires. In addition, the source electrode of each transistor is grounded directly through a metal via hole.

Example 12

(183) According to one example of the present invention, a random access memory based on the novel array of electric-field-modulated memory cells as set forth in Example 1 is provided. FIG. 9 shows the overall structure of the random access memory in this example, the random access memory comprising a basic row decoder, a sense amplifier and a column decoder, a register, a control circuit, a read-write drive, a register, input and output, etc. The memory array disclosed in any of the aforementioned examples and the corresponding read-write circuit can be used as the memory array and the read-write circuit thereof in this example. It is worth noting that the structure chart in this example is only a particular example of the design of a memory, and some changes made to the structure chart, e.g., changes in the structure of the array and in the wiring, are within the scope of spirit of the design of this structure and all should be included in and belong to the design of this example.

Example 13

(184) According to one example of the present invention, similar to Example 10, a random access memory based on the novel memory cell array of electrical field modulation type as set forth in Example 2, 3, 4, 5, 6, 7, 8 or 9 is provided.

Example 14

(185) FIGS. 10A and 10B show the core structure of an ER FET (FET-ER1) and the self-defined electrical symbols. Its structure is an electrode layer/a functional layer/a buffer layer/an insulating barrier layer/a conductive layer, and a FET shown in FIG. 10 is obtained by film deposition and photolithography. The FET has four electrodes in all, wherein two electrodes from each of the bottom layer and the buffer layer are used as the control electrodes {circle around (1)} and {circle around (2)}, and also two electrodes {circle around (3)} and {circle around (4)} at both ends of the conductive layer are connected to an external circuit. When a forward voltage is applied between the bottom layer and the buffer layer, it will form an electrical field in the functional layer, and when the voltage gradually increases from zero, the electrical field applied onto the functional layer gradually increases as well. When the electrical field is less than a certain threshold value, the resistance of the conductive layer does not change; however, when the electrical field exceeds the threshold value, the resistance of the conductive layer may change suddenly from a high resistance state to a low resistance state or from a low resistance state to a high impedance state. When the electrical field is reversed and exceeds a certain threshold value, the resistance of the conductive layer will change suddenly once again.

(186) As seen in FIG. 10A and FIG. 10B, the four electrodes are located on different layers and the electrodes are insulated from each other by SiO.sub.2, thus hierarchical wiring can be realized during the actual circuit design, which will greatly reduce the difficulty in wiring and can increase the number of integrated devices. There can be three wiring layers in the entire circuit: an electrode layer in the bottom generally serves as a reference layer of the wiring, with the potential of this layer unchanged, so it is positioned on the lowest layer of the multilayer circuit board, and in a set of circuit, a plurality of the FETs according to the invention can all be connected to this reference layer so as to uniformly connect to the reference potential; a buffer layer in the middle serves as a control layer of the wiring, and the control electrodes of all the FETs are located on this layer; a conductive layer at the top serves as a circuit layer of the wiring, with most of the circuit being disposed on this layer, and this layer can be connected to the control layer through a via hole.

(187) The potentials of the reference layer and the control layer as mentioned above may be crossly exchanged, so that the FET can vary between a high resistance state and a low resistance state, as shown in Type 1 of Table 1; however, this method causes each FET to have an additional peripheral circuit, thereby lowering the integration level. Similarly, the potential of the reference layer may remain zero, i.e., be grounded, then the voltage of the control layer must have both the function of inputting a positive voltage and the function of inputting a negative voltage, in order for the FET according to the invention to vary between a high resistance state and a low resistance state, as shown in Type 2 of Table 1. This type of control mode requires an additional circuit for generating a negative voltage, but each transistor does not need an additional external circuit; the potential of the reference layer can also be kept at a constant value V.sub.m, then a high voltage V.sub.H or a low voltage V.sub.L is applied to the control layer, wherein V.sub.m=(V.sub.H+V.sub.L)/2, it is defined that V.sub.=V.sub.HV.sub.m, the electrical field generated by V.sub. is greater than the reversed electrical field of electroresistance, whereby a switch between a high resistance state and a low resistance state can be achieved when the voltage on the electrode varies between a high voltage and a low voltage, as shown in Type 3 of Table 1. The design of such a circuit is the simplest, but the selection of the reference voltage needs to be very precise, otherwise a misoperation will be caused.

(188) TABLE-US-00001 TABLE 1 Listing of Control States (FET-ER1) Type Control Layer Reference Layer Circuit Layer 1 High Voltage Zero Voltage Low resistance state Zero Voltage High Voltage High resistance state 2 Positive Voltage Zero Voltage Low resistance state Negative Voltage Zero Voltage High resistance state 3 High Voltage Reference Voltage Low resistance state Zero Voltage Reference Voltage High resistance state

Example 15

(189) FIGS. 11A and 11C show the basic structure of a complementary ER FET (FET-ER2) and the self-defined electrical symbols. The basic structure of the complementary ER FET according to the invention is a conductive layer/an insulating barrier layer/a buffer layer/a functional layer/a buffer layer/an insulating barrier layer/a conductive layer. It has a total of six electrodes, wherein the two buffer layers have electrodes {circle around (1)} and {circle around (2)}, respectively, as the control electrodes, and the conductive layers on the left and right sides have electrodes {circle around (3)} {circle around (4)} and electrodes {circle around (5)} {circle around (6)}, respectively, which can be connected to an external circuit. When voltages are applied to both the buffer layers, a polarized electrical field can be generated in the functional layer, and the electrical field will act on the conductive layers on the two sides to induce their resistances to reverse; however, since the conductive layers on the two sides are in reverse symmetry, their resistance states are just opposite and complementary to each other.

(190) TABLE-US-00002 TABLE 2 Listing of Control States (FET-ER2) Control Control Conductive Conductive Type Electrode 1 Electrode 2 Layer 1 Layer 2 1 High Voltage Zero Voltage High Low resistance resistance state state Zero Voltage High Voltage Low High resistance resistance state state 2 Positive Voltage Zero Voltage High Low resistance resistance state state Negative Zero Voltage Low High Voltage resistance resistance state state 3 High Voltage Reference High Low Voltage resistance resistance state state Zero Voltage Reference Low High Voltage resistance resistance state state

(191) The complementary FETs can be controlled in three ways, as specified in Table 2. The first type is interleaving control, i.e., the positive or negative of the electrical field is controlled by switching between the voltages of the two control electrodes; the second type is positive-negative control, i.e., the voltage of one control electrode remains zero and the voltage of the other control electrode has two polarities, wherein when the polarity of said electrode's voltage is changed, the resistance state of the complementary FET will change as well, as shown in Type 2 of Table 2; the third type is reference control, i.e., the potential of the control electrode 2 is kept at the reference voltage, namely the constant value V.sub.m, and a high voltage V.sub.H or a zero voltage is applied to the control electrode 1, wherein V.sub.m=V.sub.H/2 (it is defined that V.sub.=V.sub.HV.sub.m), the electrical field generated by V.sub. is greater than the reversed electrical field of electroresistance, whereby a switch between a high resistance state and a low resistance state can be achieved when the voltage on the electrode varies between a high voltage and a low voltage, as shown in Type 3 of Table 2.

(192) As seen in FIG. 11, the six electrodes are located on different layers and the electrodes are insulated from each other by SiO.sub.2, thus hierarchical wiring can be realized during the actual circuit design. There can be three wiring layers in the entire circuit: in the bottom is a control layer of the wiring, with the control electrodes of all the FETs being located on this layer; a conductive layer in the middle serves as a circuit layer 1 of the wiring, a conductive layer at the top serves as a circuit layer 2 of the wiring, wherein most of the circuits are disposed on these two layers, and these two layers can be connected to each other and to the control layer through via holes.

Example 16

(193) The basic circuits of an inverter, a NAND gate and a NOR gate can be obtained by using the FET-ER1 according to the invention and an externally applied conventional resistance, as shown in FIGS. 12A, 12B, and 12C, respectively. Next, each of the circuits will be described separately.

(194) The logic circuit of an inverter is shown in FIG. 12A, wherein R1 is an external resistor, and Q1 is the FET-ER1 according to the invention. The FET has a total of four electrodes, two of which are control electrodes and the other two are connected to external circuits. One of the two control electrodes is connected to a reference voltage REFERENCE, and the other serves as an input port INPUT, and the output port OUTPUT is as shown in the figure.

(195) The reference voltage REFERENCE may be a constant value V.sub.m, a high voltage V.sub.H or a zero voltage is applied to the input port INPUT, wherein V.sub.m=V.sub.H/2, it is defined that V.sub.=V.sub.HV.sub.m, the electrical field generated by V.sub. is greater than the reversed electrical field of electroresistance, whereby a switch between a high resistance state and a low resistance state can be achieved when the voltage on the electrode varies between a high voltage and a low voltage.

(196) The logic state of the entire circuit is shown in Table 3A. In case of high-level input, i.e., logic 1, according to the state of control of the FET-ER1 as shown in Type 3 of Table 1, the FET then is in a low resistance state RL. When RL<<R1, according to the relationship of voltage division in series, then VRL<<VR1, the output is a low voltage i.e., logic 0. Similarly, in case of low-level input, i.e., logic 0, according to the state of control of the FET-ER1 as shown in Type 3 of Table 1, the FET then is in a high resistance state RH. When RH>>R1, according to the relationship of voltage division in series, then VRL>>VR1, the output is a high voltage, i.e., logic 1. Therefore the logic functions of the inverter can be achieved.

(197) TABLE-US-00003 TABLE 3A Logic state table of a FET-ER1 inverter (OUTPUT = INPUT) REFERENCE INPUT OUTPUT Q1 Constant Value V.sub.m 1 0 Low resistance state R.sub.L Constant Value V.sub.m 0 1 High resistance state R.sub.H

(198) The logic circuit of a NAND gate is shown in FIG. 12B, wherein R2 is an external resistor, Q2 and Q7 are each the FET-ER1 according to the invention, and they are connected in series with the resistor in the circuit. Each of the FETs has four electrodes, two of which are control electrodes and the other two are connected to external circuits. One of the two control electrodes is connected to a reference voltage REFERENCE, and the other serves as an input port INPUT. The two input ports are labeled INPUT1 and INPUT2, respectively. The output port OUTPUT is as shown in the figure.

(199) As concerns each said FET-ER1, the reference voltage REFERENCE may be a constant value V.sub.m, a high voltage V.sub.H or a zero voltage is applied to the input port INPUT, wherein V.sub.m=V.sub.H/2, it is defined that V.sub.=V.sub.HV.sub.m, the electrical field generated by V.sub. is greater than the reversed electrical field of electroresistance, whereby a switch between a high resistance state and a low resistance state can be achieved when the voltage on the electrode varies between a high voltage and a low voltage.

(200) TABLE-US-00004 TABLE 3B Logic state table of FET-ER1 and a NAND gate (OUTPUT = INPUT1.Math. INPUT2) REF- ERENCE INPUT1 INPUT2 OUTPUT Q2 Q7 Constant 0 0 1 High High Value V.sub.m resistance resistance state R.sub.H state R.sub.H Constant 0 1 1 High High Value V.sub.m resistance resistance state R.sub.H state R.sub.H Constant 1 0 1 Low High Value V.sub.m resistance resistance state R.sub.L state R.sub.H Constant 1 1 0 Low Low Value V.sub.m resistance resistance state R.sub.L state R.sub.L

(201) The logic state of the entire circuit is shown in Table 3B. The low resistance state and the high resistance state of the FET satisfy RH>>R2>>RL. The specific analysis is as follows:

(202) In case of low-level INPUT1 and INPUT2, i.e., logic 0, according to the state of control of the FET-ER1 as shown in Type 3 of Table 1, each of the two FETs then is in a high resistance state RH. According to the relationship of voltage division in series, then VRH1+VRH2>>VR2, the output is a high voltage, i.e., logic 1.

(203) In case of low-level INPUT1, i.e., logic 0, and high-level INPUT2, i.e., logic 1, according to the state of control of the FET-ER1 as shown in Type 3 of Table 1, the FET corresponding to INPUT1 then is in a high resistance state RH1, while the FET corresponding to INPUT2 then is in a low resistance state RL2. According to the relationship of voltage division in series, then VRH1+VRL2>>VR2, the output is a high voltage, i.e., logic 1.

(204) In case of high-level INPUT1, i.e., logic 1, and low-level INPUT2, i.e., logic 0, according to the control state of the FET-ER1 as shown in Type 3 of Table 1, the FET corresponding to INPUT1 then is in a low resistance state RL1, while the FET corresponding to INPUT2 then is in a high resistance state RH2. According to the relationship of voltage division in series, then VRL+VRL2>>VR2, the output is a high voltage, i.e., logic 1.

(205) In case of high-level INPUT1 and INPUT2, i.e., logic 1, according to the control state of the FET-ER1 as shown in Type 3 of Table 1, both of the two FETs are in a low resistance state RL1. According to the relationship of voltage division in series, then VRL1+VRL2<<VR2, the output is a low voltage, i.e., logic 0.

Example 17

(206) A look-up table of a nonvolatile field programmable gate array (FPGA) can be obtained by using the FET-ER1 and the complementary FET-ER2 according to the invention. By means of a random access memory based on an ER effect, a FPGA which is fully based on such ER effect can be obtained and, accordingly, can entirely replace the existing FPGA fabricated with a semiconductor device.

(207) In this example, a basic circuit of a look-up table with double input channels is introduced, as shown in FIG. 14A, and a look-up table with 2.sup.n input channels can also be designed according to this principle. Hereinafter, the circuit of a look-up table with double input channels is introduced in detail.

(208) Q5, Q6 and Q11 are each a complementary ER FET-ER2, Q10, Q15, Q16 and Q17 are each an ER FET-ER1, and R4 is a pull-up network. The electrodes of each FET are connected as shown in the figure. INPUT1 and INPUT2 serve as strobe input ports, and WRITE1, WRITE2, WRITE3 and WRITE4 are state write ports. Any one of Q10, Q15, Q16 and Q17 can be gated by INPUT1 and INPUT2. In this way, the resistance state of Q10, Q15, Q16 or Q17 can be read through the pull-up network R4. In addition, the resistance state of Q10, Q15, Q16 or Q17 can be artificially pre-set through WRITE1, WRITE2, WRITE3 or WRITE4, so that it can be used in any two-input logic operation. According to theoretical calculations, each device has two states, so there should be 2.sup.4=16 combinations of states, i.e., sixteen kinds of logical operations. Hereinafter, some basic logic operation truth tables, including NAND Gate Truth Table 5B, are introduced.

(209) TABLE-US-00005 TABLE 5A Listing of Strobe of a look-up table in FPGA Resistance State of INPUTA INPUTB Strobe Device Device 0 0 Q10 High resistance state/Low resistance state 0 1 Q15 High resistance state/Low resistance state 1 0 Q16 High resistance state/Low resistance state 1 1 Q17 High resistance state/Low resistance state

(210) TABLE-US-00006 TABLE 5B NAND gate truth table (OUTPUT = INPUT1.Math. INPUT2) Preset Resistance State INPUTA INPUTB Strobe Device of Device OUTPUT 0 0 Q10 High resistance 1 state 0 1 Q15 High resistance 1 state 1 0 Q16 High resistance 1 state 1 1 Q17 Low resistance 0 state

(211) The nano multilayer film structure described below can be used in the above-mentioned core structure of the present invention.

(212) The object of the present invention is to present a nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type and a random access memory of electrical field drive type, configured to achieve a novel reversible ER effect by regulating nano multilayer films under an electrical field at room temperature, and to use the reversible ER effect in electronic devices.

(213) Compared with the ordinary FETs, the novel FET controlled by electrical field according to the present invention is significantly different in the following aspects: on the one hand, the FET according to the invention is controlled by an electrical field and has a higher input impedance up to the order of M, so that the input leakage current is relatively small and will not affect the signals input into the circuit; on the other hand, the FET according to the invention is non-volatile, i.e. the FET maintains the original resistance state when the electrical field working on the gate disappears, so, only one control pulse needs to be input in advance but does not need to be maintained during the work, thereby greatly reducing the electrical loss of the circuit and reducing the power consumption of devices.

Example 18

(214) FIG. 15A is a schematic view showing a logic device based on structure h in Scheme 2, and FIG. 15B is the corresponding truth table. Structure: a substrate/a bottom layer/a functionally pinning layer (FPL)/a buffer layer/a barrier layer/a conductive layer (CL)/a functionally free layer (FFL)/a cap layer.

(215) Wherein, the substrate is an insulating material; the bottom layer is a conductive material for applying an electrical field to the functionally pinning layer and the functionally free layer; the functionally pinning layer is a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is a conductive material for reducing the roughness of the barrier layer; the barrier layer is an oxide; the conductive layer is a conductive inorganic or organic material; the functionally free layer is a ferroelectric or multiferroic material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the cap layer is a protective layer for preventing the oxidation of the structure.

(216) Circuit Connection:

(217) 1. Four collinear point electrodes are obtained on the surface of the cap layer by such methods as UV exposure, argon ion etching, and post-deposition of metals: the resistance in a high resistance state is denoted by a logic output 1 (the polarization intensity of the functionally pinning layer is downward, and the polarization intensity of the functionally free layer is downward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functionally pinning layer is downward, and the polarization intensity of the functionally free layer is upward; the polarization intensity of the functionally pinning layer is upward, and the polarization intensity of the functionally free layer is downward; the polarization intensity of the functionally pinning layer is upward, and the polarization intensity of the functionally free layer is upward).

(218) 2. Two identical input electrical field intensities E.sub.A and E.sub.B are applied between the bottom layer and the cap layer, wherein both E.sub.A and E.sub.B are greater than the coercive field intensity of the functionally free layer but smaller than the coercive field intensity of the functionally pinning layer, and E.sub.A+E.sub.R is greater than the coercive field intensity of the functionally pinning layer. E.sub.A, E.sub.B>0 is denoted by a logic input 1, and E.sub.A, E.sub.B<0 is denoted by a logic input 0.

(219) NAND Logic (See FIG. 15B1 for the Truth Table)

(220) 1. Input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and set the initial output logic state C=1;

(221) 2. Rules for logical operation:

(222) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1;

(223) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1;

(224) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1; and

(225) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0.

(226) NOR Logic (See FIG. 15B2 for the Truth Table)

(227) 1. Input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward; disconnect input B and input a logic state A=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state C=0;

(228) 2. Rules for logical operation:

(229) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1;

(230) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0;

(231) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=0; and

(232) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0.

(233) NOR Logic (See FIG. 15B3 for the Truth Table)

(234) 1. Input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward; disconnect input B and input a logic state A=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state C=0;

(235) 2. Rules for logical operation:

(236) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1;

(237) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and output a logic state C=0;

(238) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and output a logic state C=0; and

(239) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0.

(240) NOR Logic (See FIG. 15B4 for the Truth Table)

(241) 1. Input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state C=0;

(242) 2. Rules for logical operation:

(243) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state C=1;

(244) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0;

(245) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0; and

(246) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state C=0.

Example 19

(247) FIG. 16A is a schematic view showing a logic device based on Structure h in Scheme 3, and FIG. 16B is the corresponding truth table. Structure: a substrate/a bottom layer/a functionally pinning layer/a buffer layer/a barrier layer/a conductive layer/a functionally free layer/a cap layer.

(248) Wherein, the substrate is of an insulating material; the bottom layer is of a conductive material for applying an electrical field to the functionally pinning layer and the functionally free layer; the functionally pinning layer is of a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is of a conductive material for reducing the roughness of the barrier layer; the barrier layer is of an oxide; the conductive layer is of a conductive inorganic or organic material; the functionally free layer is of a ferroelectric or multiferroic material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the cap layer is a protective layer for preventing the oxidation of the structure.

(249) Circuit Connection:

(250) 1. Four collinear point electrodes are obtained on the surface of the cap layer by such methods as UV exposure, argon ion etching, and post-deposition of metals: the resistance in a high resistance state is denoted by a logic output 1 (the polarization intensity of the functionally pinning layer is downward, and the polarization intensity of the functionally free layer is downward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functionally pinning layer is downward, and the polarization intensity of the functionally free layer is upward; the polarization intensity of the functionally pinning layer is upward, and the polarization intensity of the functionally free layer is downward; the polarization intensity of the functionally pinning layer is upward, and the polarization intensity of the functionally free layer is upward).

(251) 2. Three identical input electrical field intensities E.sub.A, E.sub.B and E.sub.C are applied between the bottom layer and the cap layer: both E.sub.A and E.sub.B are less than the coercive field intensity of the functionally free layer, E.sub.A+E.sub.1 is greater than the coercive field intensity of the functionally free layer, E.sub.A+E.sub.B is smaller than the coercive field intensity of the functionally pinning layer, and E.sub.A+E.sub.B+E.sub.C is greater than the coercive field intensity of the functionally pinning layer. E.sub.A, E.sub.B and E.sub.C>0 is denoted by a logic input 1, and E.sub.A, E.sub.B and E.sub.C<0 is denoted by a logic input 0. Wherein, E.sub.C denotes a control input.

(252) NOR Logic (See FIG. 16B1 for the Truth Table)

(253) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward; disconnect input C and input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state D=0;

(254) 2. Rules for logical operation:

(255) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(256) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0;

(257) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0; and

(258) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0.

(259) NOR Logic (See FIG. 16B2 for the Truth Table)

(260) 1. Input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward; disconnect input C and input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and set the initial output logic state D=0;

(261) 2. Rules for logical operation:

(262) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(263) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and output a logic state D=0;

(264) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and output a logic state D=0; and

(265) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is downward, and output a logic state D=0.

(266) NOR Logic (See FIG. 16B3 for the Truth Table)

(267) 1. Input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state D=0;

(268) 2. Rules for logical operation:

(269) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(270) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0;

(271) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0; and

(272) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0.

(273) NAND Logic (See FIG. 16B4 for the Truth Table)

(274) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and set the initial output logic state D=1;

(275) 2. Rules for logical operation:

(276) 1) input logic states A=0, B=0, C=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(277) 2) input logic states A=0, B=1, C=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(278) 3) input logic states A=1, B=0, C=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1; and

(279) 4) input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is upward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0.

(280) NAND Logic (See FIG. 16B5 for the Truth Table)

(281) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and set the initial output logic state D=1;

(282) 2. Rules for logical operation:

(283) 1) input logic states A=0, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(284) 2) input logic states A=0, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(285) 3) input logic states A=1, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1; and

(286) 4) input logic states A=1, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0.

(287) NOR Logic (See FIG. 16B6 for the Truth Table)

(288) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward; disconnect input C and input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and set the initial output logic state D=0;

(289) 2. Rules for logical operation:

(290) 1) input logic states A=0, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and output a logic state D=1;

(291) 2) input logic states A=0, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0;

(292) 3) input logic states A=1, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0; and

(293) 4) input logic states A=1, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is upward, and output a logic state D=0.

Example 20

(294) FIG. 17A is a schematic view showing a logic device based on Structure d in Scheme 1, and FIG. 17B is the corresponding truth table. Structure: a substrate/a bottom layer/a functional layer/a buffer layer/a barrier layer/a conductive layer/a cap layer.

(295) Wherein, the substrate is of an insulating material; the bottom layer is of a conductive material for applying an electrical field to the functional layer; the functional layer is of a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is of a conductive material for reducing the roughness of the barrier layer; the barrier layer is of an oxide; the conductive layer is of a conductive inorganic or organic material; the cap layer is a protective layer for preventing the oxidation of the magnetic layer.

(296) Circuit Connection:

(297) 1. Four point-contact electrodes are fabricated on the cap layer by a collinearly method: the resistance in a high resistance state is denoted by a logic output 1 (the polarization intensity of the functional layer is downward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functional layer is upward).

(298) 2. Two identical input electrical field intensities E.sub.A and E.sub.B are applied between the bottom layer and the cap layer: both E.sub.A and E.sub.B are less than the coercive field intensity of the functional layer, and E.sub.A+E.sub.B is greater than the coercive field intensity of the functional layer. E.sub.A, E.sub.B>0 is denoted by a logic input 1, and E.sub.A, E.sub.B<0 is denoted by a logic input 0.

(299) NAND Logic (See FIG. 17B1 for the Truth Table)

(300) 1. Input logic states A=0, B=0, so that the polarization intensity of the functional layer is downward, and set the initial output logic state C=1;

(301) 2. Rules for logical operation:

(302) 1) input logic states A=0, B=0, so that the polarization intensity of the functional layer is downward, and output a logic state C=1;

(303) 2) input logic states A=0, B=1, so that the polarization intensity of the functional layer is downward, and output a logic state C=1;

(304) 3) input logic states A=1, B=0, so that the polarization intensity of the functional layer is downward, and output a logic state C=1; and

(305) 4) input logic states A=1, B=1, so that the polarization intensity of the functional layer is upward, and output a logic state C=0.

(306) NOR Logic (See FIG. 17B2 for the Truth Table)

(307) 1. Input logic states A=1, B=1, so that the polarization intensity of the functional layer is upward, and set the initial output logic state C=0;

(308) 2. Rules for logical operation:

(309) 1) input logic states A=0, B=0, so that the polarization intensity of the functional layer is downward, and output a logic state C=1;

(310) 2) input logic states A=0, B=1, so that the polarization intensity of the functional layer is upward, and output a logic state C=0;

(311) 3) input logic states A=1, B=0, so that the polarization intensity of the functional layer is upward, and output a logic state C=0; and

(312) 4) input logic states A=1, B=1, so that the polarization intensity of the functional layer is upward, and output a logic state C=0.

Example 21

(313) FIG. 18A is a schematic view showing a logic device based on Structure h in Scheme 4, and FIG. 18B is the corresponding truth table. Structure: a substrate/a functionally pinning layer/a buffer layer/a barrier layer/a conductive layer/a functionally free layer/a cap layer.

(314) Wherein, the substrate is an insulating material; the functionally pinning layer is a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is a conductive material for reducing the roughness of the barrier layer; the barrier layer is an oxide; the conductive layer is a conductive inorganic or organic material; the functionally free layer is a ferroelectric or multiferroic material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the cap layer is a protective layer for preventing the oxidation of the structure.

(315) Circuit Connection:

(316) 3. Four collinear point electrodes are obtained on the surface of the cap layer by such methods as UV exposure, argon ion etching, and post-deposition of metals: the resistance in a high resistance state is denoted by a logic output 1 (the polarization intensity of the functionally pinning layer is leftward, and the polarization intensity of the functionally free layer is leftward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functionally pinning layer is leftward, and the polarization intensity of the functionally free layer is rightward; the polarization intensity of the functionally pinning layer is rightward, and the polarization intensity of the functionally free layer is leftward; the polarization intensity of the functionally pinning layer is rightward, and the polarization intensity of the functionally free layer is rightward).

(317) 4. Two electrodes are respectively prepared on the left and right sides of each of the functionally pinning layer and the functionally free layer by such methods as UV exposure, argon ion etching, and post-deposition of metals and insulating materials, and two identical in-plane input electrical field intensities E.sub.A and E.sub.B are applied to the functionally pinning layer and the functionally free layer: both E.sub.A and E.sub.B are greater than the coercive field intensity of the functionally free layer but less than the coercive field intensity of the functionally pinning layer, and E.sub.A+E.sub.B is greater than the coercive field intensity of the functionally pinning layer. E.sub.A, E.sub.B>0 is denoted by a logic input 1, and E.sub.A, E.sub.B<0 is denoted by a logic input 0.

(318) NAND Logic (See FIG. 18B1 for the Truth Table)

(319) 1. Input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and set the initial output logic state C=1;

(320) 2. Rules for logical operation:

(321) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1;

(322) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1;

(323) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1; and

(324) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0.

(325) NOR Logic (See FIG. 18B2 for the Truth Table)

(326) 1. Input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward; disconnect input B and input a logic state A=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and set the initial output logic state C=0;

(327) 2. Rules for logical operation:

(328) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1;

(329) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0;

(330) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=0; and

(331) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0.

(332) NOR Logic (See FIG. 18B3 for the Truth Table)

(333) 1. Input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward; disconnect input B and input a logic state A=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and set the initial output logic state C=0;

(334) 2. Rules for logical operation:

(335) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1;

(336) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=0;

(337) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=0; and

(338) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0.

(339) NOR Logic (See FIG. 18B4 for the Truth Table)

(340) 1. Input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and set the initial output logic state C=0;

(341) 2. Rules for logical operation:

(342) 1) input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state C=1;

(343) 2) input logic states A=0, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0;

(344) 3) input logic states A=1, B=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0; and

(345) 4) input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state C=0.

Example 22

(346) FIG. 19A is a schematic view showing a logic device based on Structure h in Scheme 4, and FIG. 19B is the corresponding truth table. Structure: a substrate/a functionally pinning layer/a buffer layer/a barrier layer/a conductive layer/a functionally free layer/a cap layer.

(347) Wherein, the substrate is of an insulating material; the functionally pinning layer is of a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is of a conductive material for reducing the roughness of the barrier layer; the barrier layer is of an oxide; the conductive layer is of a conductive inorganic or organic material; the functionally free layer is of a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the cap layer is a protective layer for preventing the oxidation of the structure.

(348) Circuit Connection:

(349) 1. Four collinear point electrodes are obtained on the surface of the cap layer by such methods as UV exposure, argon ion etching, and post-deposition of metals: the resistance in a high resistance state is denoted by a logic output 1 (the polarization intensity of the functionally pinning layer is leftward, and the polarization intensity of the functionally free layer is leftward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functionally pinning layer is leftward, and the polarization intensity of the functionally free layer is rightward; the polarization intensity of the functionally pinning layer is rightward, and the polarization intensity of the functionally free layer is leftward; the polarization intensity of the functionally pinning layer is rightward, and the polarization intensity of the functionally free layer is rightward).

(350) 2. Two electrodes are respectively prepared on the left and right sides of each of the functionally pinning layer and the functionally free layer by methods of UV exposure, argon ion etching, and post-deposition of metals and insulating materials, and three identical in-plane input electrical field intensities E.sub.A, E.sub.B and E.sub.C are applied to the functionally pinning layer and the functionally free layer, wherein both E.sub.A and E.sub.B are smaller than the coercive field intensity of the functionally free layer, E.sub.A+E.sub.B is greater than the coercive field intensity of the functionally free layer, E.sub.A+E.sub.B is smaller than the coercive field intensity of the functionally pinning layer, and E.sub.A+E.sub.B+E.sub.C is greater than the coercive field intensity of the functionally pinning layer. E.sub.A, E.sub.B and E.sub.C>0 is denoted by a logic input 1, and E.sub.A, E.sub.B and E.sub.C<0 is denoted by a logic input 0. Wherein, E.sub.C denotes a control input.

(351) NOR Logic (See FIG. 19B1 for the Truth Table)

(352) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward; disconnect input C and input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and set the initial output logic state D=0;

(353) 2. Rules for logical operation:

(354) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(355) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0;

(356) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0; and

(357) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0.

(358) NOR Logic (See FIG. 19B2 for the Truth Table)

(359) 1. Input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward; disconnect input C and input logic states A=0, B=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and set the initial output logic state D=0;

(360) 2. Rules for logical operation:

(361) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(362) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=0;

(363) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=0; and

(364) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=0.

(365) NOR Logic (See FIG. 19B3 for the Truth Table)

(366) 1. Input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and set the initial output logic state D=0;

(367) 2. Rules for logical operation:

(368) 1) input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(369) 2) input logic states A=0, B=1, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0;

(370) 3) input logic states A=1, B=0, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0; and

(371) 4) input logic states A=1, B=1, C=0, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0.

(372) NAND Logic (See FIG. 19B4 for the Truth Table)

(373) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is downward and the polarization intensity of the functionally free layer is downward, and set the initial output logic state D=1;

(374) 2. Rules for logical operation:

(375) 1) input logic states A=0, B=0, C=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(376) 2) input logic states A=0, B=1, C=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(377) 3) input logic states A=1, B=0, C=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1; and

(378) 4) input logic states A=1, B=1, C=1, so that the polarization intensity of the functionally pinning layer is rightward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0.

(379) NAND Logic (See FIG. 19B5 for the Truth Table)

(380) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and set the initial output logic state D=1;

(381) 2. Rules for logical operation:

(382) 1) input logic states A=0, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(383) 2) input logic states A=0, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(384) 3) input logic states A=1, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1; and

(385) 4) input logic states A=1, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0.

(386) NOR Logic (See FIG. 19B6 for the Truth Table)

(387) 1. Input logic states A=0, B=0, C=0, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward; disconnect input C and input logic states A=1, B=1, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and set the initial output logic state D=0;

(388) 2. Rules for logical operation:

(389) 1) input logic states A=0, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is leftward, and output a logic state D=1;

(390) 2) input logic states A=0, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0;

(391) 3) input logic states A=1, B=0, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0; and

(392) 4) input logic states A=1, B=1, C OFF, so that the polarization intensity of the functionally pinning layer is leftward and the polarization intensity of the functionally free layer is rightward, and output a logic state D=0.

Example 23

(393) FIG. 20A is a schematic view showing a logic device based on Structure d in Scheme 4, and FIG. 20B is the corresponding truth table. Structure: a substrate/a functional layer/a buffer layer/a barrier layer/a conductive layer/a cap layer.

(394) Wherein, the substrate is of an insulating material; the functional layer is of a ferroelectric or multi-ferric material, which can alter and regulate the intensity and the direction of polarization under the action of an electrical field; the buffer layer is of a conductive material for reducing the roughness of the barrier layer; the barrier layer is of an oxide; the conductive layer is of a conductive inorganic or organic material; the cap layer is a protective layer for preventing the oxidation of the magnetic layer.

(395) Circuit Connection:

(396) 1. Four point-contact electrodes are fabricated on the cap layer by a collinearly method: the resistance in a high resistance state is denoted by a logic output I (the polarization intensity of the functional layer is leftward), and the resistance in a low resistance state is denoted by a logic output 0 (the polarization intensity of the functional layer is rightward).

(397) 2. Two electrodes are respectively prepared on the left and right sides of the functional layer by such methods as UV exposure, argon ion etching, and post-deposition of metals and insulating materials, and two identical in-plane input electrical field intensities E.sub.A and E.sub.B are applied to the functional layer: both E.sub.A and En are less than the coercive field intensity of the functional layer, and E.sub.A+E.sub.B is greater than the coercive field intensity of the functional layer. E.sub.A, E.sub.B>0 is denoted by a logic input 1, and E.sub.A, E.sub.B<0 is denoted by a logic input 0.

(398) NAND Logic (See FIG. 20B1 for the Truth Table)

(399) 1. Input logic states A=0, B=0, so that the polarization intensity of the functional layer is leftward, and set the initial output logic state C=1;

(400) 2. Rules for logical operation:

(401) 1) input logic states A=0, B=0, so that the polarization intensity of the functional layer is leftward, and output a logic state C=1;

(402) 2) input logic states A=0, B=1, so that the polarization intensity of the functional layer is leftward, and output a logic state C=1;

(403) 3) input logic states A=1, B=0, so that the polarization intensity of the functional layer is leftward, and output a logic state C=1; and

(404) 4) input logic states A=1, B=1, so that the polarization intensity of the functional layer is rightward, and output a logic state C=0.

(405) NOR Logic (See FIG. 20B2 for the Truth Table)

(406) 1. Input logic states A=1, B=1, so that the polarization intensity of the functional layer is rightward, and set the initial output logic state C=0;

(407) 2. Rules for logical operation:

(408) 1) input logic states A=0, B=0, so that the polarization intensity of the functional layer is leftward, and output a logic state C=1;

(409) 2) input logic states A=0, B=1, so that the polarization intensity of the functional layer is rightward, and output a logic state C=0;

(410) 3) input logic states A=1, B=0, so that the polarization intensity of the functional layer is rightward, and output a logic state C=0; and

(411) 4) input logic states A=1, B=1, so that the polarization intensity of the functional layer is rightward, and output a logic state C=0.

INDUSTRIAL APPLICABILITY

(412) In the present invention, an electrical field is applied between the bottom layer and the buffer layer (the upper and lower electrodes) (since the changes in the intensity and the direction of electrical polarization of the substrate (a ferroelectric or multi-ferric material) influence and change the in-plane conductivity between the neighboring conductive layers, different resistance states corresponding to different electrical fields can be obtained), thereby achieving a reversible ER effect.

(413) Of course, the present invention may have a variety of other embodiments. Those skilled in the art can make all kinds of corresponding changes and modifications according to the present invention without departing from the spirit and essence of the present invention. It is intended that all these changes and modifications be covered by the appended claims of the present invention.