Capacitive MEMS sensor and method

Abstract

A system and method for forming a sensor device includes defining an in-plane electrode in a device layer of a silicon on insulator (SOI) wafer, forming an out-of-plane electrode in a silicon cap layer located above an upper surface of the device layer, depositing a silicide-forming metal on a top surface of the silicon cap layer, and annealing the deposited silicide-forming metal to form a silicide portion in the silicon cap layer.

Claims

1. A method of forming a sensor device, comprising: defining an in-plane electrode in a device layer of a silicon on insulator (SOI) wafer; forming an out-of-plane electrode in a silicon cap layer located above an upper surface of the device layer by forming at least one non-silicon spacer in the cap layer; depositing a silicide-forming metal on a top surface of the silicon cap layer and on a top surface of the at least one non-silicon spacer; and annealing the deposited silicide-forming metal to form a silicide portion in the silicon cap layer.

2. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises rapid thermal annealing the deposited silicide-forming metal.

3. The method of claim 1, further comprising: etching a residual silicide-forming metal from the top surface of the silicon cap layer.

4. The method of claim 1, wherein depositing the silicide-forming metal comprises: depositing a silicide-forming metal selected from a group consisting of nickel, tantalum, titanium, tungsten, and platinum.

5. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises: annealing the deposited silicide-forming metal for a duration between 1 second and 10 minutes.

6. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises: annealing the deposited silicide-forming metal at a temperature in a range of 250 C. to 800 C.

7. The method of claim 6, wherein the annealing temperature is less than 450 C.

8. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises: annealing the deposited silicide-forming metal such that the entire cap layer is converted to silicide.

9. The method of claim 1, further comprising: removing a portion of the silicide-forming metal deposited on the top surface of the at least one non-silicon spacer in the cap layer after annealing the silicide-forming metal.

10. The method of claim 1, further comprising: supporting the cap layer with the device layer at a location above the defined in-plane electrode prior to forming the out-of-plane electrode.

11. The method of claim 10, further comprising: forming a device layer connector portion within the device layer in electrical communication with the defined in-plane electrode; and forming a cap layer connector portion within the supported cap layer, the cap layer connector portion in electrical communication with the device layer connector portion.

12. The method of claim 1, further comprising: placing the formed silicide portion in the silicon cap layer in electrical communication with a piezo-resistor.

13. A sensor device, comprising: an in-plane electrode; a cap layer spaced apart from an upper surface of the in-plane electrode; an out-of-plane electrode defined in the cap layer by at least one first non-silicon spacer; a connector portion defined in the cap layer and in electrical communication with the in-plane electrode, the connector portion having a silicide upper surface; and a silicide portion formed in the cap layer.

14. The sensor device of claim 13, wherein the silicide portion and the silicide upper surface are formed in the cap layer by annealing a silicide-forming metal deposited on a top surface of the cap layer.

15. The sensor device of claim 14, wherein the silicide-forming metal is one or more of nickel, tantalum, titanium, tungsten, and platinum.

16. The sensor device of claim 13, wherein the sensor device is a pressure sensor device and the silicide portion is formed throughout an entire depth of the cap layer.

17. The sensor device of claim 13, further comprising: at least one piezo-resistor, wherein the silicide portion is formed in a top portion of the cap layer in electrical communication with the at least one piezo-resistor so as to provide an electrical connection to the at least one piezo-resistor.

18. The sensor device of claim 13, further comprising: a second non-silicon spacer extending downwardly from an upper surface of the cap layer, the second non-silicon spacer electrically isolating the silicide portion from the silicide upper surface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a side cross-sectional view of a known sensor device having a metal layer deposited and patterned on a top surface of the sensor;

(2) FIG. 2 depicts a sensor device which includes silicide in a top portion of a cap layer;

(3) FIG. 3 depicts a side cross-sectional view of a wafer with a device layer etched to define an in-plane-electrode;

(4) FIG. 4 depicts a top plan view of the wafer of FIG. 3;

(5) FIG. 5 depicts the wafer of FIG. 3 with the trenches filled with an oxide material and an oxide layer formed above the device layer;

(6) FIG. 6 depicts a top plan view of the wafer of FIG. 5;

(7) FIG. 7 depicts the wafer of FIG. 5 with an opening etched in the oxide layer above a contact portion of the device layer;

(8) FIG. 8 depicts a top plan view of the wafer of FIG. 7;

(9) FIG. 9 depicts the wafer of FIG. 7 with a first cap layer portion formed above the oxide layer and trenches formed in the oxide layer;

(10) FIG. 10 depicts a top plan view of the wafer of FIG. 9;

(11) FIG. 11 depicts the wafer of FIG. 9 with the trenches filled with an insulating material, the insulating material also forming a layer above the first cap layer portion, and an etch stop layer formed above the insulating layer;

(12) FIG. 12 depicts a top plan view of the wafer of FIG. 11;

(13) FIG. 13 depicts the wafer of FIG. 11 after the insulating layer and etch stop layer have been etched to define gaskets for an out-of-plane electrode and a device layer contact;

(14) FIG. 14 depicts a top plan view of the wafer of FIG. 13;

(15) FIG. 15 depicts the wafer of FIG. 13 after a second cap layer portion has been deposited above the first cap layer portion and the gaskets, and the second cap layer portion has been planarized;

(16) FIG. 16 depicts a top plan view of the wafer of FIG. 15;

(17) FIG. 17 depicts the wafer of FIG. 15 after vapor etch vent holes have been etched through the first cap layer portion and the second cap layer portion, and a portion of the oxide layer, the oxide material in the device layer, and a portion of a buried oxide layer have been etched, thereby electrically isolating an in-plane electrode and releasing the first cap layer portion above the in-plane electrode;

(18) FIG. 18 depicts a top plan view of the wafer of FIG. 17;

(19) FIG. 19 depicts the wafer of FIG. 17 after the vapor etch vent holes have been sealed by a third cap layer portion;

(20) FIG. 20 depicts a top plan view of the wafer of FIG. 19;

(21) FIG. 21 depicts the wafer of FIG. 19 with trenches formed through the third cap layer portion and the second cap layer portion to upper surfaces of the gaskets;

(22) FIG. 22 depicts a top plan view of the wafer of FIG. 21;

(23) FIG. 23 depicts the wafer of FIG. 21 with an insulating material deposited within the trenches and a silicide forming material deposited along the upper surface of the third cap layer portion;

(24) FIG. 24 depicts a top plan view of the wafer of FIG. 23; and

(25) FIG. 25 depicts a side cross-sectional view of a wafer including a silicide layer formed in an upper portion of the cap layer.

DESCRIPTION

(26) For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiments illustrated in the drawings and described in the following written specification. It is understood that no limitation to the scope of the disclosure is thereby intended. It is further understood that the disclosure includes any alterations and modifications to the illustrated embodiments and includes further applications of the principles of the disclosure as would normally occur to one skilled in the art to which this disclosure pertains.

(27) In many of these embodiments, a MEMS sensor may be used to sense a physical condition such as acceleration, pressure, or temperature, and to provide an electrical signal representative of the sensed physical condition. The embodiments may be implemented in or associated with a variety of applications such as automotive, home appliances, laptops, handheld or portable computers, mobile telephones, smart phones, wireless devices, tablets, personal data assistants (PDAs), MP3 players, camera, GPS receivers or navigation systems, electronic reading displays, projectors, cockpit controls, game consoles, earpieces, headsets, hearing aids, wearable display devices, security systems, and etc.

(28) FIG. 2 depicts a pressure sensor 100. The pressure sensor 100 includes a handle layer 102, a buried oxide layer 104, and a device layer 106. An oxide layer 108 separates the device layer 106 from a cap layer 110. A silicide layer 112 is located above the cap layer 110.

(29) Within the device layer 106, an in-plane electrode 114 is defined by two etch portions 116 and 118. The in-plane electrode 114 is isolated from the cap layer 110 by an etched portion 120 of the oxide layer 108. The etched portions 116, 118, and 120 are etched through vent holes 122 which are closed by the cap layer 110.

(30) An out-of plane electrode 124 is located above the in-plane electrode 114 and electrically isolated from the in-plane electrode 114 by the etched portion 120. The out-of-plane electrode 124 is isolated from the rest of the cap layer 110 by two non-silicon spacers 126 and 128. The spacers 126 and 128 include a lower nitride portion 130 which extends upwardly from the etched portion 120, and an upper oxide portion 132 which extends from the nitride portion 130 to the upper surface of the cap layer 110. The detection signal is the capacity and or capacitance change between the electrodes 114 and 124. The electrode 124 is deflected as a function of the outside pressure.

(31) Spacers 134 and 136, which are formed like the spacers 126 and 128, electrically isolate a connector 138 in the cap layer 110 from the rest of the cap layer 110. The connector 138 is in electrical communication with a connector 140 in the device layer 106. The connector 140 is in electrical communication with the in-plane electrode 114 and isolated from the remainder of the device layer 106 by isolation posts 142 and 144. The isolation posts 142 and 144 extend from the buried oxide layer 104 to the oxide layer 108.

(32) The spacers 126 and 128 also define and electrically separate a silicide portion 146 from the rest of the silicide layer 112 while the spacers 134 and 136 electrically separate a silicide portion 148 from the rest of the silicide layer 112

(33) Silicides are common materials in semiconductor processing. Silicide has a very low electric resistance that is comparable to the resistance of metals and has mechanical properties that are comparable to those of silicon. Moreover, silicides are highly conductive. Thus, silicide materials are well-suited for mechanically sensitive pressure sensor membranes.

(34) The silicide portions 146 and 148 in the pressure sensor 100 of FIG. 2 enable electrical communication with the connectors 138, 140 and the in-plane electrode 114 from a top surface of the pressure sensor 100. As shown by comparing FIG. 1 and FIG. 2, the silicide layer 112 in the pressure sensor 100 replaces the passive layer 22 and the trace 56 of the prior art pressure sensor 10. Consequently, the process steps for forming the passive layer 22 and the trace 56 are eliminated. Alternatively, the passive layer 22 can be added on top of the silicide.

(35) A process for forming a sensor such as the pressure sensor 100 is discussed with reference to FIGS. 3-25. Referring initially to FIGS. 3 and 4, an SOI wafer 200 including a handle layer 202, a buried oxide layer 204, and a device layer 206 is initially etched to define an in-plane electrode 208 and a lower contact portion 210 for the in-plane-electrode 208. A connector 212 is etched between the in-plane electrode 208 and the lower contact portion 210. The in-plane electrode 208 is defined by a trench portion 214, while the lower contact portion 210 is defined by a trench portion 216 and the connector 212 is defined by a trench portion 218. If desired, the structural or handle layer 202 may be a pressure chemical vapor deposition (LPCVD) or epi-polysilicon layer.

(36) The trench portions 214, 216, and 218 are then filled with a trench oxide portion 220 as shown in FIGS. 5 and 6 using a conformal oxide deposition. Oxide deposition further results in an oxide layer 222 on the upper surface of the device layer 206. The thickness of the oxide layer 222 sets the gap between two electrodes as discussed more fully below. The oxide layer 222 may be planarized by any desired technique such as chemical mechanical polishing (CMP).

(37) Referring to FIGS. 7 and 8, a contact opening 224 is then etched through the oxide layer 222 to expose the upper surface of the lower contact portion 210. An epi-poly deposition fills the contact opening 224 with a lower middle contact portion 226 of epi-poly while depositing a lower cap layer portion 228 above the oxide layer 222 as shown in FIGS. 9 and 10. The lower middle contact portion 226 thus extends from the upper surface of the lower contact portion 210 to the upper surface of the lower cap layer portion 228. In an alternative embodiment, the lower cap layer portion 228 may be a single crystal silicon formed using a fusion bonding process followed by grinding/polishing or SmartCut technology to remove the bulk of the bonded wafer. In this alternative embodiment, electrical contacts must be formed after fusion. In a further embodiment, a polished polysilicon device layer may be used.

(38) FIGS. 9 and 10 further show trenches 230 and 232 which may be etched after CMP of the lower cap layer portion 228. The trench 230 extends from the upper surface of the lower cap layer portion 228 to the upper surface of the oxide layer 222 to define the lower middle contact portion 226. The trench 232 includes a trench portion 234 that defines a lower out-of-plane electrode portion 236, a trench portion 238 that defines a connector 240, and a trench portion 242 that defines a lower contact portion 244 for the lower out-of-plane electrode portion 236.

(39) A low stress nitride is then used to fill the trenches 230 and 232 with trench nitride portions 250 and 252 while a low stress nitride layer 254 is deposited on the upper surface of the lower cap layer portion 228 as shown in FIGS. 11 and 12. A thin oxide layer 256 is provided on the upper surface of the low stress nitride layer 254. The thin oxide layer 256 and the nitride layer 254 are then patterned and etched resulting in the configuration of FIGS. 13 and 14. In FIGS. 13 and 14, a remainder 258 of the oxide layer 256 and a remainder 260 of the nitride layer 254 form a gasket 262 for an out-of plane electrode described more fully below. A remainder 264 of the oxide layer 256 and a remainder 266 of the nitride layer 254 form a gasket 268 for a contact the in-plane-electrode 208. The lateral extent of the gaskets 262 and 268 when viewed in cross-section may be selected to provide the desired isolation characteristics for the components defined thereby.

(40) A thin epi-poly deposition layer 270 is then formed on the upper surface of the lower cap portion 228 and the upper surface of the gaskets 262 and 268 to form a middle cap layer portion 272 (see FIGS. 15 and 16). The epi-poly deposition layer may be deposited in the manner described by Candler et al., Long-Term and Accelerated Life Testing of a Novel Single-Wafer Vacuum Encapsulation for MEMS Resonators, Journal of Microelectricalmechanical Systems, vol. 15, no. 6, December 2006. The middle cap layer portion 272 may be planarized if desired.

(41) Referring to FIGS. 17 and 18, after vent holes 274 are formed, an HF vapor etch release is performed which releases the middle cap layer portion 272 from the in-plane-electrode 208. The etched portion of the oxide layer 222 between the upper surface of the in-plane-electrode 208 and the lower surface of the middle cap layer portion 272 thus sets the gap between the in-plane-electrode 208 and the lower surface of what will be the out-of-plane electrode. A clean high temperature seal is then performed in an epi reactor to seal the vent holes 274. Alternatively, the vent holes 274 may be sealed using oxide, nitride, silicon migration, etc. The resulting configuration is shown in FIGS. 19 and 20 wherein a layer portion 276 is formed above the middle cap layer portion 272.

(42) A trench 280 and a trench 282 are then etched as depicted in FIGS. 21 and 22. The trench 280 extends from the upper surface of the layer portion 276 to the upper surface of the gasket 262 which acts as an etch stop. The trench 282 extends from the upper surface of the layer portion 276 to the upper surface of the gasket 268 which acts as an etch stop. A passivation material, which may be oxide, nitride, etc., is then deposited in the trenches 280 and 282 to form passivation portions 286 and 288 and patterned and a silicide forming metal 290 is deposited on the upper surface of the layer portion 276 (see FIGS. 23 and 24). The silicide-forming material 290 may be titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), or platinum (Pt).

(43) After the silicide-forming material 290 is deposited, the assembly 200 is subjected to an annealing process. In some embodiments, the duration of the annealing process can be in a range of one (1) second to one (1) minute. The temperature of the annealing process in these embodiments can be in a range of 250 C. to 800 C., depending on the type of silicide-forming metal 190 used in the process. In some embodiments, the annealing temperature is less than 450 C. It should be understood that the annealing temperature of less than 450 C. in these embodiments is not limiting because only a short anneal time is required for silicide formation.

(44) In the annealing process, silicide forming material which is directly above a silicon material reacts with the silicon material to form silicide 292 as shown in FIG. 25. Silicide forming material which is above non-silicon material, such as the passivation portions 286 and 288 does not react. A metal-etch process is used to remove the residual metal that is not converted into silicide.

(45) In some embodiments, silicide is formed only in a top portion of a cap layer. An example of such an embodiment is a piezo-resistive pressure sensor that has the silicide formed on the top portion of the cap layer to provide a connection to one or more piezo-resistors. In other embodiments, the silicide is formed throughout the entire depth of the cap layer.

(46) This selective silicide forming process can be done using a patterned passivation layer on top of which the silicide forming metal is deposited. After anneal and silicide formation, the excess unreacted metal is removed using a metal etch. Another option is to pattern the silicide forming metal prior to the annealing process.

(47) The process described can further be used in order to realize conductive structures with low resistance on and closely besides the pressure sensor membrane without impacting the mechanical properties.

(48) While the disclosure has been illustrated and described in detail in the drawings and foregoing description, the same should be considered as illustrative and not restrictive in character. It is understood that only the preferred embodiments have been presented and that all changes, modifications and further applications that come within the spirit of the disclosure are desired to be protected.