CIRCUIT AND METHOD FOR INTER-SYMBOL AND INTRA-SYMBOL VOLTAGE MODULATION

Abstract

Circuit and method for inter-symbol and intra-symbol voltage method are disclosed. Herein, a transceiver circuit is configured to determine a voltage target(s) for generating a modulated voltage(s) to amplify a radio frequency (RF) signal modulated in multiple symbols. Specifically, the transceiver circuit will generate multiple voltage targets for any of the symbols to thereby enable intra-symbol voltage modulation when the respective symbol is modulated to carry a selected type of information or generate a single voltage target for any of the symbols to thereby enable inter-symbol voltage modulation when the respective symbol lacks the selected type of information. By dynamically performing inter-symbol and intra-symbol voltage modulation based on the type of information carried in a symbol(s), the modulated voltage can be timely adapted to closely track a time-variant power envelope of the RF signal to thereby avoid potential distortion and protect critical information in the RF signal.

Claims

1. A transceiver circuit comprising: a digital baseband circuit configured to generate an input vector comprising a selected type of information modulated in one or more of a plurality of symbols; and a target voltage circuit configured to: determine a plurality of voltage modulation intervals corresponding to the plurality of symbols, respectively; divide a respective one of the plurality of voltage modulation intervals into a plurality of voltage modulation subintervals each comprising a respective one of a plurality of voltage targets when a corresponding one of the plurality of symbols comprises the selected type of information; and generate a respective one of a plurality of target voltage indications comprising the plurality of voltage targets.

2. The transceiver circuit of claim 1, wherein the selected type of information comprises one or more of: physical downlink control channel (PDCCH) information, physical uplink control channel (PUCCH) information, physical downlink shared channel (PDSCH) information, and physical uplink shared channel (PUSCH) information.

3. The transceiver circuit of claim 1, wherein each of the plurality of symbols is an orthogonal frequency division multiplexing (OFDM) symbol.

4. The transceiver circuit of claim 1, wherein the target voltage circuit is further configured to equally divide the respective one of the plurality of voltage modulation intervals into the plurality of voltage modulation subintervals.

5. The transceiver circuit of claim 1, wherein the target voltage circuit is further configured to unequally divide the respective one of the plurality of voltage modulation intervals into the plurality of voltage modulation subintervals.

6. The transceiver circuit of claim 1, wherein the target voltage circuit is further configured to generate the respective one of the plurality of target voltage indications comprising a single voltage target when the corresponding one of the plurality of symbols does not contain the selected type of information.

7. The transceiver circuit of claim 1, further comprising a signal processing circuit configured to generate a radio frequency (RF) signal from the input vector.

8. A transmission circuit comprising: a transceiver circuit comprising: a digital baseband circuit configured to generate an input vector comprising a selected type of information modulated in one or more of a plurality of symbols; and a target voltage circuit configured to: determine a plurality of voltage modulation intervals corresponding to the plurality of symbols, respectively; divide a respective one of the plurality of voltage modulation intervals into a plurality of voltage modulation subintervals each comprising a respective one of a plurality of voltage targets when a corresponding one of the plurality of symbols comprises the selected type of information; and generate a respective one of a plurality of target voltage indications comprising the plurality of voltage targets; and a power management integrated circuit (PMIC) comprising a voltage generation circuit configured to: receive the plurality of target voltage indications from the transceiver circuit; and generate a plurality of modulated voltages in the plurality of voltage modulation subintervals based on the plurality of voltage targets, respectively.

9. The transmission circuit of claim 8, wherein the PMIC further comprises: an inter-chip interface coupled to the transceiver circuit to receive the plurality of target voltage indications; and a memory circuit configured to store the plurality of received target voltage indications.

10. The transmission circuit of claim 8, wherein the PMIC is further configured to receive the respective one of the plurality of target voltage indications corresponding to the respective one of the plurality of voltage modulation intervals during an immediately preceding one of the plurality of voltage modulation intervals.

11. The transmission circuit of claim 8, wherein the voltage generation circuit is further configured to generate each of the plurality of modulated voltages based on the respective one of the plurality of voltage targets no later than a respective start of the respective one of the plurality of voltage modulation subintervals.

12. The transmission circuit of claim 11, wherein the voltage generation circuit is further configured to: generate a respective one of the plurality of modulated voltages prior to the respective start of the respective one of the plurality of voltage modulation subintervals in response to the respective one of the plurality of voltage targets indicating that the respective one of the plurality of modulated voltages will increase during the respective one of the plurality of voltage modulation subintervals; and generate the respective one of the plurality of modulated voltages at the respective start of the respective one of the plurality of voltage modulation subintervals in response to the respective one of the plurality of voltage targets indicating that the respective one of the plurality of modulated voltages will decrease during the respective one of the plurality of voltage modulation subintervals.

13. The transmission circuit of claim 8, wherein the target voltage circuit is further configured to generate a single voltage target for the respective one of the plurality of voltage modulation intervals when the respective one of the plurality of symbols does not contain the selected type of information.

14. The transmission circuit of claim 13, wherein the voltage generation circuit is further configured to generate a single modulated voltage during the respective one of the plurality of voltage modulation intervals based on the single voltage target.

15. A method for enabling inter-symbol and intra-symbol voltage modulation comprising: generating an input vector comprising a selected type of information modulated in one or more of a plurality of symbols; determining a plurality of voltage modulation intervals corresponding to the plurality of symbols, respectively; dividing a respective one of the plurality of voltage modulation intervals into a plurality of voltage modulation subintervals each comprising a respective one of a plurality of voltage targets when a corresponding one of the plurality of symbols comprises the selected type of information; generating a respective one of a plurality of target voltage indications comprising the plurality of voltage targets; and generating a plurality of modulated voltages in the plurality of voltage modulation subintervals based on the plurality of voltage targets, respectively.

16. The method of claim 15, further comprising receiving the respective one of the plurality of target voltage indications corresponding to the respective one of the plurality of voltage modulation intervals during an immediately preceding one of the plurality of voltage modulation intervals.

17. The method of claim 15, further comprising generating each of the plurality of modulated voltages based on the respective one of the plurality of voltage targets no later than a respective start of the respective one of the plurality of voltage modulation subintervals.

18. The method of claim 17, further comprising: generating a respective one of the plurality of modulated voltages prior to the respective start of the respective one of the plurality of voltage modulation subintervals in response to the respective one of the plurality of voltage targets indicating that the respective one of the plurality of modulated voltages will increase during the respective one of the plurality of voltage modulation subintervals; and generating the respective one of the plurality of modulated voltages at the respective start of the respective one of the plurality of voltage modulation subintervals in response to the respective one of the plurality of voltage targets indicating that the respective one of the plurality of modulated voltages will decrease during the respective one of the plurality of voltage modulation subintervals.

19. The method of claim 15, further comprising generating a single voltage target for the respective one of the plurality of voltage modulation intervals when the respective one of the plurality of symbols does not contain the selected type of information.

20. The method of claim 19, further comprising generating a single modulated voltage during the respective one of the plurality of voltage modulation intervals based on the single voltage target.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] FIG. 1 illustrates an exemplary time slot(s) and a mini time slot(s) as widely supported in a fifth generation (5G) or a 5G new-radio (5G-NR) system;

[0015] FIG. 2 is a schematic diagram of an exemplary transmission circuit wherein a power management integrated circuit (PMIC) and a transceiver circuit are configured according to embodiments of the present disclosure to enable inter-symbol and intra-symbol voltage modulation;

[0016] FIGS. 3A and 3B are block diagrams providing exemplary illustrations of a target voltage indication generated by the transceiver circuit in FIG. 2 to cause the PMIC to perform the intra-symbol voltage modulation;

[0017] FIG. 4 is a block diagram providing an exemplary illustration as to how the PMIC in FIG. 2 can perform the intra-symbol voltage modulation;

[0018] FIG. 5 is a schematic diagram of an exemplary voltage modulation circuit, which can be provided in the PMIC in FIG. 2 to perform inter-symbol and intra-symbol voltage modulation during the voltage modulation interval(s);

[0019] FIG. 6 is a schematic diagram illustrating the transceiver circuit in FIG. 2 configured to enable inter-symbol and intra-symbol voltage modulation; and

[0020] FIG. 7 is a flowchart of an exemplary process for enabling inter-symbol and intra-symbol voltage modulation according to embodiments of the present disclosure.

DETAILED DESCRIPTION

[0021] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0022] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0023] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0024] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0027] Embodiments of the disclosure relate to circuit and method for inter-symbol and intra-symbol voltage modulation. Herein, a transceiver circuit is configured to determine a voltage target(s) and provide the voltage target(s) to a power management integrated circuit (PMIC) for generating a modulated voltage(s) to amplify a radio frequency (RF) signal modulated in multiple symbols. Specifically, the transceiver circuit will generate multiple voltage targets for any of the symbols to thereby enable intra-symbol voltage modulation when the respective symbol is modulated to carry a selected type of information (e.g., control information). In contrast, the transceiver circuit will generate a single voltage target for any of the symbols to thereby enable inter-symbol voltage modulation when the respective symbol is not modulated to carry the selected type of information. By dynamically performing inter-symbol and intra-symbol voltage modulation based on the type of information carried in a symbol(s), the modulated voltage can be timely adapted to closely track a time-variant power envelope of the RF signal to thereby avoid potential distortion (e.g., amplitude clipping) and protect critical information in the RF signal.

[0028] Before discussing inter-symbol and intra-symbol voltage modulation of the present disclosure, starting at FIG. 2, an overview of orthogonal frequency division multiplexing (OFDM) symbols, which can be used to define durations of voltage modulation intervals, is first provided with reference to FIG. 1.

[0029] FIG. 1 illustrates an exemplary time slot(s) 10 and a pair of mini time slots 12(1)-12(2) as widely supported in a fifth generation (5G) and 5G new-generation (5G-NR) system. The time slot(s) 10, which can represent any one or more of multiple continuous time slots, includes multiple symbols 14(1)-14(N), such as OFDM symbols. The mini time slots 12(1)-12(2) can each include at least two of the symbols 14(1)-14(N). In the example shown in FIG. 1, each of the mini time slots 12(1)-12(2) includes four of the symbols 14(1)-14(N). As previously shown in Table 1, each of the symbols 14(1)-14(N) has a symbol duration that depends on the subcarrier spacing (SCS). Once the SCS is chosen, the duration and the CP of each of the symbols 14(1)-14(N) are set accordingly.

[0030] The symbols 14(1)-14(N) in the time slot(s) 10 can be modulated based on any type of modulation and coding scheme (MCS) to carry various types of information. For example, some of the symbols 14(1)-14(N) can be modulated to carry downlink/uplink control information, some of the symbols 14(1)-14(N) can be modulated to carry downlink/uplink data payload, and yet some of the symbols 14(1)-14(N) can be empty (e.g., not bearing any information). Among the symbols 14(1)-14(N), those symbols that are modulated to carry a selected type of information are of special importance in the context of the present disclosure.

[0031] Herein, the selected type of information may include information related to physical downlink control channel (PDCCH), physical uplink control channel (PUCCH), physical downlink shared channel (PDSCH), and/or physical uplink shared channel (PUSCH). In a non-limiting example, the selected type of information can be a sounding reference signal (SRS), a demodulation reference signal (DMRS), and so on. As described in detail below, whether the selected type of information is present or absent in any of the symbols 14(1)-14(N) is a determining factor for intra-symbol or inter-symbol voltage modulation.

[0032] FIG. 2 is a schematic diagram of an exemplary transmission circuit 16 wherein a PMIC 18 and a transceiver circuit 20 are configured according to embodiments of the present disclosure to enable inter-symbol and intra-symbol voltage modulation. The transmission circuit 16 also includes a power amplifier circuit 22. The power amplifier circuit 22 is configured to amplify an RF signal 24 based on a modulated voltage V.sub.CC, which can be an envelope tracking (ET) modulated voltage or an average power tracking (APT) modulated voltage. The PMIC 18 is configured to generate the modulated voltage V.sub.CC and the transceiver circuit 20 is configured to generate the RF signal 24.

[0033] The transceiver circuit 20 is configured to modulate the RF signal 24 onto the symbols 14(1)-14(N) in FIG. 1. Herein, three consecutive symbols 14(X−1), 14(X), 14(X+1) among the symbols 14(1)-14(N) (X>1, N≥X+1) are illustrated as an example. As described above, some of the symbols 14(X−1), 14(X), 14(X+1) may be modulated to carry the selected type of information, while some other ones of the symbols 14(X−1), 14(X), 14(X+1) may not. As an example, it is assumed that the symbol 14(X) is modulated to carry the selected type of information, and symbols 14(X−1) and 14(X+1) do not contain the selected type of information. In this regard, as further described below, the transmission circuit 16 will perform intra-symbol voltage modulation during the symbol 14(X) and inter-symbol voltage modulation during the symbols 14(X−1) and 14(X+1).

[0034] Herein, intra-symbol voltage modulation means that the PMIC 18 can change the modulated voltage V.sub.CC multiple times during the symbol 14(X). In contrast, inter-symbol voltage modulation means that the PMIC 18 does not change the modulated voltage V.sub.CC during any of the symbols 14(X−1) and 14(X+1). However, with inter-symbol voltage modulation, the PMIC 18 can still change the modulated voltage V.sub.CC between the symbols 14(X−1) and 14(X+1). In other words, the modulated voltage V.sub.CC in the symbol 14(X−1) can be identical to or different from the modulated voltage V.sub.CC in the symbol 14(X+1).

[0035] In an embodiment, the transceiver circuit 20 is configured to generate multiple target voltage indications V.sub.TGT(i) (i=X−1, X, X+1) in multiple voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1, respectively. Each of the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 correspond to a respective one of the symbols 14(X−1), 14(X), 14(X+1). In other words, there exists a one-to-one relationship between the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 and the symbols 14(X−1), 14(X), 14(X+1). Notably, the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 represent three consecutive voltage modulation intervals among any number of voltage modulation intervals, so chosen for the sole purpose of illustration. Understandably, the voltage modulation interval S.sub.X−1 is an immediately preceding voltage modulation interval of the voltage modulation interval S.sub.X, the voltage modulation interval S.sub.X is an immediately preceding voltage modulation interval of the voltage modulation interval S.sub.X+1, and so on.

[0036] According to an embodiment of the present disclosure, the PMIC 18 includes an inter-chip interface 26, a memory circuit 28, and a voltage generation circuit 30. In a non-limiting example, the inter-chip interface 26 can be a multi-wire interface, such as an RF front-end (RFFE) interface, that is coupled to the transceiver circuit 20. The transceiver circuit 20 is configured to provide a respective target voltage indication V.sub.TGT(i) (i=X−1, X, X+1, and so on) for each of the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1.

[0037] Specifically, to enable to PMIC 18 to perform inter-symbol voltage modulation, the transceiver circuit 20 is configured to determine and provide a single voltage target V.sub.TGT to the PMIC 18 in the target voltage indications V.sub.TGT(i) (i=X−1, X+1). Accordingly, the PMIC 18 will generate the modulated voltage V.sub.CC during the voltage modulation intervals S.sub.X−1, S.sub.X+1 based on the respective voltage target V.sub.TGT received in the target voltage indications V.sub.TGT(i) (i=X−1, X+1).

[0038] Notably, the transceiver circuit 20 is configured to generate the RF signal 24 with a time-variant power envelope P(t) that can increase or decrease multiple times during each of the symbols 14(X−1), 14(X), 14(X+1). In this regard, since the symbol 14(X) includes the selected type of information, it is desirable that the PMIC 18 can generate multiple modulated voltages V.sub.CC1-V.sub.CCN during the voltage modulation interval S.sub.X to better track (increase or decrease) the time-variant power envelope P(t) on an intra-symbol basis to help avoid potential distortion (e.g., amplitude clipping) to the RF signal 24 when the RF signal 24 is amplified by the power amplifier circuit 22.

[0039] FIGS. 3A and 3B are block diagrams providing exemplary illustrations of the target voltage indication V.sub.TGT(i) (i=X) generated by the transceiver circuit 20 in FIG. 2 to cause the PMIC 18 to perform the intra-symbol voltage modulation during the voltage modulation interval S.sub.X. Common elements between FIGS. 2 and 3A-3B are shown therein with common element numbers and will not be re-described herein.

[0040] In one embodiment, as illustrated in FIG. 3A, the transceiver circuit 20 can divide the voltage modulation intervals S.sub.X equally such that each of the modulation subintervals T.sub.1-T.sub.N will have an identical duration.

[0041] In another embodiment, as illustrated in FIG. 3B, the transceiver circuit 20 can divide the voltage modulation interval S.sub.X unequally such that each of the modulation subintervals T.sub.1-T.sub.N will have different durations. For example, the transceiver circuit 20 can make any of the modulation subintervals T.sub.1-T.sub.N longer if a variation of the modulated voltage V.sub.CC exceeds a preset threshold between adjacent ones of the modulation subintervals T.sub.1-T.sub.N, or make any of the modulation subintervals T.sub.1-T.sub.N shorter if the modulated voltage V.sub.CC remains unchanged or the variation of the modulated voltage V.sub.CC is below the preset threshold in between the adjacent ones of the modulation subintervals T.sub.1-T.sub.N.

[0042] With reference back to FIG. 2, the transceiver circuit 20 is also configured to set the voltage targets V.sub.TGT-1-V.sub.TGT-N for each of the modulation subintervals T.sub.1-T.sub.N based on the time-variant power envelope P(t) of the RF signal 24. In a non-limiting example, the transceiver circuit 20 can set a respective one of the voltage targets V.sub.TGT-1-V.sub.TGT-N for a respective one of the modulation subintervals T.sub.1-T.sub.N based on a maximum of the time-variant power envelope P(t) during the respective one of the modulation subintervals T.sub.1-T.sub.N.

[0043] The transceiver circuit 20 is configured to write the voltage targets V.sub.TGT-1-V.sub.TGT-N, in association with the modulation subintervals T.sub.1-T.sub.N, into the memory circuit 28 via the inter-chip interface 26. In one embodiment, the transceiver circuit 20 may write the voltage targets V.sub.TGT-1-V.sub.TGT-N associated with the voltage modulation interval S.sub.X prior to a start of the voltage modulation interval S.sub.X. Preferably, the transceiver circuit 20 will write the voltage targets V.sub.TGT-1-V.sub.TGT-N associated with the voltage modulation interval S.sub.X during an immediately preceding one of the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1. For example, the transceiver circuit 20 will write the voltage targets V.sub.TGT-1-V.sub.TGT-N associated with the voltage modulation interval S.sub.X during the voltage modulation interval S.sub.X−1.

[0044] Prior to the voltage modulation interval S.sub.X, the voltage generation circuit 30 retrieves the voltage targets V.sub.TGT-1-V.sub.TGT-N, in association with the modulation subintervals T.sub.1-T.sub.N, from the memory circuit 28. Accordingly, the voltage generation circuit 30 can generate the modulated voltages V.sub.CC-1-V.sub.CC-N during the modulation subintervals T.sub.1-T.sub.N based on the voltage targets V.sub.TGT-1-V.sub.TGT-N, respectively.

[0045] FIG. 4 is a block diagram providing an exemplary illustration as to how the PMIC 18 in FIG. 2 can perform intra-symbol voltage modulation during the voltage modulation interval S.sub.X. Common elements between FIGS. 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0046] The voltage generation circuit 30 is configured to determine multiple starts T.sub.START-1-T.sub.START-N of the modulation subintervals T.sub.1-T.sub.N, respectively. In a non-limiting example, the voltage generation circuit 30 can receive the start T.sub.START-1-T.sub.START-N of the modulation subintervals T.sub.1-T.sub.N from the transceiver circuit 20 together with or separately from the voltage targets V.sub.TGT-1-V.sub.TGT-N. Accordingly, the voltage generation circuit 30 can generate each of the modulated voltages V.sub.CC-1-V.sub.CC-N no later than a respective one of the determined start T.sub.START-1-T.sub.START-N of the voltage modulation subintervals T.sub.1-T.sub.N.

[0047] According to an embodiment of the present disclosure, the voltage generation circuit 30 is configured to determine whether each of the modulated voltages V.sub.CC-1-V.sub.CC-N is set to increase or decrease during a respective one of the modulation subintervals T.sub.1-T.sub.N. If any of the modulated voltages V.sub.CC-1-V.sub.CC-N is set to increase during the respective one of the modulation subintervals T.sub.1-T.sub.N, the voltage generation circuit 30 may start transitioning to the respective one the modulated voltages V.sub.CC-1-V.sub.CC-N prior to the respective start T.sub.START-1-T.sub.START-N of the respective one of the modulation subintervals T.sub.1-T.sub.N. For example, the voltage generation circuit 30 determines that the modulated voltages V.sub.CC-1 and V.sub.CC-3 are set to increase during the modulation subintervals T.sub.1 and T.sub.3, respectively. Accordingly, the voltage generation circuit 30 will start transitioning to the modulated voltages V.sub.CC-1 and V.sub.CC-3 with a timing advance Ta prior to the respective starts T.sub.START-1 and T.sub.START-3 of the modulation subintervals T.sub.1 and T.sub.3. By starting the transition with the timing advance Ta, the voltage generation circuit 30 can ensure that the modulated voltages V.sub.CC-1 and V.sub.CC-3 can be ramped up to desired levels in time to help avoid amplitude clipping in the RF signal 24.

[0048] In contrast, if any of the modulated voltages V.sub.CC-1-V.sub.CC-N is set to increase, or remain unchanged, during the respective one of the modulation subintervals T.sub.1-T.sub.N, the voltage generation circuit 30 may start transitioning to the respective one the modulated voltages V.sub.CC-1-V.sub.CC-N at the respective start T.sub.START-1-T.sub.START-N of the respective one of the modulation subintervals T.sub.1-T.sub.N. For example, the voltage generation circuit 30 determines that the modulated voltages V.sub.CC-2 and V.sub.CC-N are set to decrease during the modulation subintervals T.sub.2 and T.sub.N, respectively. Accordingly, the voltage generation circuit 30 will start transitioning to the modulated voltages V.sub.CC-2 and V.sub.CC-N right at the respective starts T.sub.START-2 and T.sub.START-N of the modulation subintervals T.sub.2 and T.sub.N.

[0049] FIG. 5 is a schematic diagram of the voltage generation circuit 30 configured according to an embodiment of the present disclosure. Common elements between FIGS. 2 and 5 are shown therein with common element numbers and will not be re-described herein.

[0050] Herein, the voltage generation circuit 30 includes a current modulation circuit 32, a voltage modulation circuit 34, and a control circuit 36. The current modulation circuit 32 includes a multi-level charge pump (MCP) 38 and a power inductor 40. During the voltage modulation interval S.sub.X, the MCP 38 is configured to generate multiple low-frequency voltages V.sub.DC-1-V.sub.DCN, each as a function of a battery voltage V.sub.BAT, during the modulation subintervals T.sub.1-T.sub.N, respectively. Accordingly, in the voltage modulation interval S.sub.X, the power inductor 40 is configured to induce multiple low frequency currents I.sub.DC1-I.sub.DCN based on the low-frequency voltages V.sub.DC-1-V.sub.DCN, respectively.

[0051] The voltage modulation circuit 34 includes a voltage amplifier 42, an offset capacitor C.sub.OFF, and a bypass switch S.sub.BYP. The voltage amplifier 42 is configured to generate multiple modulated initial voltages V.sub.AMP1-V.sub.AMPN based on the voltage targets V.sub.TGT-1-V.sub.TGT-N in the modulation subintervals T.sub.1-T.sub.N, respectively. The offset capacitor C.sub.OFF is modulated by the low frequency currents I.sub.DC1-I.sub.DCN to multiple offset voltages V.sub.OFF1-V.sub.OFFN in the modulation subintervals T.sub.1-T.sub.N, respectively. Each of the offset voltages V.sub.OFF1-V.sub.OFFN will raise a respective one of the modulated initial voltages V.sub.AMP1-V.sub.AMPN to a respective one of the modulated voltages V.sub.CC1-V.sub.CCN. For specific example as to how the offset voltages V.sub.OFF1-V.sub.OFFN can be modulated by the low frequency currents I.sub.DC1-I.sub.DCN to raise the modulated initial voltages V.sub.AMP1-V.sub.AMPN to the modulated voltages V.sub.CC1-V.sub.CCN, please refer to U.S. patent application Ser. No. 17/946,224, entitled “MULTI-VOLTAGE GENERATION CIRCUIT.”

[0052] FIG. 6 is a schematic diagram illustrating the transceiver circuit 20 in FIG. 2 configured to enable inter-symbol and intra-symbol voltage modulation. Common elements between FIGS. 2 and 6 are shown therein with common element numbers and will not be re-described herein.

[0053] Herein, the transceiver circuit 20 includes a digital baseband circuit 44, a signal processing circuit 46, and a target voltage circuit 48. The digital baseband circuit 44 is configured to generate an input vector {right arrow over (b.sub.MOD)} modulated in the symbols 14(X−1), 14(X), 14(X+1). According to the example described above, the symbol 14(X) is modulated to include the selected type of information, while the symbols 14(X−1) and 14(X+1) are not. In an embodiment, the digital baseband circuit 44 may determine which of the symbols 14(X−1), 14(X), 14(X+1) will be modulated with the selected type of information based on system configuration. For example, in a 5G or 5G-NR system, the exact symbol location of the selected type of information can be predefined in a standard, such as a third-generation partnership project (3GPP) standard.

[0054] The signal processing circuit 46, which may include digital-to-analog converter (DAC) and frequency converter (not shown), is configured to generate the RF signal 24 from the input vector {right arrow over (b.sub.MOD)} and provide the RF signal 24 to the power amplifier circuit 22 in FIG. 2.

[0055] In an embodiment, the target voltage circuit 48 may include an internal memory and an internal processor, which are not shown herein for the sake of simplicity. The internal memory, which can be any type of memory, may store a target voltage lookup table (LUT) that correlates a time-variant amplitude of the input vector {right arrow over (b.sub.MOD)} with various levels of voltage targets. The internal memory may also store the exact symbol location of the selected type of information such that the internal processor (e.g., a digital signal processor) in the target voltage circuit 48 can determine whether the selected type of information is modulated in any of the symbols 14(X−1), 14(X), 14(X+1). Alternatively, the digital baseband circuit 44 may provide an indication to the target voltage circuit 48 as to which of the symbols 14(X−1), 14(X), 14(X+1) is modulated with the selected type of information.

[0056] The target voltage circuit 48 is configured to determine the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 that correspond respectively to the symbols 14(X−1), 14(X), 14(X+1). In one embodiment, the internal processor of the target voltage circuit 48 determines that the symbol 14(X) is modulated to include the selected type of information. Accordingly, the internal processor in the target voltage circuit 48 divides the voltage modulation interval S.sub.X into the voltage modulation subintervals T.sub.1-T.sub.N and uses the target voltage LUT to generate the voltage targets V.sub.TGT-1-V.sub.TGT-N for the voltage modulation subintervals T.sub.1-T.sub.N, respectively. In another embodiment, the internal processor in the target voltage circuit 48 determines that the symbols 14(X−1) and 14(X+1) are not modulated to include the selected type of information. Accordingly, the internal processor in the target voltage circuit 48 uses the target voltage LUT to generate the single voltage target V.sub.TGT for the voltage modulation intervals S.sub.X−1 and S.sub.X+1. Further, the internal processor in the target voltage circuit 48 generates the target voltage indications V.sub.TGT(i) (i=X−1, X, X+1) and provides the target voltage indications V.sub.TGT(i) to the PMIC 18 via the inter-chip interface 26. In an embodiment, the target voltage LUT may store the various levels of voltage targets in digital formats. In this regard, the target voltage circuit 48 may also include an internal DAC (not shown) to convert the voltage targets V.sub.TGT-1-V.sub.TGT-N or the single voltage target V.sub.TGT into respective analog formats in the target voltage indications V.sub.TGT(i).

[0057] The transmission circuit 16 of FIG. 2 can be configured to enable inter-symbol and intra-symbol voltage modulation based on a process. In this regard, FIG. 7 is a flowchart of an exemplary process 200 for enabling inter-symbol and intra-symbol voltage modulation according to embodiments of the present disclosure.

[0058] Herein, the digital baseband circuit 44 is configured to generate an input vector {right arrow over (b.sub.MOD)} modulated to include the selected type of information in one or more (e.g., symbol 14(X)) of the symbols 14(X−1), 14(X), 14(X+1) (step 202). The target voltage circuit 48 is configured to determine the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 corresponding to the symbols 14(X−1), 14(X), 14(X+1) (step 204). The target voltage circuit 48 then divides a respective one (e.g., voltage modulation interval S.sub.X) of the voltage modulation intervals S.sub.X−1, S.sub.X, S.sub.X+1 into the voltage modulation subintervals T.sub.1-T.sub.N, each of the voltage modulation subintervals includes a respective one of the voltage targets V.sub.TGT-1-V.sub.TGT-N when the target voltage circuit 48 determines that a corresponding one (e.g., symbol 14(X)) of the symbols 14(X−1), 14(X), 14(X+1) includes the selected type of information (step 206). The target voltage circuit 48 then generates a respective one of the target voltage indications V.sub.TGT(i) (i=X−1, X, X+1) that includes the voltage targets V.sub.TGT-1-V.sub.TGT-N (step 208). The voltage generation circuit 30 will then generate the modulated voltages V.sub.CC1-V.sub.CCN in the voltage modulation subintervals T.sub.1-T.sub.N based on the voltage targets V.sub.TGT-1-V.sub.TGT-N, respectively (step 210).

[0059] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.