Fabrication of an optoelectronic semiconductor device and integrated circuit structure

Abstract

There is provided a method for fabricating an optoelectronic semiconductor device (2,27) including a layer stack (1,26) that comprises a metallization structure (7,7) including a contact region (8,11) for electrically contacting the semiconductor device (2,27). Moreover, a dielectric layer (12) and a semiconductor layer (3) are provided. The semiconductor layer (3) comprises a functional region (6) configured as an interface for electromagnetic (visible or UV) radiation. Material in regions (17,20) above the contact region (8,11) and above the functional region (6) of the layer stack (1,26) is removed by a temporarily simultaneous etching, thereby forming two windows (24,18) for coupling the semiconductor device (2,27) to the environment, optically as well as electrically. It is an accomplishment of the invention that coupling and/or absorption losses of radiation to be analysed optically in CMOS silicon and other semiconductors is reduced at the reduced process complexity.

Claims

1. A method for fabricating an optoelectronic semiconductor device (2, 27), comprising the steps of: providing a layer stack (1, 26) including at least one metallization structure (7, 7) that includes at least one contact region (8, 11) for electrically contacting the semiconductor device (2, 27); said layer stack (26) including at least one dielectric layer (12) and at least one semiconductor layer (3), wherein the semiconductor layer (3) includes at least one functional region (6) configured as an interface for electromagnetic radiation; and stripping or removing material of the layer stack (1, 26) by a common stripping or removal in local regions (17, 20) above the at least one contact region (8) and above the functional region (6); thereby exposing or forming two differently deep windows (18, 24; 18, 24) for coupling the semiconductor device (2, 27) to an environment.

2. The method according to claim 1, wherein the metallization structure (7, 7) is integrated into the dielectric layer (12) such that the dielectric layer (12) above the at least one functional region (6) is recessed more deeply (h.sub.24, h.sub.24) by said stripping or removing as compared to the local region (17) above the contact region (8).

3. The method according to claim 1, wherein a mask (16) is applied above the layer stack (1, 26) and the local stripping or removing is performed by using the mask (16).

4. The method according to claim 3, wherein the mask (16) is formed by at least one of a photolithography process and a modification of an etch mask (16) provided for exposing the contact region (8, 11).

5. (canceled)

6. The method according to claim 1, further comprising: forming a further passivation layer (28) above the layer stack (26), said further passivation layer reaching into the region (20) exposed above the functional region (6) and into the exposed region (17) above the contact region (8); removing the further passivation layer (28) in part within the region (17) that was exposed above the contact region (8).

7. The method according to claim 1, wherein the functional region (6) of the semiconductor layer (3) comprises at least one of a light emitting region and a light sensitive region.

8. The method according to claim 1, wherein the layer stack (1, 26) including the at least one metallization structure is provided with a multilayer wiring (7, 7*).

9. An integrated circuit structure comprising a plurality of semiconductor devices (2, 27) and respective an associated optoelectronic interface (6) for coupling the integrated circuit structure to an environment, the semiconductor devices (2, 27) being produced by: providing a layer stack (1, 26) including at least one metallization structure (7, 7) that includes at least one contact region (8, 11) for electrically contacting the semiconductor device (2, 27); said layer stack (26) including at least one dielectric layer (12) and at least one semiconductor layer (3), wherein the semiconductor layer (3) includes at least one functional region (6) configured as an interface for electromagnetic radiation; and stripping or removing material of the layer stack (1, 26) by a common stripping or removal in local regions (17, 20) above the at least one contact region (8) and above the functional region (6); thereby exposing or forming two differently deep windows (18, 24; 18, 24) for coupling the semiconductor device (2, 27) to an environment.

10. The circuit structure according to claim 9, wherein the plurality of semiconductor devices (2, 27) forms a CMOS structure.

11. The circuit structure according to claim 9, wherein the interfaces comprise a window (24, 24) formed by etching whose lateral extension is greater in at least one direction by at least one of a predefined factor and a predefined amount than a lateral extension of a respective optoelectronically functional region (6) below the respective interface of the respective semiconductor device (2, 27).

12. The circuit structure according to claim 9, wherein a window (24, 24) formed by one of stripping or removing extends across a plurality of the optoelectronically functional regions (6).

13. The circuit structure according to claim 11, wherein at least one of an electric wiring of a metallization structure (7, 7, 7, 7*) and components of a metal aperture extends into an area laterally adjacent to at least one of the functional region (6) and the window (24) or is placed therein.

14. A semiconductor device (2, 27) having optoelectronic properties, said semiconductor device being produced by: providing a layer stack (1, 26) including at least one metallization structure (7, 7) that includes at least one contact region (8, 11) for electrically contacting the semiconductor device (2, 27); said layer stack (26) including at least one dielectric layer (12) and at least one semiconductor layer (3), wherein the semiconductor layer (3) includes at least one functional region (6) configured as an interface for electromagnetic radiation; and stripping or removing material of the layer stack (1, 26) by a common stripping or removal in local regions (17, 20) above the at least one contact region (8) and above the functional region (6); thereby exposing or forming two differently deep windows (18, 24; 18, 24) for coupling the semiconductor device (2, 27) to an environment.

15. The method according to claim 1, wherein the etching is selective and is performed for a predefined etch time that is selected such that the etching ends at the contact region (8) after a time period that is shorter than the predefined etch time and the etching continues in the region (2) located above the at least one functional region (6).

16. The method according to claim 1, wherein the stripping or removal of the layer stack (1, 26) is performed by etching.

17. The method according to claim 16, wherein the layer stack (1, 26) comprises a passivation layer (13) that is opened by the etching.

18. The method according to claim 5, wherein the passivation layer (13) is formed from silicon nitride.

19. The method according to claim 7, wherein the light sensitive region comprises a UV light sensitive region.

20. The integrated circuit structure of claim 9, wherein the stripping or removal of the layer stack (1, 26) is performed by etching, the etching being selective and being performed for a predefined etch time that is selected such that the etching ends at the contact region (8) after a time period that is shorter than the predefined etch time and the etching continues in the region (2) located above the at least one functional region (6).

21. The semiconductor device (2, 27) of claim 14, wherein the stripping or removal of the layer stack (1, 26) is performed by etching, the etching being selective and being performed for a predefined etch time that is selected such that the etching ends at the contact region (8) after a time period that is shorter than the predefined etch time and the etching continues in the region (2) located above the at least one functional region (6).

Description

[0043] Further embodiments are put forward in the following detailed description, while referring to the drawings, which serve to illustrate preferred embodiments in an exemplary and highly schematic manner without being read into the claims based on the concrete statements and announcements, if more general terms are used therein. In the following like or similar components are denoted by the same reference signs throughout the drawings.

[0044] FIG. 1 is a schematic view of the layer stack 1 of an optoelectronic semiconductor device 2 according to an embodiment of the invention.

[0045] FIG. 2 is a schematic view illustrating a lateral portion 14 of the layer stack of the optoelectronic device of FIG. 1, wherein a sacrificial layer 15 is additionally applied above the layer stack for forming a masking 16 according to one embodiment of the invention.

[0046] FIG. 3 is a schematic in view of the layer stack of FIG. 2 after a further step, in which the sacrificial layer has been patterned into a mask 16 according to one embodiment of the invention.

[0047] FIG. 4 is a schematic view of the masked layer stack of FIG. 3 in an intermediate state during at process in regions 17 and 20 according to one embodiment of the invention.

[0048] FIG. 5 is a view of the masked layer stack of FIGS. 3 and 4 in a further advanced intermediate state during the etching, wherein the etching has advanced to a depth h.sub.8 (also h.sub.18 for the window 18) of a contact region of the metallization structure according to one embodiment of the invention.

[0049] FIG. 6 is a view of the masked layer stack of FIGS. 3 to 5 in a still further advanced state after a predefined etch time, thereby forming the optical window 24 having the depth h.sub.24 according to one embodiment of the invention.

[0050] FIG. 7 is a schematic view of an initial state of a further layer stack 26 having a sacrificial layer 15 formed thereon, wherein, contrary to FIG. 1, more details of a multilayer wiring 7 and 7* are illustrated in the layer stack according to a further embodiment of the invention.

[0051] FIG. 8 is a schematic view of the layer stack of FIG. 7 after the patterning, thereby forming a window 24 of depth h.sub.24 above the optically functional region for optical coupling to the environment, and a further window 18 of depth h.sub.18 has been formed above the metal 8 according to one embodiment of the invention.

[0052] FIG. 9 is a schematic view of an optoelectronic semiconductor device that corresponds to the patterned layer stack of FIG. 8, wherein the sacrificial layer 15 has been removed.

[0053] FIG. 10 is a schematic view of an optoelectronic semiconductor device, wherein, contrary to FIG. 9, the two lower metal layers 25 of the metallization structure 7 and 7* extend to the optical window 24.

[0054] FIG. 11 is a schematic view of an optoelectronic semiconductor device including a window 24 above a light sensitive region 6, wherein within the window and above the semiconductor device a thin additional passivation layer 28 has been formed according to one embodiment of the invention.

[0055] FIG. 1 illustrates a schematic view of a layer stack 1 of an optoelectronic semiconductor device 2 according to a first embodiment. The semiconductor device 2 is arranged on a substrate (not shown) and includes a semiconductor layer 3 having doped regions 4 and 5.

[0056] For example, the first doped region 4 may be a source region and the second doped region 5 may be a drain region. Between the doped regions 4 and 5 there is disposed an optoelectronically effective functional region 6. It may be light sensitive for visible light or specifically UV radiation.

[0057] The functional region 6 in this embodiment is configured as a UV light sensitive region. By means of UV light sensitive region in particular the conductivity between the doped regions 4, 5 may be controlled by irradiating UV light of a certain light intensity onto the light sensitive region 6. In this manner, for instance a UV light sensor may be realized. Generally, a function similar to a gate may be achieved or may be provided by the light sensitive region 6.

[0058] To this end, the semiconductor device 2 includes metallization structures 7 and 7 spaced apart from each other, which include wirings and electrical contacts. The metallization structures 7, 7 are adapted depending on the application and the geometrical circumstances of the semiconductor device 2 upon forming the semiconductor device 2. For simplicity FIG. 1 merely illustrates a first contact region 8 connected to the first doped region 4 by a first metallic through-contact 8a as a via (structure 7), and includes a second contact region 11 connected to the second doped region 5 by a second metallic through-contact 11a as a via (structure 7). Additionally, the semiconductor device 2 may also include horizontal wirings in the layer or level 8-11 as a component of the metallization structures 7, 7.

[0059] In this case the metallization structures 7 and T are integrated into a dielectric layer 12, which is used for electrical insulation of the remaining layers and the metallization structures. The dielectric layer 12 may preferably be made from SiO.sub.2 or any other conventional materials. Metallization structure 7 is positioned on the left-hand side, structure 7 is positioned on the right-hand side of the functional region 6.

[0060] Moreover, the layer stack 1 includes an upper passivation layer 13 for protecting the layers located below. The passivation layer 13 according to this embodiment is formed from Si.sub.3N.sub.4 that exhibits no or only low light absorption in the visible wavelength range, which, however, strongly absorbs light in the UV range. As illustrated in FIG. 2, the layer stack 1 is provided with a sacrificial layer 15, from which an etch mask is to be formed.

[0061] The contact regions 8, 11 should serve the purpose of attaching electrical terminals to the semiconductor device 2, for instance by bonding or by further metallic through-contacts as vias 8a and 11a. To this end, openings (that is windows) in the layer(s) stack 1 are formed to the contact regions 8, 11.

[0062] FIG. 2 illustrates a schematic view showing a lateral partial section 14 of the layer(s) stack 1 of the optoelectronic semiconductor device 2 of FIG. 1 according to one embodiment of the invention. As shown in FIG. 2, the layer stack 1 has been provided with a sacrificial layer 15, from which an etch mask is to be formed. For simplicity, here only the first contact region 8 and the optoelectronically functional region 6 are illustrated, whereas the second contact region 11, the through-contacts 8a, 11a and the doped regions 4 and 5, already explained above, are no longer illustrated.

[0063] The etch mask (pad mask) 16, obtained from layer 15, is used for opening the passivation layer 13 and any layers formed therebelow to the uppermost metal wiring layer in order to allow electrical contact thereof.

[0064] Openings of this type are not only formed above areas with metal in the uppermost wiring level, but also in areas having a desired light in-coupling. Since the etching stops at a deeper position in the silicon oxide insulation stack, the result is that no strongly UV absorbing layer is present above the light sensitive regions of the CMOS circuit.

[0065] In the following description further steps of embodiments of the invention are illustrated, by which a window for electromagnetic radiation above the functional region 6 as well as a passage to the contact regions, for instance contact region 8, are formed.

[0066] FIG. 3 illustrates a schematic view of the layer stack 1 of FIG. 2 after a further step, in which the sacrificial layer 15 has been patterned into the mask 16 according to one embodiment of the invention. In this state, for example, the sacrificial layer 15 is prepared as an etch mask 16 for the following process steps. This may be accomplished by a photolithography procedure. The etch mask is appropriately modified, which is initially provided for forming a window (as a passage) located in a first region 17 to the exemplary contact region 8 and which is provided with a corresponding opening. In this manner, the etch mask 16 now additionally has an opening for a second window to be formed in a second region 20 after the modification, through which the functional region 6 buried in the layer stack 1 is coupled to the environment.

[0067] FIG. 4 illustrates a schematic view of the masked layer stack 1 of FIG. 3 in an intermediate state during the etch process according to one embodiment of the invention. As illustrated in FIG. 4, the window (the passage) in the region 17 and the window 24 in the region 20 have a depth h.sub.13+, at which the passivation layer 13 has been opened and already a certain amount of material of the dielectric layer 12 has been removed. However, neither the left window nor the right window is completed with respect to the depth to be finally reached.

[0068] FIG. 5 illustrates a schematic view of the masked layer stack 1 of FIGS. 3 and 4 in a still further advanced etch state, wherein the etching has been performed to a depth h.sub.8 to the surface of the contact region 8 of the metallization structure 7 according to one embodiment of the invention. Since, on the one hand, the etching of the window or passage 18 is performed in the region 17 to the contact region 8 and, on the other hand, the etching of the window 24 is performed in the region 20 to the optoelectronically functional region 6 on the basis of an etch process that is up to this point a common process, the passage 18 in the region 17 and the window 24 in the region 20 have substantially the same depth h.sub.8 or h.sub.18 in this state of the process with regard to the window 18 that is completed with respect to the final depth.

[0069] FIG. 6 illustrates a schematic view of the masked layer stack 1 of FIGS. 3 to 5 in a still further advanced etch state after expiration of a predefined etch time according to one embodiment of the invention. According to the embodiment illustrated here a selective etch process was selected regarding the material of the contact region 8 of the metallization structure 7 so that the etching stops or has stopped in the region 17 at the contact region 8, whereas in the region 20 the etching still continues. After expiration of a given or predetermined etch time the window 24 has reached the intended depth h.sub.24, at which also the etching for the optical window is stopped.

[0070] Thereafter the sacrificial layer 15 obtained from the etch mask 16 may be removed.

[0071] FIG. 7 illustrates a schematic view of an initial state of a further layer(s) stack 26 of a further semiconductor device 27 according to a further embodiment of the invention. As illustrated in FIG. 7, the layer stack 26 is provided with a sacrificial layer 15. Contrary to FIG. 1, in this layer stack 26 several layers or levels 25 of the metallization structure 7 (left-hand side) and 7* (right-hand side) are used at both sides of the functional region 6, thereby facilitating more complex wirings. The contact pad or the contact region 8 is stacked several times at the left-hand side and is respectively contacted through a via 8a to next deeper level 25. The same holds true for the multilayer system 25 at the right-hand side, which includes contact regions 11 and via 11a, and this holds true for a plurality of metallization layers or levels 25.

[0072] FIG. 8 illustrates a schematic view of the layer stack 26 of FIG. 7 after the steps of patterning and etching, thereby forming a passage 18 to the contact region 8 of the uppermost metal layer and a window 24 for electromagnetic radiation, in particular for UV light, in a region 20 above the optoelectronically functional region 6. The depth of window 18 is h.sub.18.

[0073] In the pad level an opening in the resist mask was formed above the optically sensitive region 6 by means of photolithography so that the subsequent pad etching in this region and at each pad, that is, at each contact region 8, removes the passivation layer 13 as well as respective subsequent dielectric insulation layers. Here, the pad etching stops upon reaching the metallic pads (contact region 8) and after a short over-etch time. Since the preferably UV sensitive region 6 does not include metallic structures, a recess h.sub.24 is obtained that extends below the uppermost metal layer.

[0074] In order to guarantee that no metal is encountered in the region 20 of the window 24 also the second uppermost metal is forbidden in the entire region 20 of the corresponding mask openings.

[0075] In a four-metal layer process therefore metal traces of the first and at most of the second metal layers 25 may be light emitting below the UV window 24, but metal traces of the third and fourth (uppermost) metal layers 25 will not be capable of emitting light. Preferably, h.sub.24 terminates below the first metal layer 8 and in front of (or above) the second metal layer, it is, however, deeper than the etch depth h.sub.18 that reaches to the contact region 8 (left-hand side). This corresponds to the result of FIG. 6 for the one-layer metal level.

[0076] FIG. 9 illustrates a schematic view of an optoelectronic semiconductor device 27 that corresponds to the patterned layer stack 26 of FIG. 7 or 8, wherein the sacrificial layer 15 (its mask residue 16) has been removed. As illustrated in FIG. 9 light or UV light 19 may be incident through the window 24 in the region 20 onto the functional region 6, wherein absorption and reflection are now reduced.

[0077] FIG. 10 illustrates a schematic view of a comparable optoelectronic semiconductor device 27, wherein, contrary to FIG. 9, the two lower metal layers 25 of the four-layer metallization structure 7 and 7 extend within the window 24.

[0078] Since the UV window 24 may extend across several UV sensitive regions 6 coupling in of light is accomplished as homogeneous as possible, wherein even the electric wiring or metal apertures may be provided within the UV window 24. Among others, this allows the provision of filters on the wafer for modifying the incident light spectrum without negative effect of the steep steps at the edge of the UV window on the sensor performance, since these regions may be formed at a far distance with respect to the UV sensitive regions 6.

[0079] FIG. 11 is a schematic view of an optoelectronic semiconductor device 27 including a window 24 above a light sensitive region 6, wherein a thin additional passivation layer 28 has been applied in the window 24 and above the semiconductor device 26 according to a further embodiment.

[0080] According to this embodiment, after exposing the region by etching an additional Si.sub.3N.sub.4 layer 28 is deposited for the window 24 and the region 17 above the contact region 8 in this manner. This layer is patterned by means of an additional mask (not shown), thereby removing the layer in the region 17 of the contact region 8 and thus allowing the final chip to be electrically contacted.

[0081] In this manner, the passivation protection of the semiconductor device 27 is also achieved in the deeply etched region 20 of the window 24 above the functional region 6, wherein the thickness of the passivation layer 28 deposited and the associated absorption may specifically be reduced by an order of magnitude compared to the original first passivation layer 13.