Abstract
A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.
Claims
1. A method of making stacked lateral semiconductor devices comprising: depositing alternating layers of first and second material on a single crystal semiconductor substrate, the first and second material having different etching characteristics; removing a hole region of each of the layers down to the substrate; using the substrate as a seed, forming single crystal semiconductor material in the hole region; removing an isolation slot region of each of the layers down to the substrate, the isolation slot being disposed between adjacent hole regions; filling the isolation slot with dielectric material; removing a stack cut region of each of the layers down to the substrate, the stack cut region being orthogonal to and spaced apart from a first end of the isolation slot; removing the layers of second material; forming single crystal semiconductor material in place of the layer; of second material; and during the step of forming single crystal semiconductor material in place of the layers of second material, introducing at least one semiconductor dopant to dope the single crystal semiconductor material to have desired conductivity type.
2. A method as in claim 1 wherein the step of introducing at least one semiconductor dopant comprises introducing both p-conductivity and n-conductivity type dopants to form at least one pn junction.
3. A method as in claim 2 wherein the first and second material comprise silicon dioxide and silicon nitride respectively, and the dielectric material comprises silicon dioxide.
4. A method as in claim 3 followed by a step of forming electrical connections to exposed portions of the single crystal semiconductor material resulting from the step of forming single crystal semiconductor material in place of the of the layers of second material.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a perspective view of an 8-layer stacked memory array with semiconductor junction device memory cells.
[0018] FIGS. 2A and 2B are a perspective and cross-sectional views after etching first slots through a layered insulator stack.
[0019] FIGS. 3A and 3B are a perspective and cross-sectional views after forming single crystal semiconductor fences in the structure of the preceding figure.
[0020] FIG. 4 is a perspective view after etching support slots in the structure of the preceding figure.
[0021] FIG. 5 is a perspective view after filling the support slots with dielectric material.
[0022] FIGS. 6A and 6B are a perspective and cross-sectional views after stack cuts are made in the structure.
[0023] FIGS. 7A and 7B are a perspective and cross-sectional views after an etching step.
[0024] FIGS. 8A and 8B are a perspective and cross-sectional views after growth of single crystal semiconductor material.
[0025] FIG. 8C illustrates PNP and PIN devices.
[0026] FIG. 9 is a perspective view after final cut etching.
[0027] FIG. 10 is a perspective view of a second embodiment of a three-dimensional semiconductor structure.
[0028] FIGS. 11A and 11B are a perspective and cross-sectional views after etching holes through a layered insulator stack.
[0029] FIGS. 12A and 12B are a perspective and cross-sectional views after forming single crystal semiconductor pillars in the structure of the preceding figure.
[0030] FIG. 13 is a perspective view after etching ELO isolation slots in the structure of the preceding figure.
[0031] FIG. 14 is a perspective view after filling the isolation slots with dielectric material.
[0032] FIGS. 15A and 15B are a perspective and cross-sectional views after stack cuts are made in the structure.
[0033] FIGS. 16A and 16B are a perspective and cross-sectional views after etching to expose the pillars.
[0034] FIGS. 17A and 17B are a perspective and cross-sectional views after formation of single crystal semiconductor using the exposed pillars.
[0035] FIG. 18 is a cross-sectional view after formation of electrical connections.
[0036] FIG. 19 is a cross-sectional view after filling of the stack cuts with dielectric material.
DETAILED DESCRIPTION OF THE INVENTION
[0037] The assignee of this application has previously disclosed memory devices suitable for a variety of applications. It is advantageous, however, to be able to stack the memory cells to provide multiple layers of memory cells in a memory array. This increases bit density per unit area and further reduces patterning cost. This application discloses designs and methods of manufacturing a multiple layer single crystal semiconductor structure.
[0038] Features of the invention include: an exemplary stacked memory array with memory cells selectively formed using confined epitaxial lateral overgrowth (ELO) of single crystalline silicon, or other semiconductor materials. If the devices are thyristor memory cells, each thyristor consists of pnpn or npnp thyristor in-situ doped during epitaxial growth.
[0039] FIG. 1 illustrates a small portion of a semiconductor memory array structure where junction devices 16 are repeated in 3-dimensions. FIGS. 2-9 illustrate a preferred process for fabricating the array. In FIG. 1, the three-dimensional array of junction devices in single crystal semiconductor using ELO seeded from vertical selective epitaxial growth (SEG) single crystal semiconductor walls. Junction devices are isolated after ELO growth by vertical cut and dielectric material fill.
[0040] In a typical implementation, the structure shown in FIG. 1 is only a small portion of the memory array. In FIG. 1 the memory cells are preferably thyristors, however, those of skill in the art will appreciate other types of memory devices may also be employed. For example, in other embodiments, phase change memory cells, fuses, anti-fuses, resistive elements or other memory cell types can be employed from the teaching of this invention.
[0041] As shown in FIG. 1, on a semiconductor substrate 10, SEG semiconductor columns 12 are electrically isolated from other columns by intervening dielectric columns 13. Each layer of junction devices 16 is isolated from layers above and below it by an intervening layer of dielectric 11.
[0042] FIG. 2A is a perspective view, and FIG. 2B is a cross-sectional view along line A-A, after forming a stack of alternating layers 22 of two materials having different etching characteristics, e.g., silicon dioxide and silicon nitride. The number of layers deposited determines the number of layers of memory devices to be formed, with one layer of, e.g., silicon nitride deposited for each layer of memory cells. On the top of the structure, a hard mask 15, typically a metal oxide such as aluminum oxide (Al.sub.2O.sub.3), is formed. After patterning the mask, appropriate etchants are used to cut slots 20 through all layers for formation of single crystal silicon. The slots 20 extend through the layers, stopping at the single crystal semiconductor substrate 10.
[0043] As next shown by FIGS. 3A and 3B, after a well-known post-etch cleaning, single crystal semiconductor fences or walls are grown inside the slots using selective epitaxial growth (SEG). The SEG process grows single-crystal silicon only from the bottom of the slots where the single crystal semiconductor substrate 10 is exposed.
[0044] The next steps in the process are illustrated by FIGS. 4 and 5. Using lithography masking and well-known dry etching technology, support slots 40 are etched through all of the layers down to and optionally into the substrate 10. Then, as shown in FIG. 5, the slots are filled with dielectric material 50 to provide dielectric support pillars. The structure is then planarized, preferably using a chemical mechanical polishing process (CMP). The dielectric support pillars are repeated for specified distances ranging from 1 m to 100 m depending on the number of layers. The purpose of the pillars is to support mechanically the number of first dielectric layers after the second dielectric layers are etched away, as described below in FIG. 7.
[0045] The next step in the process is etching stack cuts 60 through all of the layers down to the bottom dielectric layer, usually silicon dioxide. The stack cuts are shown in FIG. 6A. The cuts 60 divide the structure into parallel stacks of layers in which electrically separate semiconductor devices will be formed, as described below. The stack cuts 60 are made in the areas between the support slot cuts and their dielectric 50. The cuts are shown in cross-section in FIG. 6B. After making the cuts 60, the exposed semiconductor surfaces are oxidized to prevent further epitaxial silicon growth in those regions, labeled blocking oxide 64 in FIGS. 6A and 6B.
[0046] Using an appropriate isotropic etchant the structure is next selectively etched to remove the alternating layers of the stacks where exposed by the stack cuts. The resulting structure is shown in FIG. 7A and in cross-section in FIG. 7B. In the preferred embodiment the silicon nitride layers are removed, leaving only the silicon dioxide layers. The silicon dioxide layers 22 are supported by the dielectric 50 and the SEG 30 fences.
[0047] FIGS. 8A and 8B illustrate the next steps in the process. Using the exposed SEG semiconductor 30 side surface as a seed, single crystal semiconductor 80 is grown between the layers of silicon dioxide. This process is preferably performed using known confined epitaxial lateral overgrowth (ELO). The growth of single crystal silicon by ELO occurs only at crystalline semiconductor surfaces. As the process proceeds, desired semiconductor dopants are introduced into the gas flow to create doped semiconductor regions. The choice of dopants depends upon the semiconductor devices to be formed. For illustration in FIGS. 8A and 8B alternating dopant gases of diborane (B.sub.2H.sub.6) and phosphine (PH.sub.3) are used toform a pnpn semiconductor thyristor. Of course other devices such as pn or np diodes, p-i-n or n-i-p diodes, p-n-p or n-p-n diodes, programmable links, fuses, etc. could be formed in place of the illustrated thyristors. Examples of such are shown in FIG. 8C.
[0048] After forming the desired semiconductor devices, electrical connections 94, to the last formed portion of the devices, can be made using known metal silicide processes followed by a conformal deposition of low resistivity metal. After deposition the metal is isotropically etched to fill the cavity openings between the layers as shown.
[0049] Next using another mask, the semiconductor sheet devices 16 are then separated by a reactive ion etching process into separate stacks, as shown in FIG. 9. Optionally the etching process can be continued to etch into the semiconductor substrate 10 to improve electrical isolation between the semiconductor regions 30. Following the etch, an insulating material 51 is deposited to fill the cuts 90 to form insulating columns 14, as shown in FIG. 1, and a CMP process planarizes the structure to prepare it for known processes to provide electrical connections.
[0050] FIG. 10 illustrates a second embodiment for a 3-dimensional array of junction devices. This structure is also formed using epitaxial lateral overgrowth (ELO), however, in this implementation seeded from vertical single crystal semiconductor pillars 130, instead of walls as in FIGS. 1-9. Compared to the embodiment above, the process flow for the structure shown in FIG. 10 reduces the number of masking, etch and CMP operations, however, the requirements for the SEG and ELO steps are more stringent because of the need for cleaning and epitaxial growth into much smaller areas. FIG. 10 also shows substrate 100, ELO semiconductor devices 116, silicide and metal contacts 117, hard mask 115, and dielectric 113.
[0051] FIG. 11A is a perspective view, and FIG. 11B is a cross-sectional view along line B-B, after forming a stack of alternating layers 122 of two materials having different etching characteristics, e.g., silicon dioxide and silicon nitride. The number of layers deposited determines the number of layers of memory devices to be formed, with in this embodiment one layer of silicon nitride deposited for each layer of memory cells. On the top of the structure a hard mask 115, typically a metal oxide such as Al.sub.2O.sub.3, is formed. After patterning the mask, appropriate etchants are used to cut holes 112 for later formation of single crystal silicon, for example, using an SEG process. The holes 112 extend through all the layers, stopping at the single crystal semiconductor substrate 100.
[0052] As next shown by FIGS. 12A and 12B, after a post-etch cleaning, single crystal semiconductor pillars are grown inside the holes 112 using selective epitaxial growth. The SEG process grows single-crystal silicon only from the bottom of the holes where the single crystal semiconductor substrate 100 is exposed.
[0053] The next steps in the process are illustrated by FIGS. 13 and 14. Using another lithography masking step and known dry etching technology, isolation slots 130 are etched through all of the layers down to and optionally into the substrate 10. Then, as shown in FIG. 14, the slots 130 are filled with dielectric material 140 and the structure planarized, preferably using a chemical mechanical polishing process.
[0054] The next step in the process is etching stack cuts 150 through all of the layers down to the bottom dielectric, e.g. silicon dioxide. This is illustrated in FIG. 15A and 15B. The cuts 150 divide the structure into parallel stacks of layers in which electrically separate semiconductor devices will be formed as described below. The stack cuts are made in the areas between the isolation slots 130. The cuts are shown in cross-section A-A in FIG. 15B. After making the cuts 150, the exposed semiconductor surfaces are oxidized to prevent further epitaxial silicon growth in those regions. This oxide is labeled blocking oxide 154 in FIGS. 15A and 15B.
[0055] Using an appropriate isotropic etchant the structure is next etched to remove alternating layers of the stacks where the edges of those layers are exposed by the stack cuts. The resulting structure after etching is shown in FIG. 16A and in cross-section A-A in FIG. 16B. In the preferred embodiment the silicon nitride layers are removed, leaving only the silicon dioxide layers. The silicon dioxide layers are supported by the surrounding material. This etch also exposes the sidewalls of the SEG pillars 125.
[0056] FIGS. 17A and 17B illustrate the next steps in the process. Using the exposed SEG semiconductor 125 sidewall surfaces as seed, single crystal semiconductor 170 is grown between the layers of silicon dioxide. This process preferably is performed using confined epitaxial lateral overgrowth, as mentioned above. The growth of single crystal silicon by ELO occurs only at single crystal semiconductor surfaces. As the process proceeds, desired semiconductor dopant is introduced into the gas flow to create doped semiconductor regions. The choice of dopants depends upon the semiconductor devices to be formed. For illustration in FIGS. 17A and 17B alternating dopant gases of diborane (B.sub.2H.sub.6) and phosphine (PH.sub.3) are used to form a pnpn semiconductor thyristor. Of course other devices such as pn or np diodes, p-i-n or n-i-p diodes, p-n-p or n-p-n diodes, programmable links, fuses, etc. could be formed by use of appropriate processing in place of the illustrated thyristors.
[0057] After forming the desired semiconductor devices, electrical connections 180 to the last formed, and therefore exposed edge, using a known metal silicide process followed by a conformal deposition of low resistivity metal 182. After deposition the metal 182 is isotropically etched to fill the cavity openings between the layers, as shown in FIG. 18.
[0058] Following the etch, an insulating material 190 is deposited, filling the cuts, and a CMP process planarizes the structure and prepare it for well-known processes to form additional electrical connections as shown in FIG. 19.
[0059] This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.
