LEVEL CONVERTER AND CIRCUIT ARRANGEMENT COMPRISING SUCH LEVEL CONVERTERS

Abstract

A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.

Claims

1-12. (canceled)

13. A level converter, comprising: a transistor; an impedance converter; an input voltage connection; an output voltage connection; and a power supply connection; wherein: the input voltage connection is connected to a gate terminal of the transistor and is equipped to be connected to an input voltage that is to be shifted by the level converter, the output voltage connection is connected to a source terminal of the transistor and to the power supply connection and is equipped to provide the input voltage that is to be shifted by the level converter as an output voltage, a first input terminal of the impedance converter is connected to the source terminal of the transistor, or the gate terminal of the transistor, an output terminal of the impedance converter is connected to a drain terminal of the transistor, the power supply connection is equipped to receive a current from a constant current source, and the impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.

14. The level converter as recited in claim 13, wherein the transistor is a MOSFET.

15. The level converter as recited in claim 13, wherein the transistor is: (i) a p-channel MOSFET or an n-channel MOSFET, or (ii) an npn bipolar transistor or a pnp bipolar transistor, or (iii) an n-channel JFET or a p-channel JFET, or (iv) a p-channel FinFET or an n-channel FinFET.

16. The level converter as recited in claim 13, wherein the reference voltage is provided based on a voltage source upstream from the first input terminal of the impedance converter.

17. The level converter as recited in claim 13, wherein the impedance converter includes a differential amplifier, the first input terminal of the impedance converter corresponds to a positive input terminal of the differential amplifier, and a second input terminal of the impedance converter, which corresponds to a negative input terminal of the differential amplifier, is connected to the drain terminal of the transistor.

18. The level converter as recited in claim 17, wherein the reference voltage is based on a predefined voltage offset between a positive and a negative signal path of the differential amplifier of the impedance converter.

19. The level converter as recited in claim 18, wherein the predefined voltage offset is achieved in the positive and negative signal paths of the differential amplifier using: different resistors, and/or different voltage sources, and/or different power sources, and/or transistors having different characteristics.

20. The level converter as recited in claim 13, wherein the level converter is an integrated circuit and/or as a discrete circuit.

21. The level converter as recited in claim 13, wherein a bulk-source voltage of the transistor corresponds to a predefined potential difference.

22. The level converter as recited in claim 21, wherein the potential difference is 0 V.

23. The level converter as recited in claim 13, wherein the impedance converter has substantially a voltage amplification of one.

24. The level converter as recited in claim 13, wherein the level converter is used in a battery management system, and/or in conjunction with a current measurement technology.

25. A circuit arrangement, comprising: a first level converter, and a second level converter, each of which includes: a transistor; an impedance converter; an input voltage connection; an output voltage connection; and a power supply connection; wherein: the input voltage connection is connected to a gate terminal of the transistor and is equipped to be connected to an input voltage that is to be shifted by the level converter, the output voltage connection is connected to a source terminal of the transistor and to the power supply connection and is equipped to provide the input voltage that is to be shifted by the level converter as an output voltage, a first input terminal of the impedance converter is connected to the source terminal of the transistor, or the gate terminal of the transistor, an output terminal of the impedance converter is connected to a drain terminal of the transistor, the power supply connection is equipped to receive a current from a constant current source, and the impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage, wherein: the first level converter is equipped to shift a positive input signal that is related to a negative input signal by a predefined level, the second level converter is equipped to shift the negative input signal by the same predefined level as the first level converter, and the circuit arrangement is equipped to be used for a differential measurement between a positive output signal of the first level converter and a negative output signal of the second level converter.

26. The circuit arrangement as recited in claim 25, wherein the first level converter and the second level converter are arranged in such a way that environmental effects on the first level converter and on the second level converter have a substantially uniform effect on the first and second level converters.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Below, example embodiments of the present invention will be described in detail with reference to the figures.

[0023] FIG. 1 is a circuit diagram of a specific embodiment of a level converter according to the present invention.

[0024] FIG. 2 is a circuit diagram of a further specific embodiment of a level converter according to the present invention.

[0025] FIG. 3 is a circuit diagram of an exemplary circuit arrangement for a differential voltage measurement on the basis of a level converter according to the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0026] FIG. 1 is a circuit diagram of a specific example embodiment of a level converter according to the present invention. The level converter here comprises a p-channel MOSFET 10 (abbreviated below to “PMOS 10”), the source terminal 12 of which is bypassed with a bulk terminal 18 of the PMOS 10, as a result of which a source-gate voltage U.sub.SG of the PMOS 10 is kept substantially constant. A gate terminal 16 of the PMOS 10 is connected to an input voltage connection 30 by way of which an input voltage U.sub.E related to a ground potential M of the level converter is fed in, the level of which input voltage is raised by 2 V here using the level converter. An output voltage connection 40 of the level converter is connected to the source terminal 12 of the PMOS 10 and to a power supply connection 50, and is equipped to provide the input voltage U.sub.E raised by 2 V by the level converter as output voltage U.sub.A. The power supply connection 50 is connected to a first connection of a constant current source 60 that provides a constant current I. For this, the constant current source 60 is connected to a second connection with a positive supply voltage V.sub.DD. The source terminal 12 is furthermore connected to a first connection of a reference voltage source 80 that provides a predefined constant reference voltage. A second connection of the reference voltage source 80 is connected to a first input terminal 22 of an impedance converter 20. An output terminal 26 of the impedance converter 20 is connected to a drain terminal 14 of the PMOS 10. The impedance converter 20 is equipped to keep a source-drain voltage U.sub.SD of the PMOS 10 at a predefined value using the reference voltage.

[0027] FIG. 2 shows a circuit diagram of a further specific embodiment of a level converter according to the present invention. It should be pointed out that, owing to the similarities between the specific embodiments of the level converter according to the present invention in FIGS. 1 and 2, in order to avoid repetition only the differences between the two figures will be described below. The impedance converter 20 in the specific embodiment shown in FIG. 2 is implemented on the basis of a differential amplifier. The first input terminal of the impedance converter 20 thus corresponds here to a positive input terminal 22 of the differential amplifier. A second input terminal of the impedance converter corresponds to a negative input terminal 24 of the differential amplifier. The negative input terminal 24 of the differential amplifier is connected to a drain terminal 14 of the PMOS 10.

[0028] FIG. 3 shows a circuit diagram of an exemplary circuit arrangement for a differential voltage measurement on the basis of the level converter according to the present invention. The circuit arrangement is marked using the broken line in FIG. 2 and comprises a first level converter 70 and a second level converter 75 that are constructed identically and are arranged here in the immediate vicinity of each other in an integrated circuit. A positive input signal U.sub.EP, which is related to a negative input signal U.sub.EN, is fed into an input voltage connection 30 of the first level converter 70. A negative input signal U.sub.EN, which is related to the positive input signal U.sub.EP, is fed into an input voltage connection 30 of the second level converter 75. Both level converters 70, 75 raise the input signals U.sub.EP and U.sub.EN each by the same value. By way of an output voltage connection 40 of the first level converter 70, a correspondingly level-shifted positive output signal U.sub.AP is emitted which corresponds to a negative output signal U.sub.AN of an output voltage connection 40 of the second level converter 75.