Solid state power controller

Abstract

A solid state power controller including: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3.sup.rd quadrant operation mode.

Claims

1. A solid state power controller comprising: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other; wherein the gate drive means causes the backwards-facing FETs to operate in 3.sup.rd quadrant operation mode.

2. The solid state power controller of claim 1 wherein pairs of FETs are connected via the drains of the FETs of the respective pairs.

3. The solid state power controller of claim 1, whereby the means for isolating the sources comprises a resistor between sources of respective FETs and the gate drive means.

4. The solid state power controller of claim 1, comprising an operational amplifier for controlling an on/off status of the FETs and for controlling the clamping voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Preferred embodiments will now be described, by way of example only, with reference to the drawings.

(2) FIG. 1 is a simplified circuit diagram of a standard, parallel FET, SSPC;

(3) FIG. 2 is a simplified circuit diagram of an SSPC according to the present invention.

DETAILED DESCRIPTION

(4) The standard SSPC has been described above, with reference to the invention.

(5) The reverse FET of the present SSPC (depends on the current direction) gives us the opportunity in SSPCs to use the reverse or backwards-facing FET as an adjustable source resistor if it is operating in its third quadrant.

(6) In order to prevent current imbalance because of the Vth variations, a feedback resistor (the already existing low, or backwards-facing side FET working in its third quadrant mode) is implemented for every FET between the FET's SOURCE potential and the LOAD output. This Resistor reduces the actual Vgs proportional to the current.

(7) If one transistor-resistor path is carrying more dI current than others, the gate voltage at this transistor will be reduced by the amount of dUcorrection:
dU correction=dI(Fet)*R(Resistor feedback)
U correction=I(Fet)*R(Resistance of feedback resistor)I(average/Fet)*R(Resistance of feedback resistor).

(8) Therefore the Fets n*SOURCEs cannot be directly connected, in order to enable individual current-to-voltage feedback from the implemented individual n*feedback resistors.

(9) This is done by separating the Fet n*SOURCEs from each other, and creating n*discrete sources.

(10) A virtual COMMON SOURCE is created only for the purpose of being able to use a single gate driver for all paralleled n*FETs.

(11) The discrete source potentials [n*] are connected via high impedance>1 Ohm [n*]resistors to the COMMON SOURCE.

(12) This does not corrupt the functionality of the [n*] source path resistors (SPICE parts M3-M5), as it is not attractive for a current dI to use a path>1 Ohm if a path with 25-80 mOhm is available.

(13) As can be seen in FIG. 2, the backwards FET (M3, M4 and M5) is used in the third quadrant operation mode. The 3rd quadrant control voltage is supplied by the gate driver.

(14) In one embodiment, an IC logic (FPGA) controls if the upper (forward) or the lower (backward) FET array is controlled for 3rd quadrant operation mode, depending on the sensed current flow direction at the beginning of a SSPC switch off operation.

(15) A non IC solution is also feasible, such as using NAND circuits to allow 3rd quadrant control for the FETs which do not get any voltage via the clamping diodes.

(16) It is preferred to apply the Vgs which results in the largest differential resistance. Of course the maximum possible absolute 3rd quadrant voltage drop Vsd is limited by the transfer function of the FET's inherent body diode.

(17) The maximum achievable differential resistance depends therefore on the device 3rd quadrant characteristic and mainly on the induced current level.

(18) Current feedback is thus performed by the backwards FETs working as emitter resistors for the other FETs working in linear mode (clamping) by raising their source potential compared to their gate potential. This is made possible by creating discrete sources for the backwards FETs e.g. using resistors for decoupling.

(19) The SSPC, therefore, enables current to be more evenly distributed between FETs when an inductive load is switched OFF.