Method and System for Evaluating an Input Voltage of a Power Supply

Abstract

Method and system for evaluating an input voltage of a power supply or a switched-mode power supply, wherein the input voltage has a constant polarity, where a digitized input voltage is supplied as the input signal to a filter which is filtered such that an output signal from the filter lags the input signal of the filter at the input of the filter, where the input signal and the output signal of the filter are compared, where comparison results are evaluated during an evaluation period until, following a first change in state of a comparison result, a further change in state of the comparison result is identified, and where a respective evaluation period is then terminated and subsequently, a period duration and/or a frequency of an AC voltage component of the input voltage are determined using the present count value of a counter.

Claims

1. A method for evaluating an input voltage of a switched-mode power supply, the input voltage having a predetermined polarity, the method comprising: sampling the input voltage at a predetermined sampling rate to create a digitized input voltage; filtering the digitized input voltage supplied as an input signal to a filter, such that an output signal from the filter lags the input signal of the filter; comparing, by a comparator, the input signal of the filter with the output signal from the filter; and evaluating comparison results delivered by the comparator; wherein, during a respective evaluation period which is started by resetting a counter, comparison results delivered by the comparator are evaluated until, subsequent to a first change in state of a comparison result, a further change in state of a comparison result is identified; and wherein a respective evaluation period is then terminated and, utilizing a present count value of the counter, at least one of a period duration and a frequency of an AC voltage component of the input voltage are determined.

2. The method as claimed in claim 1, wherein a sum value of the digitized input voltage added up over the respective evaluation period and the present count value at an end of the respective evaluation period are utilized to determine an average value of the input voltage.

3. The method as claimed in claim 1, wherein a minimum value and a maximum value of the digitized input voltage are detected during a respective evaluation period.

4. The method as claimed in claim 2, wherein a minimum value and a maximum value of the digitized input voltage are detected during a respective evaluation period.

5. The method as claimed in claim 1, wherein before sampling the input voltage is reduced to a voltage range suitable for signal processing.

6. The method as claimed in claim 1, wherein the comparator utilizes a hysteresis when comparing the input signal of the filter with the output signal from the filter.

7. The method as claimed in claim 1, wherein evaluation of the comparison result from the comparator is terminated when a predetermined maximum count value of the counter is reached.

8. The method as claimed in claim 1, wherein at least one of a noise reduction and noise suppression is performed after digitization of the input voltage.

9. A system for evaluating an input voltage of a switched-mode power supply, the input voltage having a predetermined polarity, the system comprising: an analog-to-digital converter for digitizing the input voltage, the input voltage being sampled at a predetermined sampling rate; at least one filter for filtering the digitized input voltage as the input signal, the at least one filter being formed such that an output signal from the at least one filter lags the digitized input signal of the at least one filter; a comparator for comparing the input signal of the at least one filter with the output signal from the at least one filter; a counter for measuring a respective evaluation period, the counter being reset at a start of the respective evaluation period; a sequence control system which is configured to: start a respective evaluation period by resetting at least the counter; evaluate comparison results delivered by the comparator until, subsequent to a first change in state of a comparison result, a further change in state of a comparison result being identified; terminate a respective evaluation period after the further change in the starting state of the comparator; and retrieve at least a present count value of the counter to determine the duration of at least one of a period and a frequency of an AC voltage component of the input voltage; and a timer which utilizes a clock signal to set a time control and the sampling rate of the analog-to-digital converter.

10. The system as claimed in claim 9, further comprising: an integrator for adding up the digitized input voltage over the respective evaluation period; wherein the integrator is resettable at the start of the respective evaluation period.

11. The system as claimed in claim 9, further comprising: a detector for detecting peak values of the digitized input voltage during the respective evaluation period; wherein the detector is resettable at the start of the respective evaluation period.

12. The system as claimed in claim 10, further comprising: a detector for detecting peak values of the digitized input voltage during the respective evaluation period; wherein the detector is resettable at the start of the respective evaluation period.

13. The system as claimed in claim 9, further comprising: a voltage divider arranged on an input side of the analog-to-digital converter, said voltage divider reducing the input voltage to a voltage range suitable for signal processing.

14. The system as claimed in claim 10, further comprising: a voltage divider arranged on an input side of the analog-to-digital converter, said voltage divider reducing the input voltage to a voltage range suitable for signal processing.

15. The system as claimed in claim 11, further comprising: a voltage divider arranged on an input side of the analog-to-digital converter, said voltage divider reducing the input voltage to a voltage range suitable for signal processing.

16. The system as claimed in claim 9, further comprising: a further filter arranged between an output of the analog-to-digital converter and an input of the filter.

17. The system as claimed in claim 10, further comprising: a further filter arranged between an output of the analog-to-digital converter and an input of the filter.

18. The system as claimed in claim 11, further comprising: a further filter arranged between an output of the analog-to-digital converter and an input of the filter.

19. The system as claimed in claim 13, further comprising: a further filter arranged between an output of the analog-to-digital converter and an input of the filter.

20. The system as claimed in claim 9, wherein the system is implemented aided by a microcontroller or a programmable logic circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The invention will be explained below by way of example, with reference to the attached figures, in which:

[0026] FIG. 1 shows, schematically and by way of example, an embodiment of the system for evaluating an input voltage of a switched-mode power supply in accordance with the invention;

[0027] FIG. 2a shows, schematically, an exemplary flowchart of the method for evaluating an input voltage of a switched-mode power supply in accordance with the invention;

[0028] FIG. 2b shows, schematically, an exemplary flow chart of an evaluation of comparison results from the comparator unit in accordance with the invention; and

[0029] FIG. 3 shows, schematically and by way of example, a further embodiment of the system for evaluating an input voltage of a switched-mode power supply in accordance with the invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0030] FIG. 1 shows an exemplary schematic block diagram of the system for evaluating an input voltage U.sub.rect of a switched-mode power supply, where the system has functional units that can be implemented as hardware and/or software units, where functional units of the system that are formed as software units may be implemented, for example, in a microcontroller. As an alternative, the system may be implemented at least with the aid of a programmable logic circuit.

[0031] Here, the switched-mode power supply is supplied, for example, by a supply voltage UN. The supply voltage UN may be, for example, a single-phase or three-phase line voltage from a power supply network. The supply voltage UN is fed to an input stage GL of the switched-mode power supply, where, for example, depending on the supply voltage UN, the input stage GL may be formed as a 2-pulse or 6-pulse rectifier unit GL. The rectifier unit GL rectifies the supply voltage UN and generates an input voltage U.sub.rect for the switched-mode power supply. The input voltage U.sub.rect, which is expressed in relation to a reference potential MP (e.g., 0 volts), has a defined or constant polarity. That is, the polarity does not change over the time characteristic of the input voltage U.sub.rect. The amplitude of the input voltage U.sub.rect does undergo a change over time, however, such as due to a “ripple” that is produced, for example, by rectification of the supply voltage UN by the rectifier unit GL.

[0032] The input voltage U.sub.rect of the switched-mode power supply is then fed to a voltage divider that comprises, for example, the resistors R1 and R2. This voltage divider puts the input voltage U.sub.rect which, for example, with a supply or line voltage UN of, for example, 400 volts is in the region of approximately 550 volts, into a voltage region (e.g., approximately 3 to 4 volts) that is useful for implementing the method in accordance with the invention or of which the signals can be processed. As a result of the voltage divider, or as a result of a relationship between the resistors R1 and R2, the input voltage U.sub.rect is reduced to an input voltage U.sub.r at a level that makes signal processing possible (e.g. 3.3 volts).

[0033] The reduced input voltage U.sub.r is fed to an analog-to-digital converter AD that digitizes or samples the reduced input voltage U.sub.r. The analog-to-digital converter AD may be formed, for example, as a separate component or can be integrated in the microcontroller via which the method in accordance with the invention is performed. Furthermore, for correct operation of the analog-to-digital converter AD, for example, it may be necessary to connect a capacitor, which for the sake of simplicity is not shown in FIG. 1, to an input of the analog-to-digital converter AD. Here, the capacitor should be selected such that, as far as possible, a signal shape of the input voltage U.sub.r is not affected. The analog-to-digital converter AD samples the analog input voltage U.sub.r at a sampling rate or sampling frequency. The analog-to-digital converter AD then delivers a sampled or digitized input voltage U.sub.r_dig, for example, in the form of a chronological string of sample values.

[0034] The sampling rate, or a clock for sampling the reduced input voltage U.sub.r, is delivered by an output signal or a clock signal CLK from a clock generator or timer unit TI. Thus, through its output signal or the clock signal CLK, the timer unit TI assumes time control of the analog-to-digital converter AD but also of the further functional units of the system in accordance with the invention. This means that the respective output signals of these functional units are always available at the clock rate CLK of the timer unit TI at the respective output of the functional unit. A frequency of the clock signal CLK is freely selectable (e.g., 10 kHz). However, because the clock signal CLK also forms the sampling rate of the analog-to-digital converter AD, it must be ensured that the sampling rate or sampling frequency and hence the clock signal CLK are substantially greater than an expected frequency of the AC voltage components or the ripple of the expected input voltage U.sub.rect or the reduced input voltage U.sub.r. Thus, the duration of a period of the sampling frequency is also significantly shorter (e.g. 100 μs) than that of the input voltage U.sub.rect of the switched-mode power supply or the reduced input voltage U.sub.r of overlaid ripples.

[0035] The digitized input voltage U.sub.r_dig is now fed to a filter unit PT. The filter unit PT is formed, for example, as a first-order digital low-pass filter unit that has an amplification P (e.g., P=1) and a time constant T. Here, the filter time constant T is, for example, greater than or at least equal to the duration of the period of the sampling rate CLK or that of the clock signal CLK. For example, the filter time constant T may be 4 times or ideally 16 times the duration of the period of the sampling rate or clock signal CLK. In this way, the filter unit PT has a filtering effect and a runtime for a filtered output signal U.sub.r_pt as a result of which, for example, the output signal U.sub.r_pt from the filter unit PT lags, or at least has a time delay in relation to, the input signal U.sub.r_dig of the filter unit PT. That is, the output signal U.sub.r_pt from the filter unit PT is based on a sample value of the digitized input voltage U.sub.r_dig that, in time terms, precedes a sample value of the digitized input voltage U.sub.r_dig that is applied as the input signal U.sub.r_dig of the filter unit PT at the input of the filter unit PT with the same clock signal CLK of the timer unit TI or with the same clock edge of the clock signal CLK.

[0036] The input signal U.sub.r_dig of the filter unit PT and the output signal U.sub.r_pt from the filter unit PT are then supplied to a comparator unit COMP. Depending on whether the input signal U.sub.r_dig of the filter unit PT is greater or smaller than the output signal U.sub.r_pt from the filter unit PT, a comparison result AW at the output of the comparator unit COMP may have a different value or state. Here, the comparison result AW may, for example, have a first value or state if the input signal U.sub.r_dig of the filter unit PT is smaller than the output signal U.sub.r_pt from the filter unit PT. If the input signal U.sub.r_dig of the filter unit PT is greater than the output signal U.sub.r_pt from the filter unit PT, then the comparison result AW at the output of the comparator unit COMP has a second value or state, for example.

[0037] The comparison comprising which of the two signals U.sub.r_dig, U.sub.r_pt of the filter unit PT is the greater and which the smaller can be performed by the comparator unit COMP, for example, with or without hysteresis H. When a hysteresis H is used in the evaluation, for example, any signal noise can reduce or prevent erroneous measurements. In this arrangement, depending on which comparison result AW applies or which value or state the comparison result AW has at the output of the comparator unit COMP, the hysteresis H may, for example, be added to the input signal U.sub.r_dig and the output signal U.sub.r_pt of the filter unit PT or subtracted from them. This brings about positive feedback, which makes the comparison result AW of the comparator unit COMP more stable.

[0038] The comparison result AW of the comparator unit COMP is forwarded to a sequence control system AS as the respectively present value or state at the output of the comparator unit COMP. The sequence control system controls a sequence of the evaluation of the input voltage U.sub.rect or the reduced input voltage U.sub.r, and can thus determine a duration of a respective evaluation period and, from this, a frequency of an AC voltage component or ripple overlaid on the input voltage U.sub.rect or U.sub.r. For this purpose, the sequence control system is formed, for example, as a “state machine”, which can move from a present, first state into a new, second state if there is a first change in the comparison result AW at the output of the comparator unit COMP, or if the value or state at the output of the comparator unit COMP changes for the first time. In the event of a further change in the comparison result AW at the output of the comparator unit COMP, the sequence control system AS can switch from the second state, through a third state or calculation state and a reset step, back to the first state. An exemplary detailed sequence of evaluation of the comparison results AW of the comparator unit COMP by the sequence control system AS is illustrated in FIG. 2b and, with reference to this, is described in more detail by way of example.

[0039] Furthermore, the sequence control system AS receives signals from a counter unit CO, an integrator unit INT and a detector unit DET, and these can be reset by a reset signal r, such as to start a respective evaluation period. Here, the counter unit CO counts the pulses of the clock signal CLK of the timer unit TI. At the start of the respective evaluation period, the counter unit CO can be started by the sequence control system AS, via the reset signal r. At the end of the respective evaluation period, the counter unit CO delivers a count value CO_W or count CO_W to the sequence control system AS, and a duration of the respective evaluation period can be derived from this count CO_W. The counter unit CO can be then reset again for a new evaluation period, via the reset signal r of the sequence control system AS.

[0040] The integrator unit INT adds up the signals or sample values of the digitized input voltage U.sub.r_dig over the respective evaluation period. At the end of the respective evaluation period, the integrator unit INT can provide the sequence control system AS with a sum value U.sub.r sum of the digital input voltage U.sub.r_dig, and the sequence control system AS can derive, for example, an average value of the input voltage U.sub.rect from this sum value U.sub.r_sum. The integrator unit INT can likewise be reset by the reset signal r at the start of each new evaluation period. The integrator unit INT is also clocked by the clock signal CLK of the timer unit TI.

[0041] During the respective evaluation period, a maximum value U.sub.r_max of the digitized input voltage U.sub.r_dig and a minimum value U.sub.r_min of the digitized input voltage U.sub.r_dig are detected by the detector unit DET. At the end of the respective evaluation period, these values U.sub.r_max, U.sub.r_min are provided to the sequence control system AS. The detector unit DET can likewise be reset by the reset signal r at the start of each new evaluation period. Moreover, the detector unit DET is also clocked by the clock signal CLK of the timer unit TI.

[0042] FIG. 2a shows, schematically and by way of example, a flowchart of the method for evaluating the input voltage U.sub.rect of a switched-mode power supply. Here, the input voltage U.sub.rect has a constant and defined polarity, but an amplitude that changes over time. Before a first step 101 of the method, a voltage divider R1, R2 can put the input voltage U.sub.rect into a voltage range that is suitable for signal processing by, for example, a microcontroller. The input voltage U.sub.rect of the switched-mode power supply is reduced, for example, to an input voltage U.sub.r.

[0043] In the first step 101, or in a digitization step 101, the reduced input voltage U.sub.r is converted into the digitized input voltage U.sub.r_dig by the analog-to-digital converter AD. For this purpose, the input voltage U.sub.r is sampled at a sampling rate or sampling frequency that is set, for example, by the clock signal CLK of the timer unit TI. The sampled or digitized input voltage U.sub.r_dig is then provided at the output of the analog-to-digital converter AD, for example, in the form of a chronological string of sample values.

[0044] The digitized input voltage U.sub.r_dig is then fed to the filter unit PT for filtering in a filtering step 102. The filter unit PT in this case is formed such that the output signal U.sub.r_pt from the filter unit PT is at least time-delayed in relation to the input signal that is formed by the digitized input voltage U.sub.r_dig. That is, the output signal U.sub.r_pt from the filter unit PT lags the input signal U.sub.r_dig of the filter unit PT and is based on a sample value of the digitized input voltage U.sub.r_dig that, in terms of time, precedes a sample value of the digitized input voltage U.sub.r_dig that is applied as the input signal at the input of the filter unit PT with the same clock signal CLK of the timer unit TI.

[0045] In a comparison step 103, the input signal U.sub.r_dig and the output signal U.sub.r_pt from the filter unit PT are fed to the comparator unit COMP and compared with one another. The comparison result AW at the output of the comparator unit COMP may, for example, have different values or states depending on whether the input signal U.sub.r_dig or the output signal U.sub.r_pt from the filter unit PT is the greater. The comparison result AW that is determined in the comparison step 103 is then forwarded to the sequence control system AS.

[0046] Next, in an evaluation step 104, the sequence control system AS evaluates the comparison result AW delivered by the comparator unit COMP. For the purpose of evaluating the comparison results AW delivered continuously by the comparator unit COMP, the sequence control system AS is formed, for example, as a state machine.

[0047] A flow chart of the evaluation, by the sequence control system AS, of comparison results delivered by the comparator unit COMP is illustrated schematically and by way of example in FIG. 2b.

[0048] For the purpose of starting an evaluation period, in a reset step 1041, the sequence control system AS uses the reset signal r to reset the counter unit CO to a starting value (e.g. the value 0). The counter unit CO counts the pulses of the clock signal CLK of the timer unit TI during the respective evaluation period. In addition, the integrator unit INT and the detector unit DET can be reset to respective starting values (e.g. the value 0), and hence adding up of the digitized input voltage U.sub.r_dig over the respective evaluation period and detection of the minimum and maximum value U.sub.r_min, U.sub.r_max of the digitized input voltage U.sub.r_dig during the respective evaluation period can be started. Then, the sequence control system AS performs a switch back to the first state, for example, after the reset step 1041.

[0049] In a first check step 1042, the sequence control system checks the comparison results AW that are continuously delivered by the comparator unit COMP for a first state change. That is, the sequence control system AS evaluates whether the value or state at the output of the comparator unit COMP changes. As long as an unchanged comparison result AW is delivered by the comparator unit COMP (e.g. the input signal U.sub.r_dig of the filter unit PT remains smaller than the output signal U.sub.r_pt, or the input signal U.sub.r_dig of the filter unit PT remains greater than the output signal U.sub.r_pt) and so a present value or state is maintained at the output of the comparator unit COMP, the sequence control system AS also remains in the first state and the first check step 1042 continues to be listed.

[0050] However, if, in the first check step 1042, a first change in the value or state at the output of the comparator unit COMP is identified, then the sequence control system AS switches from the first state to the second state, and a switch from the first check step 1042 to a second check step 1043 occurs. That is, if the comparison result AW at the output of the comparator unit COMP changes because, for example, the input signal U.sub.r_dig of the filter unit PT becomes greater than the output signal U.sub.r_pt or because the input signal U.sub.r_dig of the filter unit PT becomes smaller than the output signal U.sub.r_pt, then the present state of the sequence control system AS is also changed from the first to the second state.

[0051] In the second check step 1043, the comparison results AW that are continuously delivered by the comparator unit COMP are then checked again for a further change. As long as the sequence control system AS does not identify a change in state of the value or state at the output of the comparator unit COMP from the delivered comparison results AW, the sequence control system AS remains in the second state and the second check step 1043 continues to be performed. That is, as long as, for example, the input signal U.sub.r_dig of the filter unit PT remains greater than the output signal U.sub.r_pt from the filter unit PT, or the input signal U.sub.r_dig of the filter unit PT remains smaller than the output signal U.sub.r_pt, the sequence control system AS maintains the second state and waits until there is a further change in the comparison result AW.

[0052] If a further or a second change in the comparison result AW of the comparator unit COMP is identified in the second check step 1043, such as because the input signal U.sub.r_dig of the filter unit PT has become smaller than the output signal U.sub.r_pt from the filter unit PT again, or because the input signal U.sub.r_dig of the filter unit PT has become greater than the output signal U.sub.r_pt again, then the sequence control system switches to the third state, or the calculation state, in which a calculation step 1044 is then performed.

[0053] In the calculation step 1044, the respective evaluation period is then terminated, and the sequence control system AS retrieves a present count value CO_W from the counter unit CO. Furthermore, the present sum value U.sub.r_sum from the integrator unit INT, and a minimum value U.sub.r_min and a maximum value U.sub.r_max of the digitized input voltage U.sub.r_dig that have been identified by the detector unit DET during the respective evaluation period can also be transmitted to the sequence control system AS.

[0054] Furthermore, in the calculation step 1044, it is possible to derive from the count value CO_W that is retrieved for the respective evaluation period, from the frequency of the clock signal CLK, and from the sum value U.sub.r_sum of the digitized input voltage U.sub.r_dig that is transmitted for the respective evaluation period, a frequency of the AC voltage component and an average value of the input voltage U.sub.rect. For the purpose of determining the frequency of the AC voltage component of the input voltage U.sub.rect, for example, the frequency of the clock signal CLK is divided by the count value CO_W that has been determined for the respective evaluation period. For the purpose of determining the average value of the input voltage U.sub.rect, it is possible, for example, to divide the sum value U.sub.r_sum of the digitized input voltage U.sub.r_dig that has been determined over the respective evaluation period by the count value CO_W determined for the respective evaluation period.

[0055] After the calculation step 1044, the reset step 1041 is performed again. In so doing, the counter unit CO, the integrator unit INT and the detector unit DET can be reset to the respective starting values again for a subsequent evaluation period by the sequence control system AS, via the reset signal r. With the reset step 1041, the next evaluation period is started and the sequence control system has the first state again, in order once more to evaluate for example further comparison results AW of the comparator unit COMP via the first and second check steps 1042, 1043.

[0056] If no change in the comparison result AW of the comparator unit COMP is identified, for example, during the first check step 1042 and/or the second check step 1043, then the method can be terminated if the value of the counter unit CO reaches or exceeds a predetermined count value. That is, the ongoing evaluation period is terminated or aborted upon reaching or exceeding the predetermined count value. Here, for example, the sequence control system AS can be put in the first state again, and the counter unit CO, the integrator unit INT and the detector unit DET can be reset to the respective predetermined starting values.

[0057] FIG. 3 shows a further embodiment of the system in accordance with the invention for evaluating an input voltage U.sub.rect of a switched-mode power supply via which the method in accordance with the invention can be implement. Here, once again the input voltage U.sub.rect of the switched-mode power supply is reduced by the voltage divider R1, R2 to an input voltage U.sub.r of a size suitable for signal processing (e.g., 3.3 volts). The reduced input voltage U.sub.r is once again fed to the analog-to-digital converter AD, by which the reduced input voltage U.sub.r is digitized using the sampling signal or clock signal CLK of the timer unit TI. Next, in contrast to the embodiment illustrated in FIG. 1, the digitized input voltage U.sub.r_dig is first fed to a further filter unit PT1 of which the input side is connected to the analog-to-digital converter AD. At its output side, there is connected to the further filter unit PT1 the filter unit PT, with the output signal U.sub.r_pt1 from the further filter unit PT1 now forming the input signal of the filter unit PT. The further filter unit PT1 primarily serves to suppress or reduce noise in the digitized input voltage U.sub.r_dig. The further filter unit PT1 may, for example, likewise be formed as a first-order low-pass filter and can have an amplification P (e.g., P=1). Furthermore, the further filter unit PT1 has a filter time constant T that is, for example, greater than or equal to the duration of the period of the sampling rate CLK or of the clock signal CLK.

[0058] For the purpose of making a comparison, the comparator unit COMP is then supplied with the output signal U.sub.r_pt1 from the further filter unit PT1, which now forms the input signal of the filter unit PT, and the output signal U.sub.r_pt from the filter unit PT. Once again, the two signals U.sub.r_pt1, U.sub.r_pt can then be compared with one another with or without hysteresis H.

[0059] Once again, the comparator unit COMP then delivers comparison results AW to the sequence control system AS, which then once again controls the evaluation of the comparison results, as described with reference to FIG. 2b. The embodiment illustrated in FIG. 3 also has the counter unit CO, the integrator unit INT and the detector unit DET, which can likewise be clocked using the clock signal CLK from the timer unit TI and reset by the sequence control system AS, via the reset signal r. However, in the embodiment illustrated in FIG. 3, the input signal there is supplied to the integrator unit INT and the detector unit DET digitized input voltage U.sub.r_pt1 that has been filtered by the further filter unit PT1, in order to obtain better output values U.sub.r_sum, U.sub.r_min, U.sub.r_max at the end of the respective evaluation period.

[0060] Thus, while there have been shown, described and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the methods described and the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements and/or method steps which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements and/or method steps shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.