PHOTOACTIVE SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A PHOTOACTIVE SEMICONDUCTOR COMPONENT

Abstract

The invention relates to a photoactive semiconductor component, especially a photovoltaic solar cell, having a semiconductor substrate, a carbon-containing SiC layer disposed indirectly upon a surface of the semiconductor substrate, and a passivating intermediate layer disposed indirectly or directly between the SiC layer and semiconductor substrate, and a metallic contact connection disposed indirectly or directly upon a side of the SiC layer facing away from the passivating intermediate layer and in electrically conductive connection with the SiC layer, where the SiC layer has p-type or n-type doping, which is characterized in that the SiC layer partly has a partly amorphous structure and partly has a crystalline structure.

Claims

1. A photoactive semiconductor component, comprising a semiconductor substrate, a SiC layer containing carbon and arranged indirectly on a surface of the semiconductor substrate, a passivating intermediate layer indirectly or directly arranged between the SiC layer and the semiconductor substrate, and a metallic contacting, which is arranged indirectly or directly on a side of the SiC layer facing away from the passivating intermediate layer and connected to the SiC layer in an electrically conductive fashion, the SiC layer exhibiting a p-type or n-type doping, and the SiC layer comprises partially an amorphous structure and partially a crystalline structure.

2. The semiconductor component according to claim 1, wherein an amorphous volume of the SiC layer ranges from 20% to 80%, of a total volume of the SiC layer, and a non-amorphous volume of the SiC layer essentially exhibits a crystalline structure.

3. The semiconductor component according to claim 1, wherein the SiC layer exhibits a carbon content of less than 25 atom percent.

4. The semiconductor component according to claim 1, wherein the semiconductor substrate is embodied as a base with a base doping and the SiC layer is embodied as an emitter with a doping type opposite the base doping, or the semiconductor substrate is embodied with a base with a base doping and the SiC layer is embodied as a BSF layer by the SiC layer exhibiting a doping of the base doping type.

5. The semiconductor component according to claim 1, wherein the semiconductor substrate exhibits a doping at a side facing the passivating intermediate layer with a same doping substance of the SiC layer.

6. The semiconductor component according to claim 1, wherein a second SiC layer is arranged indirectly at a side of the semiconductor substrate facing away from the SiC layer and a second passivating intermediate layer is arranged indirectly or directly between the semiconductor substrate and the second SiC layer, with the second SiC layer having a higher amorphous volume ratio in reference to the first SiC layer.

7. The semiconductor component according to claim 1, wherein the SiC layer has a thickness below 30 nm.

8. A semiconductor component according to claim 1, wherein the passivating intermediate layer has a thickness ranging from 1 nm to 5 nm.

9. The semiconductor component according to claim 1, wherein the semiconductor component is embodied as a photovoltaic solar cell.

10. A method for the production of a selective contact of a photoactive semiconductor component, comprising the following processing steps: A providing a semiconductor substrate; B arranging a passivating intermediate layer indirectly or directly on a surface of the semiconductor substrate; C arranging a carbon containing, doped SiC layer indirectly or directly on the passivating intermediate layer, and D arranging a metallic contacting structure indirectly or directly on a side of the SiC layer facing away from the passivating intermediate layer, and the SiC layer is partially embodied as an amorphous structure and partially as a crystalline structure.

11. The method for producing a selective contact of a photoactive semiconductor component according to claim 10, wherein the SiC layer is applied as an amorphous layer and subsequently only partially crystallized.

12. The method for producing a selective contact of a photoactive semiconductor component according to claim 10, the SiC layer is crystallized using heat.

13. The method for producing a selective contact of a photoactive semiconductor component according to claim 10, wherein a polycrystalline silicon layer is arranged indirectly or directly between the passivating intermediate layer and the SiC layer.

14. The method for generating a selective contact of a photoactive semiconductor component according to claim 10, wherein the passivating intermediate layer comprises one or more of the layers SiO.sub.x, Al.sub.2O.sub.3, HfAlO.sub.x, HfSiO.sub.x.

15. The method for generating a selective contact of a photoactive semiconductor component according to claim 10, wherein the SiC layer is precipitated via PECVD.

16. The semiconductor component according to claim 3, wherein at least the silicon range of the SiC layer in which no carbon is bonded exhibits both amorphous as well as crystalline structures.

17. The method for producing a selective contact of a photoactive semiconductor component according to claim 12, wherein at least the SiC layer is heated to a temperature above 800 C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In the following, additional preferred features and embodiments are described based on exemplary embodiments and the figures. Here are shown:

[0063] FIGS. 1A to C a first exemplary embodiment of a method according to the invention;

[0064] FIGS. 2A to C a second exemplary embodiment of a method according to the invention, and

[0065] FIGS. 3A to D a third exemplary embodiment of a method according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] All figures show schematic cross-sections of a semiconductor component, not to scale, and/or a precursor thereof during the production. Identical reference characters mark the same elements or those with identical effects.

First Exemplary Embodiment

[0067] In the first exemplary embodiment of the method according to the invention, shown in FIGS. 1A to C, according to FIG. 1A, a passivating intermediate layer 2, embodied as a tunnel layer, is applied upon a semiconductor substrate 1, embodied as a silicon substrate. The semiconductor substrate 1 is embodied as a monocrystalline silicon wafer. The tunnel layer exhibits a thickness ranging from 5 Angstrom to 50 Angstrom, in the present case 10 Angstrom. It is embodied as a silicon dioxide layer. The tunnel layer may also be embodied as a different oxide. The silicon substrate is embodied as a monocrystalline silicon waver and exhibits in the present case a boron-base doping (p-type) ranging from 10.sup.14 cm.sup.3 to 10.sup.17 cm.sup.3, in the present case amounting to 1.510.sup.16 cm.sup.3.

[0068] The tunnel layer is applied via wet-chemical growth. Additionally, the tunnel layer may be deposited via RTO (rapid thermal oxidation), ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or APCVD (atmospheric pressure chemical vapor deposition).

[0069] FIG. 1A shows therefore the status after the execution of exemplary embodiments of the above-mentioned processing steps A and B, in which the tunnel layer was applied directly upon the rear of the semiconductor substrate 1 (shown in FIGS. 1 to 3 respectively laying at the bottom).

[0070] In another processing step according to FIG. 1B, a doped amorphous SiC layer 3 is applied (here boron-doped). The carbon portion ranges from approx. 5% to 25%, the present case amounting to approx. 20%.

[0071] The thickness of the layer 3 ranges from 5 nm to 30 nm, in the present case amounting to approximately 15 nm. The layer 3 is applied via PECVD. The application of the layers 3 and 4 via LPCVD or APCVD or sputtering is also within the scope of the invention.

[0072] The doping of the boron-doped layer ranges here from 10.sup.18 cm.sup.3 to 10.sup.21 cm.sup.3.

[0073] FIG. 1B shows therefore the status after execution of an exemplary embodiment of the above-mentioned processing step C, in which the doped SiC-layer 3 was applied directly on the tunnel layer 2.

[0074] Subsequently, in another processing step (not shown) the solar cell is heated. This way an activation of the doping and partial crystallization of the amorphous SiC layer 3 is yielded. The heating therefore represents a high temperature step, known per se, preferably with temperatures ranging from 600 C. to 950 C., in the present case 800 C.-900 C. The high temperature step is performed via oven tempering. The high temperature step may also be performed via RTP (rapid thermal processing), or by a laser.

[0075] The degree of crystallization of the layers can here he controlled by the selected temperature budget and the carbon content in the SiC layer 3. After the heating process the amorphous rate in the overall volume of the layer should amount to at least 20%, preferably >30%, in the present case approximately 40%, in order to ensure improved selectivity due to the increased band gap of a-Si compared to c-Si.

[0076] Additionally, during this high-temperature step in an advantageous further development of the exemplary embodiment the doping substance may diffuse from the layer 3 into the substrate in a section 4 such that a shift of the p-n transition and/or the high-low junction (which allows BSF) into the absorber can occur (see FIG. 1C). The exemplary embodiment shown here represents the shift of the high-low junction.

[0077] Subsequently (not shown) metallic contact structures are applied on the SiC layer 3, which are connected to the SiC layer 3 in an electrically conductive fashion.

[0078] FIG. 1C shows therefore an exemplary embodiment of a semiconductor component according to the invention, with the above-mentioned metallic contacts not being illustrated. In order to finish the semiconductor components as photovoltaic solar cell or LED, additional elements may be added, particularly emitter diffusion (in the present case a n-type, for example using phosphor as the doping substance) at the front of the semiconductor substrate.

[0079] In order to avoid repetitions, in the following exemplary embodiments essentially the differences are described.

Second Exemplary Embodiment

[0080] In the second exemplary embodiment of a method according to the invention shown in FIGS. 2A to C, a passivating intermediate layer 2, 2 is applied according to FIG. 2A, as a tunnel layer onto a semiconductor substrate 1 embodied as a silicon substrate, at both sides. The semiconductor substrate 1 is embodied as a monocrystalline silicon wafer. The tunnel layer exhibits a thickness ranging from 5 Angstrom to 50 Angstrom, in the present case 10 Angstrom. It is embodied as a silicon dioxide layer. The tunnel layer may also be embodied as a different oxide.

[0081] The tunnel layer is applied via wet-chemical growth. The tunnel layer may also be deposited via RTO (rapid thermal oxidation), ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or APCVD (atmospheric pressure chemical vapor deposition).

[0082] In another processing step according to FIG. 2B, a boron-doped amorphous first SiC layer 3 is applied and a phosphor-doped amorphous second SiC layer 3 (at the front, shown at the top).

[0083] The carbon ratio of both layers ranges from approx. 5% to 25%, amounting in the present case to approx. 15%. The thickness of the layers 3 and 3 ranges from 5 nm to 30 nm, amounting in the present case to approx. 15 nm. The layers are applied via PECVD. Additionally, the scope of the invention includes the application of the layers 3 and 3 via LPCVD or APCVD or sputtering.

[0084] The doping of the n-doped layer 3 ranges here from 10.sup.18 cm.sup.3 to 10.sup.21 cm.sup.3. The same also applies to the p-doped layer 3.

[0085] FIG. 1B shows therefore the status at which the two doped SiC layers 3 and 3 were directly applied on the respective tunnel layer 2.

[0086] Subsequently heating of the solar cell occurs (not shown) in another processing step. This way an activation of the doping and partial crystallization of the amorphous SiC layers 3 and 3 is yielded. The heating represents therefore a high-temperature step known per se, preferably with temperatures at a range 600-950 C., preferably 800-900 C. The high-temperature step is performed via the temperature control of the oven. The high-temperature step can also occur via RTP (rapid thermal processing) or by a laser. The degree of crystallization of the layers may here be controlled by the selected temperature budget and the carbon content in the respective layers 3 and 4. Preferably the layer exhibits at the side facing the light a higher crystalline silicon ratio than the layer at the side facing away from the light. This is caused in the lower absorption coefficient of c-Si compared to a-Si.

[0087] The respective amorphous rate in reference to the total volume of both layers should preferably be at least 20%, preferably >30%, in the present case approx. 50%, in order to ensure improved selectivity based on the increased band gap of a-Si compared to c-Si.

[0088] Additionally, during this high-temperature step the doping substance can diffuse into the layers 3 and 3 and into the semiconductor substrate (absorber) such that a shift may occur of the p-n transition into the absorber, similar to the one described in FIG. 1C.

[0089] In another processing step according to FIG. 2C, a TCO-layer 5 is applied. This TCO-layer serves to generate the lateral conductivity and to improve the coupling of incident light. This layer 5 may be embodied as ITO, AZO, IO:H, and exhibits a thickness of approx. 70 nm.

[0090] Subsequently, at the front a metallic layer 6 is applied in the form of a contacting grid (metallic contacting structure) for example via serigraphy. At the rear, a metallic layer 7 is applied, preferably Ag, over the entire area.

[0091] FIG. 2C therefore represents a second exemplary embodiment of a semiconductor component according to the invention.

Third Exemplary Embodiment

[0092] In the exemplary embodiment shown in FIGS. 3A to D which show a method according to the invention, according to FIG. 3A, a tunnel layer 2 is applied at both sides on a semiconductor substrate 1 embodied as a silicon substrate. The semiconductor substrate 1 is embodied as a monocrystalline silicon wafer. The tunnel layer 2 exhibits respectively a thickness ranging from 5 Angstrom to 50 Angstrom, in the present case 10 Angstrom. It is embodied as a silicon dioxide layer. The tunnel layer may also be embodied as a different oxide.

[0093] The tunnel layer is applied via wet-chemical growth. The tunnel layer may also be deposited via RTO (rapid thermal oxidation), ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or APCVD (atmospheric pressure chemical vapor deposition).

[0094] In another processing step according to FIG. 3B, at both sides an un-doped polycrystalline Si-layer (9 and 9) is applied. The thickness of this layer ranges respectively from 5 nm to 20 nm, amounting in the present case to approx. 5 nm. The layers 9, 9 are preferably applied via LPCVD. A deposition via APCVD is also within the range of the invention.

[0095] In another processing step according to FIG. 3C, a boron-doped amorphous SiC-layer 3 and a phosphor-doped amorphous SiC-layer 3 is applied. The carbon atom ratio ranges respectively from approx. 5% to 25%, in the present case amounting to approx. 15%.

[0096] The thickness of the layers 3 and 3 ranges from 5 nm to 30 nm, amounting in the present case to approx. 15 nm. The application occurs via PECVD. Similarly, the application of the layers 3 and 3 via LPCVD or APCVD or sputtering is within the scope of the invention as well. The doping of the n-doped layer ranges here from 10.sup.18 cm.sup.3 to 10.sup.21 cm.sup.3. The same also applies to the p-doped layer.

[0097] Subsequently in another processing step the solar cell is heated (not shown). This way an activation of the doping and partially the crystallization of the amorphous SiC layers 3 and 3 is yielded. The heating therefore represents a high-temperature step known per se, preferably with temperatures ranging from 600 to 950 C., in the present case 800-900 C. The high-temperature step is performed via temperature control of the oven. The high temperature step can also occur via RTP (rapid thermal processing) or by a laser. The degree of crystallization of the layers can here be controlled by the selected temperature budget and the carbon content in the respective layers 3 and 3. Preferably the layer exhibits at the side facing the light a higher crystalline silicon rate than the layer on the side facing away from the light. This is caused by the lower absorption coefficient of c-Si compared to a-SI. The respective amorphous rate refers to the total volume of both layers should preferably amount to at least 20%, preferably >30%, and amounts preferably to approx. 50% in order to ensure improved selectivity based on the increased band gap of a-Si compared to c-Si.

[0098] Additionally during this high-temperature step the doping substance of the layer 3 and 3 can diffuse into the polycrystalline Si-layer 9 and 9. The advantage of inserting a poly-Si intermediate layer is caused in the different thermal expansion coefficients of Si and SiC. This way, excessive generation of layer tension is prevented by the poly-Si layer, which can have negative effects upon the boundary passivation.

[0099] In another processing step according to FIG. 3D, a TCO-layer 6 is applied. This TCO-layer serves for generating lateral conductivity as well as better coupling of the incident light. This layer 6 can be embodied as ITO, AZO, IOH and exhibits a thickness of approx. 70 nm.

[0100] Subsequently, a metallic contacting 6 is applied at the front in the form of a contacting grid, for example via serigraphy. At the rear, a metallic layer 7 is applied, preferably Ag, over the entire surface.

[0101] FIG. 3D therefore represents a third exemplary embodiment of a semiconductor component according to the invention.