Control of cross-over point

Abstract

There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.

Claims

1. An output stage of an amplifier, comprising: a DC offset signal generator; a phase splitter; an adder having a first input coupled to an output of the DC offset signal generator and having a second input coupled to a first output of the phase splitter; a subtractor having a first input coupled to the output of the DC offset signal generator and having a second input coupled to a second output of the phase splitter; a first transistor having a gate coupled to an output of the adder and having a drain coupled to a first power supply rail; and a second transistor having a gate coupled to an output of the subtractor and having a drain coupled to a second power supply rail.

2. The output stage of claim 1, wherein the DC offset signal generator is configured to generate a signal that equalizes the power dissipated in the first and second transistors.

3. The output stage of claim 1, wherein a source of the first transistor is coupled to a source of the second transistor.

4. The output stage of claim 3, further comprising: a transformer; and a second subtractor having a first input coupled to an output of an envelope detector and having a second input coupled to an output of the transformer, wherein an output of the second subtractor is coupled to an input of the phase splitter.

5. The output stage of claim 1, further comprising: a first measurement block having a first input coupled to the first power supply rail and having a second input coupled to the drain of the first transistor; and a second measurement block having a first input coupled to the second power supply rail and having a second input coupled to the drain of the second transistor.

6. The output stage of claim 5, further comprising: a second subtractor having a first input coupled to an output of the first measurement block and having a second input coupled to an output of the second measurement block.

7. The output stage of claim 6, wherein an input of the DC offset signal generator is coupled to an output of the second subtractor.

8. The output stage of claim 7, wherein the DC offset signal generator comprises an integrator, wherein an input of the integrator is coupled to the output of the second subtractor.

9. An envelope tracking power supply comprising the output stage according to claim 1.

10. The envelope tracking power supply of claim 9, further comprising: an envelope detector having an output coupled to an input of the phase splitter.

11. The envelope tracking power supply of claim 10, further comprising: a switched mode power supply having an input coupled to the output of the envelope detector.

12. The envelope tracking power supply of claim 11, further comprising a transformer, the transformer comprising: a first primary winding coupled between a drain of the first transistor and the first power supply rail; a second primary winding coupled between a drain of the second transistor and the second power supply rail; and a secondary winding coupled to an output of the switched mode power supply.

13. A method of generating an output signal in a push-pull amplifier output stage comprising: sourcing a first current to a node via a first transistor of a push-pull amplifier; sinking a second current from the node via a second transistor of the push-pull amplifier; and modifying a crossover point between the sourcing of the first current and the sinking of the second current in dependence on a supply voltage in order to control the power dissipated in the first and second transistors.

14. The method of claim 13 further comprising: offsetting the first current sourced to the node by an amount in a first direction; and offsetting the second current sunk from the node by the same amount in the opposite direction from the first direction.

15. The method of claim 14, further comprising: generating a DC offset signal; adding the DC offset signal to an input to the first transistor; and subtracting the DC offset signal from an input to the second transistor.

16. The method of claim 15, further comprising: measuring the power dissipated in the transistors; determining the difference between the measurements; and generating the DC offset signal in dependence on the difference.

17. The method of claim 13, wherein the modifying reduces the power dissipated in the first and second transistors.

18. The method of claim 13, further comprising combining output signals of the first and second transistors to generate the output signal in the push-pull amplifier output stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is now described by way of example with reference to the accompanying drawings in which:

(2) FIG. 1 illustrates an output stage in accordance with the prior art;

(3) FIG. 2 illustrates a non-symmetric drive signal for the output stage of FIG. 1;

(4) FIG. 3 illustrates the distribution of power dissipated in the two halves of an output stage in accordance with the location of a crossover or slicing point;

(5) FIGS. 4a to 4d illustrate the currents and voltages in the output stage in the prior art arrangement of FIG. 1, in handling a symmetrical drive signal;

(6) FIGS. 5a to 5d illustrate the voltages and currents in an output stage in dependence on a symmetric input in accordance with the invention;

(7) FIGS. 6a and 6b illustrate the voltages and currents in an output stage for a non-symmetric input in accordance with the invention;

(8) FIG. 7 illustrates an output stage adapted in accordance with an embodiment of the invention;

(9) FIGS. 8a and 8b illustrate the implementation of parts of the output stage of FIG. 7 in accordance with embodiments of the invention; and

(10) FIG. 9 illustrates an exemplary implementation of an output stage in accordance with the invention in an envelope tracking modulated power supply for an RF amplifier.

DETAILED DESCRIPTION

(11) The invention is described herein by way of reference to exemplary embodiments, and in particular exemplary embodiments which are chosen for their suitability in presenting a clear explanation of the invention. One skilled in the art will appreciate that the invention is not limited to the details of any described example implementation, and the invention may be more broadly applied than the embodiments described herein. In particular the invention may be applied in various implementations beyond implementations discussed herein.

(12) With reference to FIGS. 4a to 4d, there is illustrated the voltages and currents in the output stage transistors 12 and 14 of FIG. 1 in a typical operation. The invention is particularly applicable to arrangements which are required to handle a drive signal which is asymmetric. However the invention may also be used in implementations where the drive signal is symmetric. For the purposes of discussing the currents and voltages in the prior art arrangement of FIG. 1, in FIGS. 4a to 4d an example is discussed in which the drive signal provided on line 16 is a symmetric signal, in order to simplify the explanation. More particularly, the typical operation described for the purposes of example is an idealised Class B operation, in which each active element works in its linear range half of the time and in the other half of the time is turned off. In a typical Class B arrangement, there are two output devices each of which conducts for exactly half a cycle (180) of the input signal. In the example of FIG. 1, the transistors 12 and 14 are such active devices.

(13) With reference to FIG. 4a, there is illustrated the voltages in the upper and lower half of the output stage. The voltage V.sub.A denoted by reference numeral 42 represents the voltage supplied on signal line 18 to the transistor 12 with respect to the threshold voltage of the transistor 12, and the voltage V.sub.B denoted by reference numeral 44 represents the voltage delivered on signal line 20 to the transistor 14 with respect to the threshold voltage of the transistor 14. Thus the horizontal dashed line in FIG. 4(a) represents the point at which the transistors 12 and 14 turn on/off as the input waveform crosses it. The waveforms 42 and 44 represent opposite phases of the same signal, and are the waveforms generated as a result of the operation of the phase splitter 10.

(14) With reference to FIG. 4b, there is illustrated the current in the upper half of the output stage. As illustrated in FIG. 4b, a current, as denoted by waveform 46, is present only when the waveform voltage 42 is positive.

(15) FIG. 4c represents the current in the lower half of the output stage of FIG. 1. As illustrated in FIG. 4c a current as represented by waveform 48 is only present when the waveform 44 is positive.

(16) The waveform of FIG. 4d illustrates the combined current in the upper and lower halves of the output stage, i.e. the combination of the currents shown in FIGS. 4b and 4c, which is the same in each time period as a result of the symmetrical nature of the arrangement. The symmetrical nature of the arrangement means that each transistor is switched on for an equal amount of time T.

(17) FIGS. 4a to 4d represent the case when an idealised symmetric signal is provided as the drive signal for a Class B arrangement, and as such the power in the output stage is equally distributed between the upper half and lower half of the output stage. The slicing voltage for the waveforms of FIGS. 4a to 4d is the slicing voltage V.sub.SLICE.sub._.sub.MIN of FIG. 3, in the position represented by the line 40 of FIG. 3.

(18) FIGS. 5a and 5b illustrate the adaptation of the waveforms of FIGS. 4a to 4d in accordance with the principles of an embodiment of the present invention.

(19) In accordance with the principles of the invention, a DC offset is added to the voltages at the inputs to the respective transistors 12 and 14, in order to offset the position of the voltage waveforms 42 and 44 of FIG. 4a. As will be explained further hereinbelow, the addition of the offsets to these voltages has the functional effect of controlling the effective position of the slicing voltage V.sub.SLICE to ensure that the dissipated power is reduced, and as best as possible minimised.

(20) As illustrated in FIG. 5a, the voltage waveform V.sub.A denoted by reference numeral 50, is positively offset by an amount V.sub.OFF as indicated by the upward arrow denoted by reference numeral 54.

(21) As illustrated by FIG. 5b, the voltage waveform V.sub.B of the lower half of the output stage is negatively offset by the same offset voltage V.sub.OFF, as indicated by the downward arrow denoted by reference numeral 56.

(22) FIG. 5c illustrates the overall effect of the offsets applied to the voltage waveforms, in direct comparison to the voltage waveforms of FIG. 3a.

(23) As can be seen in FIG. 5a, the waveform V.sub.A has moved up, and the waveform V.sub.B has moved down, such that the crossover point at which the two waveforms V.sub.A and V.sub.B cross over is adjusted. As a result of the adjustment in the voltages, the upper transistor 24 is on for a time T.sub.1, where T.sub.1>T. The lower transistor 14 is on for a time T.sub.2, where T.sub.2<T.

(24) Turning to FIG. 5d, it can then be seen that the current provided by the two halves of the output stage thus differs. In the time period T.sub.1, the current I.sub.A is denoted by waveform 58 in the upper output stage. In the time period T.sub.2, the current I.sub.B of the lower half of the output stage is denoted by waveform 60. As can be seen, the current drawn by the upper output stage is higher than that drawn by the lower output stage, and current is drawn by the upper half of the output stage for a longer period of time than it is drawn by the lower half of the output stage.

(25) The addition of equal and opposite DC offsets to the upper and the lower halves of the output stage drive voltages, is functionally equivalent to moving the crossover point or slicing voltage denoted by reference numeral 30 in FIG. 2. As a consequence of this effective adjustment of the slicing voltage the power dissipation in transistor 12 is increased and the power dissipation in transistor 14 is decreased.

(26) The discussion with respect to FIGS. 4a to 4d and 5a to 5d represents the case where the drive input is a symmetric waveform. As noted, the invention is most usefully applicable in arrangements where the drive signal is asymmetric. In such an arrangement and with reference to FIG. 5d, each time period in which the upper transistor 12 is on will be duration T1 (i.e. T3=T1), and each time period in which the lower transistor 14 is on will be equal to time T2 (i.e. T4=T2).

(27) FIG. 6a illustrates a waveform 70 having an asymmetric amplitude distribution. FIG. 6b illustrates the corresponding current drawn in the upper and lower halves of the output stage as the waveform 70 of FIG. 6a crosses the crossover point or slicing point denoted by horizontal line 71. By applying an appropriate DC offset to the waveform, the current drawn in each half of the output stage, and consequently the power dissipated in each half of the output stage, can be controlled in accordance with the principle described with reference to FIGS. 5a to 5d.

(28) With reference to FIG. 7, there is illustrated a modification to the output stage arrangement of FIG. 1 in a preferred embodiment of the invention, in order to achieve the beneficial effects of the invention as described herein. Where reference numerals in FIG. 7 correspond to reference numerals in FIG. 1, they denote elements which correspond to elements of FIG. 1.

(29) The output stage arrangement of FIG. 1 is adapted, with reference to FIG. 7, to include an adder 84, a subtractor 86, power measurement stages 92 and 94, a subtractor 90, and an error integrator 88.

(30) The outputs of the phase splitter 10 of FIG. 1, on lines 18 and 20 respectively, form first inputs to the respective adder and subtractor, 84 and 86. The outputs of the respective adder and subtractor 84 and 86 on lines 80 and respectively form the inputs to the control nodes, or gates, of the transistors 12 and 14.

(31) The power measurement stage 92 receives as its inputs the high voltage supply V.sub.H and the current flowing in transistor 12, as detected by current sense node 93 and delivered on signal line 95. Similarly power measurement stage 94 receives as its inputs the low voltage supply V.sub.L and the current flowing in transistor 14, as detected by current sense node 97 and delivered on signal line 99. The current flowing in the transistors 12 and 14 may be sensed in either their drain or their source (or collector/emitter for bipolar devices), and is shown as being sensed in the drains in FIG. 7 by way of example only.

(32) Each of the power measurement stages 92 and 95 are arranged to provide on their respective outputs, on lines 93 and 95, signals representative of the average power delivered from the respective high and low voltage supply rails. The power delivered from the supply rails is a proxy for the power dissipated in the output transistors 12 and 14. The power is measured, rather than just measuring current, because the supply voltages are in general not equal to one another.

(33) The voltages representing the output powers on lines 93 and 95 are provided as inputs to the subtractor 90, which provides an error signal on its output representing the difference in power dissipated in transistors 12 and 14 (one power measurement output is subtracted from the other).

(34) This error signal is integrated in the error integrator 88. The error integrator 88 receives the error signal from subtractor 90 as one input and electrical ground as another input. The error integrator 88 compares the error value with zero (electrical ground) and integrates the difference.

(35) The integrated error signal provided by the error integrator 88 is provided as an input to the adder 84 and the subtractor 86. The adder 84 also receives as an input the drive signal for the transistor 12. The subtractor 86 also receives as an input the drive signal for the transistor 14. Thus the error signal is added to the drive signal on line 18 and subtracted from the drive signal on line 20, to provide an offset drive signal voltage on line 80 for transistor 12, and an offset drive signal voltage on line 82 for transistor 14.

(36) The arrangement shown in FIG. 7 therefore implements a closed loop control system which equalises the power dissipated in transistors 12 and 14. This is an adaptive arrangement, such that the offset is dynamically adjusted in dependence on the average power dissipated in transistors 12 and 14.

(37) With reference to FIG. 8, there is illustrated an exemplary implementation of the power measurement circuits 92 and 94 of FIG. 7. FIG. 8a illustrates the power measurement circuit 92 and FIG. 8b illustrates the power measurement circuit 94. The power measurement circuits of FIG. 8a and FIG. 8b are constructed identically.

(38) As illustrated, each of the power measurement circuits 92 and 94 includes a sense resistor, 96.sub.H and 96.sub.L, having one terminal connected to the respective supply voltage V.sub.H and V.sub.L, and the other terminal connected to respectively the drain of the transistor 12 and the drain of the transistor 14. A voltage amplifier, respectively denoted by reference numeral 98.sub.H and 98.sub.L has a pair of inputs connected across the respective sense resistors 96.sub.H and 96.sub.L. Thus the voltage amplifiers 98.sub.H and 98.sub.L generate on their outputs a voltage signal representing the current through the respective sense resistors 96.sub.H and 96.sub.L.

(39) The outputs of the voltage amplifiers 98.sub.H and 98.sub.L are provided as first inputs to respective multipliers 100.sub.H and 100.sub.L. The second inputs to the respective multipliers 100.sub.H and 100.sub.L are taken from the respective supply voltage levels V.sub.H and V.sub.L. The outputs of the respective multipliers 100.sub.H and 100.sub.L provide a signal representing the power dissipated in the respective output transistors 12 and 14. The power drawn from the rails is measured, which is a proxy for the power dissipated in the drive transistors 12 and 14.

(40) FIG. 9 illustrates an envelope tracking modulated power supply for an RF amplifier incorporating the output stage of the preferred embodiment of the invention described above with reference to FIG. 7.

(41) As can be seen, in FIG. 9 there is further illustrated an RF input signal RF.sub.IN on line 110 representing an RF signal to be amplified. This is provided as an input to an RF power amplifier 114. The RF power amplifier generates an amplified RF output signal RF.sub.OUT on line 112.

(42) The RF input signal RF.sub.IN on line 110 is provided as an input to an envelope detector 118. The envelope detector provides an envelope signal representing an envelope of the RF input signal RF.sub.IN on line 120. Alternatively the envelope signal could be generated from the baseband I and Q data. The envelope signal is provided as an input to a switched mode power supply 122.

(43) The switched mode power supply generates a voltage on its output on line 124, by selecting one of a plurality of available supply voltage levels in dependence on the current amplitude of the envelope signal. This switched mode voltage is connected to one tap of the winding 13 on the second side of the transformer 11.

(44) The transformer 11 combines the voltage generated by the output stage provided at the primary windings of the transformer 11 with the switched mode supply voltage provided at one tap on the secondary winding on line 124, such that an output is provided at the other tap of the secondary winding on line 125 which represents the switched mode supply voltage adjusted or modulated by a correction or error voltage provided by the output stage.

(45) The envelope signal on line 120 is additionally provided as a first input to a subtractor 126. A second input of the subtractor is provided by the output voltage from the transformer 11 at the other tap of the secondary winding 13 on line 126. Thus the output stage, comprised of transistors 12 and 14 and transformer windings 24 and 26, receives as a drive input signal a signal representing the error between the generated output signal and the envelope signal, which the output signal is intended to track. The output stage provides this error signal for combining with the switched mode output voltage on line 124, to generate a corrected output voltage on line 126.

(46) The corrected supply voltage on line 125 provides an envelope tracked power supply for the RF amplifier 114.

(47) It will be understood by one skilled in the art that the arrangement of FIG. 7 represents a simplified implementation of an envelope tracked modulated power supply. For example the signal fed back to the subtractor 126 from line 125 may be scaled. Filter stages may be required in the envelope signal paths to the switched mode power supply and to the output stage comprising transistors 12 and 14. A filter may be required at the output of the switched mode power supply 122.

(48) In the foregoing description reference to the output stage and power dissipated in the output stage includes reference to the drive transistors and reference to any element of the combiner which is used to combine the signals generated by the drive transistors, which elements contribute to dissipated power. In the described embodiment the combiner is identified as a transformer, and the primary windings to which the drive transistors are connected may also contribute to the dissipation of power. However in general the invention is not limited to the use of a transformer as a combiner.

(49) The invention has been described herein by way of general reference to an output stage comprising a push-pull arrangement, which receives a drive signal which is split into two phases for delivery to the two halves of the push-pull output stage. The invention may be applied therefore in any arrangement in which a push-pull arrangement is utilised, particularly but not exclusively where the push-pull arrangement is provided with a drive signal which is asymmetric.

(50) The invention is not limited to the FET implementations described, and may be implemented using bipolar transistors.

(51) Particular advantageous implementations of the invention may exist, such as the implementation in an envelope tracking power supply for an RF (radio frequency) amplifier as discussed hereinabove.

(52) The invention is described herein by way of reference to particular embodiments, but one skilled in the art will appreciate that the invention is not limited to the details of any such embodiments. The scope of the invention is defined by the appended claims.