Drive for cascode stack of power FETs

Abstract

Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between V.sub.max and 2V.sub.max, where V.sub.max is a transistor device rating.

Claims

1. A circuit comprising: a transistor stack comprising a series connection of a first transistor device, a second transistor device, and an output transistor device, the output transistor device having an output terminal and a control terminal, the first transistor device having an input terminal configured for a connection to a control voltage; a capacitive coupling between the control terminal and the output terminal configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal; and a biasing circuit connected to the control terminal of the output transistor device, the biasing circuit configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal substantially with no delay in order to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level.

2. The circuit of claim 1, wherein the second transistor device is a cascode of the first transistor device, wherein the capacitive coupling comprises a first capacitance between the control terminal of the output transistor device and the output terminal of the output transistor device, the circuit further comprising a second capacitance between the input terminal of the first transistor device and the control terminal of the output transistor device.

3. The circuit of claim 1, wherein the capacitive coupling between the control terminal of the output transistor device and the output terminal of the output transistor device comprises a parasitic capacitance between the control terminal and the output terminal.

4. The circuit of claim 1, wherein the capacitive coupling between the control terminal of the output transistor device and the output terminal of the output transistor device comprises a capacitor connected between the control terminal and the output terminal.

5. The circuit of claim 1, further comprising: a fourth transistor device; a fifth transistor device connected as a cascode of the fourth transistor device; a second output transistor device connected as a cascode of the fifth transistor device, the second output transistor device having an output terminal and a control terminal; a capacitive coupling between the control terminal and the output terminal configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal; and a biasing circuit connected to the control terminal, the biasing circuit configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal, the biasing circuit further configured to respond without delay to changes in a voltage level of the drive signal in order to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level.

6. The circuit of claim 5, wherein the capacitive coupling between the control terminal of the second output transistor device and the output terminal of the second output transistor device comprises a parasitic capacitance between the control terminal and the output terminal.

7. The circuit of claim 5, wherein the capacitive coupling between the control terminal of the second output transistor device and the output terminal of the second output transistor device comprises a capacitor connected between the control terminal and the output terminal.

8. A circuit comprising: a first stack comprising a first transistor, a second transistor, and a third transistor, the third transistor comprising a control terminal and an output terminal; a second stack connected to the first stack at a node; a biasing circuit connected to the control terminal of the third transistor; and a capacitive coupling between the control terminal of the third transistor and the output terminal of the third transistor configured to couple an output signal at the output terminal as a coupled signal to the control terminal, the biasing circuit configured to provide a DC bias voltage that combines with the coupled signal to produce a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal with substantially no delay and maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level as the voltage level of the drive signal changes.

9. The circuit of claim 8, wherein the capacitive coupling comprises a parasitic capacitance between the output terminal of the third transistor device and the control terminal of the third transistor device.

10. The circuit of claim 8, wherein the capacitive coupling comprises an explicit capacitor between the output terminal of the third transistor device and the control terminal of the third transistor device.

11. The circuit of claim 8, further comprising a capacitor connected between the first transistor device and the third transistor device.

12. The circuit of claim 8, wherein the second stack comprises: a fourth transistor device; a fifth transistor device connected as a cascode of the fourth transistor device; a sixth transistor device connected as a cascode of the fifth transistor device, the sixth transistor device having an output terminal and a control terminal; a capacitive coupling between the control terminal of the sixth transistor device and the output terminal of the sixth transistor device configured to couple to the control terminal with a coupled signal that continuously tracks an output signal on the output terminal of the sixth transistor device; and a biasing circuit configured to provide a DC bias voltage that combines with the coupled signal to produce a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal substantially with no delay to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level as the voltage level of the drive signal changes.

13. A method in a transistor comprising: providing a divided output signal at an output terminal of the transistor as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal; generating a DC bias voltage; providing a drive signal on the control terminal of the transistor by combining the DC bias voltage with the coupled signal; and responding, substantially without delay, to variations in a voltage level of the drive signal by maintaining a voltage level of the DC bias voltage between a first voltage level and a second voltage level, wherein the capacitive coupling comprises a first capacitor connected between the output terminal and the control terminal and a second capacitor connected between a power rail and the control terminal to define a capacitive voltage divider.

14. The method of claim 13, wherein the first capacitor comprises a parasitic capacitance between the output terminal and the control terminal.

15. The method of claim 14, wherein the first capacitor comprises a physical capacitor.

16. A circuit comprising: means for providing a divided output signal at an output terminal of a transistor in the circuit as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal; means for generating a DC bias voltage; means for providing a drive signal on the control terminal of the transistor by combining the DC bias voltage with the coupled signal; and means for responding, substantially without delay, to variations in a voltage level of the drive signal to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level, wherein the capacitive coupling comprises a first capacitor connected between the output terminal and the control terminal and a second capacitor connected between a power rail and the control terminal to define a capacitive voltage divider.

17. The circuit of claim 16, wherein the first capacitor comprises a parasitic capacitance between the output terminal and the control terminal.

18. The circuit of claim 17, wherein the first capacitor comprises a physical capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings:

(2) FIG. 1 illustrates a high level block diagram of a power supply in accordance with embodiments of the present disclosure.

(3) FIGS. 2 and 2A illustrate cascode stacks in accordance with the present disclosure.

(4) FIG. 3 illustrates an example of a biasing circuit.

(5) FIG. 4 illustrates a conventional design.

DETAILED DESCRIPTION

(6) In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

(7) FIG. 1 shows a switched power supply 10 configured in accordance with the present disclosure to supply an output voltage V.sub.out from an input supply voltage V.sub.in. The configuration shown in FIG. 1 represents a buck converter. However, persons of ordinary skill will appreciate that any switched power supply architecture may be configured in accordance with the present disclosure; e.g., boost converter, Class D amplifier, and the like. A control section 12 may receive the output voltage V.sub.out of the switched power supply 10 as feedback signal to control a gate driver section 14. The gate driver section 14 may generate drive signals 14a to drive a HI-side stack 102 and drive signals 14b to drive a LO-side stack 104. Inductor L and output capacitor C.sub.out may complete the buck converter.

(8) As shown in FIG. 2, in some embodiments, the HI-side stack 102 and LO-side stack 104, each, may comprise a cascode stack configuration. The HI-side stack 102 and LO-side stack 104 may connect at an output node 203. For the purposes of explanation, the supply voltage V.sub.in will be 3V.sub.max and V.sub.out can swing between 0V and 3V.sub.max, where V.sub.max represents the maximum transistor V.sub.gd. For example, if V.sub.max is 1.8V, then V.sub.out can swing from 0V to 5.4V. For a configuration where V.sub.in=3V.sub.max and V.sub.max is 1.8V, HI-side stack 102 may comprise three transistor devices P.sub.1, P.sub.2, P.sub.3. In some embodiments, the transistor devices may be PMOS devices. Likewise, the LO-side stack 104 may comprise three transistor devices N.sub.1, N.sub.2, N.sub.3, which in some embodiments may be NMOS devices. It will be appreciated that the HI-side stack 102 and LO-side stack 104 may be configured with different numbers of transistors depending on parameters such as V.sub.in and V.sub.max.

(9) In some embodiments, the HI-side drive signal 14a may be coupled to the gate of P.sub.1. The HI-side drive signal 14a may be a pulse that swings between 3V.sub.max and 2V.sub.max. The LO-side drive signal 14b may be coupled to the gate of N.sub.1. The LO-side drive signal 14b may be a pulse that swings between 0V and V.sub.max. In accordance with the present disclosure, the gates of P.sub.2 and N.sub.2 are not driven by the gate drive circuitry and may be biased at fixed voltages. In some embodiments, for example, the gate of P.sub.2 may be biased at a fixed DC level of 2V.sub.max, and similarly, the gate of N.sub.2 may be biased at a fixed DC level of V.sub.max.

(10) In accordance with the present disclosure, a biasing circuit 212 may be connected to the gate of P.sub.3. A biasing capacitor C.sub.p may be connected between a supply rail for V.sub.in and the gate of P.sub.3. A biasing circuit 214 may be connected to the gate of N.sub.3, and a biasing capacitor C.sub.n may be connected between ground potential and the gate of N.sub.3. The biasing circuits 212, 214 may be configured as means for generating a DC bias V.sub.bias. V.sub.bias may be a value between 2V.sub.max and V.sub.max. In some embodiments, for example, V.sub.bias may be 1.5V.sub.max.

(11) The drain of P.sub.3 may be capacitively coupled to the gate of P.sub.3, thus coupling an output signal at node 203, as a coupled signal, to the gate of P.sub.3. The output of the biasing circuit 212 may be combined with the coupled signal as means for providing a drive signal on the gate of P.sub.3. Likewise, the drain of N.sub.3 may be capacitively coupled to the gate of N.sub.3, thus coupling the output signal at node 203, as a coupled signal, to the gate of N.sub.3. The output of the biasing circuit 214 may be combined with the coupled signal as means for providing a drive signal on the gate of N.sub.3.

(12) In some embodiments, the parasitic capacitances C.sub.x1, C.sub.x2, respectively, of transistors P.sub.3 and N.sub.3 may provide the respective capacitive coupling. As persons of ordinary skill understand, parasitic capacitances arise within the structures of transistor device, such as the gate and drain regions. In other embodiments, explicit capacitors may used. FIG. 2A for example, illustrates an embodiment using explicit capacitive elements C.sub.1, C.sub.2, in addition to respective parasitic capacitances C.sub.x1, C.sub.x2. The capacitive elements C.sub.1, C.sub.2 are explicit or discrete devices in the same way that the transistors P.sub.3 and N.sub.3 are explicit or discrete devices.

(13) FIG. 3 shows an illustrative example of a biasing circuit 212 shown in FIG. 2, in accordance with some embodiments of the present disclosure. The biasing circuit 214 may be similarly constructed.

(14) The V.sub.bias voltage sets the DC bias level of the biasing circuit 212. Node 302 connects to the gate of P.sub.3, as shown in FIG. 2. When the voltage at the gate of P.sub.3 deviates (up or down) from V.sub.bias by an amount , transistor MN.sub.src or MP.sub.snk will turn ON to compensate. In some embodiments, the may be the transistors' V.sub.th (threshold voltage). In some embodiments, additional compensation (R.sub.src, MP.sub.src and R.sub.snk, MN.sub.snk) can be provided.

(15) In operation, suppose the voltage at node 302 rises above V.sub.bias+, this event will turn ON MP.sub.snk as compensation to drive down the voltage at node 302. When the voltage at node 302 reaches or falls below V.sub.bias+, MP.sub.snk will turn OFF. Depending on how much current is being sinked across R.sub.snk, MN.sub.snk may turn ON as well to provide further compensation.

(16) Conversely, if the voltage at node 302 falls below V.sub.bias, this event will turn ON MN.sub.src as compensation to drive up the voltage at node 302. When the voltage at node 302 reaches or exceeds below V.sub.bias, MN.sub.src will turn OFF. Depending on how much current is being sourced across R.sub.src, MP.sub.src may turn ON as well to provide further compensation.

(17) The biasing circuit 212 shown in FIG. 3 can therefore maintain the DC bias level between V.sub.bias+ and V.sub.bias in real time; the only delay is due to signal propagation delays between the transistor devices that comprise the biasing circuit 212. The biasing circuit 212 illustrates an example of a means for responding, substantially without delay, to variations in a voltage level at node 302 to maintain the DC bias voltage between V.sub.bias+ and V.sub.bias. It will be appreciated of course that the circuit shown in FIG. 3 is merely illustrative of a biasing circuit in accordance with some embodiments of the present disclosure. Persons of ordinary skill can readily implement other equivalent circuits.

(18) A brief discussion of the operation of the cascode stack shown in FIG. 2 will now be given. The gate driver section 14 (FIG. 1) can cycle the HI-side stack 102 and the LO-side stack 104 between a conductive state and a non-conductive state. For example, when the gate driver section 14 drives HI-side stack 102 to be conductive, the LO-side stack 104 is driven non-conductive, and vice-versa when the gate driver section 14 drives HI-side stack 102 to be non-conductive, the LO-side stack 104 is driven conductive.

(19) In a first cycle, for example, suppose the HI-side stack 102 is driven conductive and the LO-side stack 104 is driven non-conductive. On the HI-side stack 102, the gate driver section 14 can drive the gate of P.sub.1 to 2V.sub.max to turn ON P.sub.1. Consequently, the voltage at node 201 will rise to 3V.sub.max. Since the gate of P.sub.2 is DC-biased at 2V.sub.max, P.sub.2 will turn ON. Consequently, the voltage at node 202 will rise to 3V.sub.max.

(20) Recall from the discussion above, that the biasing circuit 212 provides a bias voltage V.sub.bias at the gate of P.sub.3 between 2V.sub.max and V.sub.max. Accordingly, P.sub.3 will turn ON, since node 202 is at 3V.sub.max. As the voltage at node 203 rises to 3V.sub.max, so too will the gate voltage of P.sub.3 rise by virtue of the capacitive coupling (e.g., C.sub.x1), which couples at least a portion of the output voltage at node 203 to the gate of P.sub.3. For example, the bias capacitor C.sub.p and C.sub.x1 (or C.sub.1 in FIG. 2A) may define a capacitive voltage divider configured as means for providing a divided potion of the output voltage a node 203 to the gate of P.sub.3. As a result of the capacitive coupling, the gate voltage at P.sub.3 can track in real time, substantially without delay, the output voltage at node 203 so that V.sub.gd of P.sub.3 does not exceed V.sub.max. Since the biasing circuit 212 is configured to maintain the gate voltage of P.sub.3 between 2V.sub.max and V.sub.max, the gate voltage of P.sub.3 will be limited (clamped) to a maximum voltage of 2V.sub.max as node 203 continues to rise to 3V.sub.max.

(21) Turning to operation of the LO-side stack 104, in the first cycle the gate driver section 14 may drive the LO-side stack 104 to a non-conductive state. The gate driver section 14 may drive the gate of N.sub.1 to ground potential, thus turning OFF N.sub.1. Since the gate of N.sub.2 is DC-biased at V.sub.max, node 205 will rise to V.sub.max, thus ensuring that N.sub.2 is OFF.

(22) At N.sub.3, as the voltage at node 203 rises to 3V.sub.max, so too will the gate voltage of N.sub.3 rise by virtue of the capacitive coupling (e.g., C.sub.x2), which couples at least a portion of the output voltage at node 203 to the gate of N.sub.3. For example, the bias capacitor C.sub.n and the C.sub.x2 (or C.sub.2 in FIG. 2A) may define a capacitive voltage divider that provides a divided potion of the output voltage a node 203 to the gate of N.sub.3. As a result, the gate voltage at N.sub.3 can track in real time substantially without delay the output voltage at node 203 so that V.sub.gd of N.sub.3 does not exceed V.sub.max. Since the biasing circuit 214 is configured to maintain the gate of N.sub.3 between 2V.sub.max and V.sub.max, the gate voltage of N.sub.3 will be limited (clamped) to 2V.sub.max as node 203 continues to rise to 3V.sub.max. The voltage at node 204 will rise to the gate voltage of N.sub.3, namely 2V.sub.max, thus ensuring that N.sub.3 is OFF. By limiting the maximum gate voltage of N.sub.3 to 2V.sub.max, the V.sub.gd of N.sub.3 will not exceed the V.sub.max rating of N.sub.3 when the voltage at node 203 reaches 3V.sub.max.

(23) Consider next a second cycle, that follows the first cycle, in which the HI-side stack 102 can be driven non-conductive and the LO-side stack 104 can be driven conductive. On the LO-side stack 104, the gate driver section 14 may drive the gate of N.sub.1 to V.sub.max, thus turning ON N.sub.1 and bringing node 205 to ground potential. Since the gate of N.sub.2 is DC-biased at V.sub.max, N.sub.2 will also turn ON and bring node 204 to ground potential. Recall from the first cycle, the gate voltage of N.sub.3 is at 2V.sub.max. Accordingly, N.sub.3 turns ON and node 203 will go from 3V.sub.max to ground potential. As the node 203 goes to ground potential, so too will the gate voltage of N.sub.3 as the gate voltage of N.sub.3 tracks in real time substantially without delay the output signal at node 203 by virtue of the capacitive coupling (e.g., C.sub.x2). The biasing circuit 214, however, will limit the minimum voltage level at the gate of N.sub.3 to V.sub.max.

(24) Turning to the HI-side stack 102, in the second cycle the gate driver section 14 can drive the HI-side stack 102 to a non-conductive state. The gate driver section 14 can drive the gate of P.sub.1 to 3V.sub.max, which will turn OFF P.sub.1. With P.sub.1 in the OFF state, the voltage at node 201 will equalize with the gate voltage of P.sub.2, namely 2V.sub.max, thus turning OFF P.sub.2. Likewise, with P.sub.2 in the OFF state, the voltage at node 202 will equalize with the gate voltage at P.sub.3. Recall from the first cycle, the gate voltage of P.sub.3 is at 2V.sub.max, and so the node 202 will become 2V.sub.max, and P.sub.3 will turn OFF.

(25) As the node 203 goes from 3V.sub.max to ground potential, so too will the gate voltage of P.sub.3 as the gate voltage of P.sub.3 tracks in real time substantially without delay the output signal at node 203 by virtue of the capacitive coupling (e.g., C.sub.x1). The biasing circuit 212, however, will limit the minimum voltage level at the gate of P.sub.3 to V.sub.max. By limiting the minimum gate voltage of P.sub.3 to V.sub.max, the V.sub.gd of P.sub.3 will not exceed the V.sub.max rating of P.sub.3 when the voltage at node 203 drops to ground potential.

(26) The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.