Method of Power Factor Correction Burst Mode Load Measurement and Control

Abstract

A power factor correction (PFC) circuit is provided. The PFC circuit includes an input for receiving alternating current and a converter for converting the received alternating current to a direct current. The PFC circuit also includes a direct current link that includes at least one capacitor. Additionally, the PFC circuit includes a voltage regulator control loop operating in burst mode under light load conditions by switching between an ON-state and an OFF-state periodically. The PFC circuit also includes a controller preloading the voltage regulator control loop with an initial value corresponding to the circuit current load under light conditions, when the voltage regulator control loop is transitioning to an ON-state of the burst mode. The initial value is based on the rate of change of the voltage at the direct current link and the capacitance of the capacitor of the direct current link.

Claims

1. A power factor correction circuit comprising: an input for receiving alternating current; a converter for converting the received alternating current to a direct current; a direct current link comprising at least one capacitor; a voltage regulator control loop operating in burst mode under light load conditions by switching between an ON-state and an OFF-state periodically; and a controller preloading the voltage regulator control loop with an initial value corresponding to initial conditions of a circuit current load under light load conditions when the voltage regulator control loop transitions to the ON-state of the burst mode.

2. The power factor correction circuit of claim 1, wherein the controller determines, during the OFF-state of the burst mode, the initial value based on a rate of change of a voltage at the direct current link and a capacitance of the capacitor.

3. The power factor correction circuit of claim 1, wherein after a re-enablement of the power factor correction circuit, the input is based on the initial value.

4. The power factor correction circuit of claim 1, further comprising: a pulse width modulator; a current regulator control loop adjusting a duty cycle of the pulse width modulator based on an output current of the voltage regulator control loop.

5. A method for preloading a voltage regulator control loop of a power factor correction (PFC) circuit with an initial value corresponding to initial conditions of a circuit current load under light load conditions, the method comprising: receiving an alternating current; converting the received alternating current to a direct current; when the voltage regulator control loop transitions to an ON-state of a burst mode, preloading the voltage regulator control loop with the initial value corresponding to initial conditions of the circuit current load under the light load conditions.

6. The method of claim 5, further comprising: determining, during an OFF-state of the burst mode, the initial value based on a rate of change of a voltage at a direct current link and a capacitance of a capacitor of the direct current link.

7. The method of claim 5, wherein when the power factor correction is re-enabled, an input of the power factor correction circuit is based on the initial value.

8. The method of claim 5, further comprising: adjusting, at a current regulator control loop, a duty cycle of a pulse width modulator based on an output current of the voltage regulator control loop.

Description

DESCRIPTION OF DRAWINGS

[0012] FIG. 1A is a schematic view of an exemplary on-board charger.

[0013] FIG. 1B is a schematic view of an exemplary power factor correction circuit of FIG. 1A.

[0014] FIG. 2A is an exemplary graph showing PFC burst mode behavior without the preloading method.

[0015] FIG. 2B is an exemplary graph showing PFC burst mode behavior with the preloading method.

[0016] FIG. 3 is an exemplary graph showing the PFC of FIG. 1 operating in burst mode.

[0017] FIG. 4 is a schematic view of an exemplary arrangement of operations for a method of preloading a voltage regulator control loop of a power factor correction (PFC) circuit with initial values corresponding to initial conditions of the circuit current load under light load conditions.

[0018] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0019] Referring to FIG. 1A, an on-board charger (OBC) 10 is used in electrical vehicles or hybrid vehicles to charge a battery of the vehicle. The OBC 10 converts alternating current (AC) input from the main grid to a direct current (DC) output which charges the vehicle battery. The OBC 10 may run a power factor correction (PFC) circuit 100 to transform the input AC voltage into an intermediate DC voltage, referred to as DC Link, which is used by the DC-to-DC stage to generate the charging current at the output. In some examples, the OBC 10 runs the PFC 100 in “burst mode” at light load to convert the inputted AC power from the AC main to DC power. Burst mode is a mode of operation which uses cycle-skipping to reduce switching losses in a switching regulator and increase operation efficiency at low output current levels.

[0020] FIG. 1B shows the PFC 100 of FIG. 1A. The PFC 100 includes controllers and measurement inputs. The PFC 100 receives power from an AC power supply from the grid that provides an input AC voltage. The received AC power supply is then rectified by a rectifier 110 having a diode bridge. Some PFC topologies may not use a rectifier. The PFC 100 also includes a switch mode power supply which is also referred to as boost converter 120. The boost converter 120 includes an inductor 122, a transistor 124, and a diode 126. Other boost converters may also be used. The boost converter 120 boosts the rectified AC voltage to the DC voltage at a DC Link and regulates the AC input current I.sub.in. The boost converter 120 includes two states of operation. During a first state of operation, a switch of the transistor 124 is closed (i.e., the transistor 124 is ON) and the inductor 122 is charged by the voltage source coming out of the rectifier 110. During a second state of operation, when the switch of the transistor 124 opens (i.e., the transistor 124 is OFF), the energy stored in the inductor 122 during the first state is transferred to the DC Link capacitors 130 through the diode 126, resulting in an increased voltage at an output of the boost converter 120. The injected current from the diode 126 charges the capacitor 130 which maintains the voltage level at the output of the PFC 100 while the inductor 122 recharges. As shown, the capacitor 130 helps smooth an output voltage ripple from the boost converter 120. Regulation of the output voltage V.sub.out is accomplished by controlling (by way of a controller 102) the length of each the first and second states using pulse width modulation (PWM) 180.

[0021] Additionally, the PFC 100 includes a first control loop 140 that includes a first error amplifier 142 and a second control loop 150 that includes a second error amplifier 152. Each of the first and second control loops 140, 150 monitors and regulates the PFC 100. The first error amplifier 142 compares the voltage at the DC Link 130 against a desired reference voltage V.sub.ref (corresponds to the desired V.sub.out). When the voltage at the DC Link 130 is below the reference voltage V.sub.ref, a current output I.sub.142 of the first error amplifier 142 increases; when the voltage at the DC Link 130 is above the reference voltage V.sub.ref, the current output I.sub.142 of the first error amplifier 142 decreases.

[0022] The output of the first control loop 140 is multiplied at a multiplier 160 with a reference sine wave 170 creating the sinusoidal input current reference I.sub.SR for the second control loop 150. The second control loop error amplifier 152 compares the input current I.sub.in with the reference current I.sub.SR and adjusts the duty cycle of the PWM 180 so that the input current I.sub.in matches the reference current I.sub.SR. The amplifiers are described as transconductance amplifiers (voltage input, current output), but may be other types such as those with outputs of voltage or digital count values.

[0023] The amplitude of the current output I.sub.142 of the first control loop 140 is roughly proportional to the amplitude of the input AC current I.sub.in, which is in turn roughly proportional to the load current I.sub.out at the PFC DC Link output. At light load, the current output I.sub.142 of the first control loop is therefore low, and when the current output I.sub.142 falls below a predefined current threshold I.sub.th (I.sub.142 < I.sub.th), the PFC power stage boost converter 120 is disabled and the PFC 100 enters burst mode. The PFC power stage boost converter 120 is then re-enabled when a DC Link voltage V.sub.dc_link (i.e., a voltage of a bank of capacitors of the PFC circuit) falls below a predefined voltage threshold V.sub.th (i.e., V.sub.dc_link <V.sub.th). The PFC 100 will then cycle between enabled and disabled modes and is active only periodically as the DC Link voltage V.sub.dc_link falls below the predefined voltage threshold V.sub.th, and turns off again when the first controller amplifier output I.sub.142 again falls below the predetermined current threshold I.sub.th.

[0024] The first control loop 140 must be disabled during the off part of the burst mode, otherwise the error amplifier 142 of the first control loop 140 continues to integrate the voltage error of the output voltage V.sub.out with respect to V.sub.ref. If the first loop 140 is not disabled during the off burst mode, then when the PFC power stage is re-enabled, the PFC 100 will run at high AC mains input current I.sub.in due to accumulated error at the first control loop 140, which will cause the output voltage V.sub.out (i.e., voltage at the DC_link) to overshoot until the first control loop 140 can recover and reduce the demand of the input current I.sub.in. Conversely, if the first control loop 140 is disabled and reset to too low a value, upon re-enabling of the power stage, in the first control loop 140 there will be a delay to increase demand of the AC mains input current I.sub.in to recharge the DC Link voltage V.sub.out.

[0025] Because the PFC 100 must not introduce harmonic distortion in the input AC current I.sub.in, the first control loop 140 is very slow. The output I.sub.142 of the first control loop 140 must not change significantly over several AC line periods so that, after being multiplied with the reference sine wave 170, the input I.sub.SR to the second control loop 150 remains nearly purely sinusoidal. The bandwidth of the first control loop 140 therefore is typically in the 1 to 10 Hz range. As a result, both burst mode restart strategies described in the previous paragraph would result in large deviations in the DC Link voltage V.sub.DC_link (overshoot and undershoot, respectively). FIG. 2A, shows an example of the over and undershoot showing the DC Link voltage V.sub.DC_link which is the PFC DC Link output voltage V.sub.out, the PFC AC input current I.sub.in, and the first control loop error amplifier output I.sub.142.

[0026] Therefore, in some examples, to overcome the slow behavior of the first control loop 140, the PFC 100 “preloads” the first control loop 140 (with the initial value 140) so that upon re-enabling of the power stage, the ideal AC mains input current I.sub.in is commanded immediately by the PFC 100 and the DC Link 130 begins to recharge at the desired rate. However, the ideal AC mains input current I.sub.in depends on the load demand on the DC Link output V.sub.out. Usually, this information is not available to the PFC controller 102 during the off phase of the burst mode, and would require additional sensing circuitry to implement, which increases cost.

[0027] The PFC 100 may estimate a circuit load based on a slope of discharge of the DC Link voltage V.sub.DC_link at the capacitor 130. The voltage of the DC Link output V.sub.DC_link is known and monitored by the PFC controller 102 at all times, including during the burst off phase. Additionally, the capacitance 130 of the DC Link is known, within some tolerance. During the burst off phase, no energy is transferred to the DC Link capacitors 130 from the disabled PFC power stage boost converter 120, so the capacitor 130 is discharged by the load current I.sub.out on the DC Link 130. Therefore, the relationship of the current flow (i) out of the capacitor bank 130 is equal to the product of the capacitance C of the capacitor 130 and the rate of change of the voltage (dv/dt) at the DC_link, i.e., i = C*dv/dt, Since the dv/dt discharge rate of the capacitors 130 is known by the PFC controller 102 by monitoring DC Link voltage V.sub.DC_link over time, it is used to estimate the current draw from the DC Link. This information is used to determine a correct initial value 104 when re-enabling the PFC 100 power stage converter 120 during burst mode.

[0028] FIG. 3 shows the PFC 100 operating in burst mode. The PFC power stage is active when the DC Link voltage V.sub.dc_link drops below a voltage threshold V.sub.th (i.e., V.sub.dc_link <V.sub.th) and disabled when the first controller current output I.sub.142 falls below a certain threshold (I.sub.142 < I.sub.th). During the disabled time, the PFC controller 102 monitors the DC Link voltage V.sub.dc_link so that the rate of discharge dv/dt may be determined. The load on the PFC 100 during the disabled time is not directly monitored but is proportional to the discharge rate dv/dt because of the i = C * dv/dt relationship, where the capacitance C of the capacitor 130 is assumed to be constant. V.sub.DC_Link shows the voltage at the output of the PFC 100 on the DC Link capacitors 130 charging and discharging during burst on and off phases, respectively. V(PWM) shows the activation of the PFC power stage boost converter 120 during the burst on phase. The first controller amplifier output I.sub.142 is the output of the first controller error amplifier 142, which is zero during the burst off phase, but initialized and preloaded with the initial value 104 corresponding to initial conditions of the circuit current load under light load condition at the start of the burst on phase. As described previously, the load on the PFC 100 during the disabled time is not directly monitored but is proportional to the discharge rate dv/dt because of the i = C * dv/dt relationship, where the capacitance C of the capacitor 130 is assumed to be constant.

[0029] Once the load is determined by the discharge rate dv/dt of the DC Link voltage, the appropriate initial value 104 may be determined by the PFC controller 102. The PFC controller 102 may determine the appropriate initial value 104 either by calculating or by referencing a look up table. The load determined by the discharge rate dv/dt, as well as factors such as AC mains input voltage and DC Link setpoint voltage are used to determine a initial value 104 such that upon re-enabling of the PFC power stage, the DC Link will be recharged at the appropriate I.sub.in for the load on DC Link so that there is no additional undershoot or overshoot, and within a target range of charging rate. The initial value 104 must also be above the threshold for entering burst mode, otherwise the PFC 100 will immediately disable the power stage again upon attempting to re-enable.

[0030] Referring back to FIG. 2B, an example of the result of the described method. V.sub.DC_link is the PFC DC Link output voltage, I.sub.input is the PFC AC input current, and I.sub.142 is the first control loop error amplifier 142 output. In comparison to the example of no preload shown in FIG. 2A, the DC Link output voltage undershoot and overshoot is eliminated in FIG. 2B, and peak input current is also reduced.

[0031] FIG. 4 provides an example arrangement of operations for a method 400 of preloading a voltage regulator control loop 140 of a power factor correction (PFC) circuit 100 with an initial value 104 corresponding to initial conditions of the circuit current load under light load conditions using the system of FIG. 1A-3. At block 402, the method 400 includes receiving, at the PFC 100, alternating current I.sub.in from an AC power supply supplied by the grid that provides an input AC voltage. At block 404, the method 400 includes converting, at a converter 120, the received alternating current I.sub.in to a direct current. method 400 may include reducing, at a boost converter 120, the direct current received from the converter 110. At block 406, the method 400 includes preloading the voltage regulator control loop 140 with the initial value 104, when the voltage regulator control loop 140 transitions to an ON-state of a burst mode.

[0032] In some implementations, the method 400 further includes determining during an OFF-state of the burst mode, the initial value 104 based on a rate of change dv/dt of the voltage at a direct current link DC_Link and a capacitance C of a capacitor 130 of the direct current link DC_Link. In some examples, the when the power factor correction is re-enabled, an input I.sub.in of the PFC circuit is based on the preloaded circuit current load i. The method 400 also includes adjusting, at the current regulator control loop 150, a duty cycle of a pulse width modulator 180 based on an output current of the voltage regulator control loop.

[0033] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.